ECE480/580 Digital Systems Design

Lab 2: Finite State Machine Designs

1. INTRODUCTION

In this lab, you will use the QUARTUS II software package to design and simulate several designs using
basic library functions. The requirements for this lab consist of completing QUARTUS II designs and printing
the VHDL files, functional simulation results and laboratory report. All simulations should be done using the
ModelSim-Altera Simulator. Before beginning the laboratory designs, you should review the simulation of
VHDL designs using the ModelSim Graphical Waveform Editor. The tutorial is available at
http://jjackson.eng.ua.edu/courses/ece480/assignments/ModelSim_GUI_Introduction.pdf.

2. DESIGN

Implement the following circuits using VHDL. Devise a set of test vectors to verify each circuit in simulation.

Finite State Machine for rotating LED display

Design a finite state machine (FSM) using VHDL that implements a rotating light around the LEDs
LEDG[0]-LEDR[17]. The FSM should light one LED after another in the order LEDG[0] to
LEDR[17]. The FSM should change the LEDs either once per second (1 Hz) or ten times per
second (10 Hz) based on the state of KEY[0]. If KEY[0] is not pressed, the segments should
change at a 1 Hz rate. If KEY[0] is pressed, the segments should change at a 10 Hz rate. The state
of KEY[1] will control the rotation direction (pressed=rotate up, not pressed=rotate down). Use the
CLK_DIV library function given on the class website, or similar design, for generating the necessary
clock rates.

View the compilation report files (*.rpt) that are generated when you compile your design for the
Cyclone IV EP4CE115F29C7 device.

The Fitter Report File (*.fit.rpt) summarizes the logic element (LE), memory block, and
interconnect usage for your design. Summarize LE, memory, and interconnect usage for your
design. This information can also be found in the Compilation Report using Processing-
>Compilation Report->Fitter->Summary.

The RTL Viewer (Tools->NetList Viewers->RTL Viewer) and Technology Map Viewer
(Tools-> NetList Viewers->Technology Map Viewer) allow you to view schematic
representations of the internal structure of designs. The RTL Viewer allows you to view a schematic
of the design netlist after analysis and elaboration and netlist extraction, but before Quartus II
synthesis and fitting optimizations. This view is not the final structure of the design because not all
optimizations are included. Instead it is the closest possible view to the original design. The
Technology Map Viewer allows you to view a low-level, technology-specific schematic of the design
netlist after analysis and synthesis, regardless of the synthesis tool you use (Technology Map
Viewer (Post-Mapping)). When opened from a timing path in the Timing Analyzer section the
Report window, the Technology Map Viewer also displays detailed timing delay information for the
timing path. Both viewers will allow for display of the design in a hierarchical fashion and can be
used to confirm HDL code is written correctly and functions as intended. Print the top level hierarchy
shown in both the RTL Viewer and the Technology Map Viewer and include in your report. If the
design contains an arbitrary finite state machine, then the State Machine Viewer Tool (Tools-
>NetList Viewers->State Machine Viewer ) will allow you to view the associate state
diagram for the FSM. If your design includes an arbitrary FSM, print the FSM diagram from the
state machine viewer tool. Simple counters and shift registers will not have an associated FSM.

Choose an appropriate set of test vectors for this design and justify your choice. Download your
design to the Altera development board and test.

Pulse Width Modulated (PWM) Signal Generator

Design a digital circuit using behavioral VHDL that will output a pulse width modulated (PWM)
output to LEDG[0]. The period for the PWM signal should be 10 seconds. A 4-bit signal using
switches SW[3]-SW[0] should be used to define the duty cycle of the output (0000=0% to
1010=100%) in 10% increments.

Choose an appropriate set of test vectors for this design and justify your choice. Download your
design to the Altera development board and test. Modify your design such that eight bits are used
to define the duty cycle of the output (00H=0% to FFH=100%). Download your design to the Altera
development board and test. Provide documentation for both the 4-bit and 8-bit designs.

(Required for ECE580) Stopwatch Design

Construct a stopwatch circuit with the output being displayed on the seven segment displays.
HEX[7]-HEX[6] should display minutes, HEX[5]-HEX[4] should display seconds, and HEX[3]-
HEX[0] should display fractions of seconds (as accurately as possible). The KEY[0] pushbutton
should be used to start the stopwatch and the KEY[1] pushbutton should stop the stopwatch. The
KEY[2] pushbutton should reset the circuit.

HINT: You should consider constructing a multi-digit BCD up counter clocked at an appropriate
clock rate for this design.

Choose an appropriate set of test vectors for this design and justify your choice. Download your
design to the Altera development board and test.

Include all report components in your lab report using the instructions for preparing reports as in
the first laboratory assignment.