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EE415VLSI Design
Manufacturing Manufacturing
Process Process
[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.
and presentation by J.Christiansen/CERN]
EE415VLSI Design
Fabrication
Wafers
Processing
Processed
Wafer
Chips
Masks
EE415VLSI Design
Traditional CMOS Process
EE415VLSI Design
A Modern CMOS Process
p-
p-epi
p well n well
p+ n+
gate oxide
Al (Cu)
tungsten
SiO
2
SiO
2
TiSi
2
Dual-Well Trench-Isolated CMOS
field oxide
EE415VLSI Design
oxidation
optical
mask
process
step
photoresist coating photoresist
removal (ashing)
spin, rinse, dry
acid etch
photoresist
stepper exposure
development
Typical operations in a single
photolithographic cycle (from[ Fullman]).
Photo-Lithographic Process
EE415VLSI Design
Growing the Silicon Ingot
From Smithsonian, 2000
2
EE415VLSI Design
Patterning - Photolithography
1. Oxidation
2. Photoresist (PR) coating
3. Stepper exposure
4. Photoresist development and
bake
5. Acid etching
Unexposed (negative PR)
Exposed (positive PR)
6. Spin, rinse, and dry
7. Processing step
Ion implantation
Plasma etching
Metal deposition
8. Photoresist removal (ashing)
mask
SiO
2 PR
UV light
EE415VLSI Design
CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
Create contact and via windows
Deposit and pattern metal layers
l One full photolithography
sequence per layer
(mask)
l Built (roughly) from the
bottom up
5 metal 2
4 metal 1
2 polysilicon
3 source and drain
diffusions
1 tubs (akawells,
active areas)
exception!
EE415VLSI Design
Example of Patterning of SiO2
Si-substrate
Silicon base material
Si-substrate
3. Stepper exposure
UV-light
Patterned
optical mask
Exposed resist
1&2. After oxidation and
deposition of negative
photoresist
Photoresist
SiO2
Si-substrate
Si-substrate
SiO2
8. Final result after
removal of resist
Si-substrate
SiO2
5. After etching
Hardened resist
SiO
2
Si-substrate
4. After development and
etching of resist, chemical or
plasma etch of SiO
2
Hardened resist
Chemical or plasma
etch
EE415VLSI Design
Diffusion and Ion
Implantation
1. Area to be doped is
exposed
(photolithography)
2. Diffusion
or
Ion implantation
EE415VLSI Design
Deposition and Etching
1. Pattern masking
(photolithography)
2. Deposit material over
entire wafer
CVD (Si
3
N
4
)
chemical deposition
(polysilicon)
sputtering (Al)
3. Etch away unwanted
material
wet etching
dry (plasma) etching
EE415VLSI Design
Planarization: Polishing the
Wafers
From Smithsonian, 2000
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EE415VLSI Design
Self-Aligned Gates
1. Create thin oxide in
the active regions,
thick elsewhere
2. Deposit polysilicon
3. Etch thin oxide from
active region (poly
acts as a mask for the
diffusion)
4. Implant dopant
EE415VLSI Design
Simplified CMOS Inverter
P-well Process
cut line
p well
EE415VLSI Design
P-Well Mask
EE415VLSI Design
Active Mask
EE415VLSI Design
Poly Mask
EE415VLSI Design
P+ Select Mask
4
EE415VLSI Design
N+ Select Mask
EE415VLSI Design
Contact Mask
EE415VLSI Design
Metal Mask
EE415VLSI Design
VLSI Fabrication: The Cycle
EE415VLSI Design
l The n-well CMOS process starts with a
moderately doped (impurity concentration
less than 10
15
cm
-3
) p-type silicon
substrate.
l Then, an oxide layer is grown on the
entire surface. The first lithographic mask
defines the n-well region. Donor atoms,
usually phosphorus, are implanted
through this window in the oxide. This
defines, the active areas of the nMOS and
pMOS transistors.
l Thin gate oxide is grown on top of the
active regions. The thickness and the
quality of the gate oxide are critical
fabrication parameters, since they affect
the characteristics of the MOS transistor,
and its reliability.
CMOS N-well Process (contd)
EE415VLSI Design
CMOS N-well Process (contd)
l The polysilicon layer is
deposited using chemical
vapor deposition (CVD) and
patterned by dry (plasma)
etching.
l The created polysilicon lines
will function as the gate
electrodes of the nMOS and the
pMOS transistors and their
interconnects.
l Also, the polysilicon gates act
as self-aligned masks for the
source and drain implantations
that follow this step.
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EE415VLSI Design
CMOS N-well Process (contd)
l Using a set of two masks, the
n+ and p+ regions are
implanted into the substrate
and into the n- well,
respectively.
l The ohmic contactsto the
substrate and to the n-well are
implanted in this process step.
EE415VLSI Design
CMOS N-well Process (contd)
l An insulating silicon dioxide
layer is deposited over the
entire wafer using CVD.
l Then, the contacts are defined
and etched awayto expose the
silicon or polysilicon contact
windows.
EE415VLSI Design
CMOS N-well Process (contd)
l Metal is deposited over the
entire chip surface using metal
evaporation, and the metal lines
are patterned through etching.
l Since the wafer surface is non-
planar, the quality and the
integrity of the metal lines
created in this step are very
critical and are essential for
circuit reliability.
EE415VLSI Design
CMOS N-well Process (contd)
l The composite layout and the
resulting cross-sectional view of
the chip, showing one nMOS
and one pMOS transistor (built-
in n-well), the polysilicon and
metal interconnections.
l The final step is to deposit the
passivation layer (overglass -
for protection) over the chip,
except for wire-bonding pad
areas.
EE415VLSI Design
Advanced Metallization
EE415VLSI Design
From Design to Reality
6
EE415VLSI Design
Design
Rules
EE415VLSI Design
CMOS Process Layers
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+)
Green
EE415VLSI Design
Layers in 0.25 m
CMOS process
EE415VLSI Design
Design Rules
l Interface between the circuit designer and process
engineer
l Guidelines for constructing process masks
l Unit dimension: minimum line width
scalable design rules: lambda parameter
absolute dimensions: micron rules
l Rules constructed to ensure that design works even
when small fab errors (within some tolerance) occur
l A complete set includes
set of layers
intra-layer: relations between objects in the same layer
inter-layer: relations between objects on different layers
EE415VLSI Design
3D Perspective
Polysilicon
Aluminum
EE415VLSI Design
Why Have Design Rules?
l To be able to tolerate some level of fabrication
errors such as
1. Mask misalignment
2. Dust
3. Process parameters
(e.g., lateral diffusion)
4. Rough surfaces
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EE415VLSI Design
Intra-Layer Design Rule
Origins
l Minimum dimensions (e.g., widths) of objects on each
layer to maintain that object after fab
minimum line width is set by the resolution of the
patterning process (photolithography)
l Minimum spaces between objects (that are not
related) on the same layer to ensure they will not
short after fab
0.3 micron
0.3 micron
0.15
0.15
EE415VLSI Design
Inter-Layer Design Rule
Origins
1. Transistor rules transistor formed by
overlap of active and poly layers
Transistors
Catastrophic
error
Unrelated Poly & Diffusion
Thinner diffusion,
but still working
EE415VLSI Design
Inter-Layer Design Rule
Origins, Cont
2. Contact and via rules
M1 contact to p-diffusion
M1 contact to poly
Mx contact to My
Contact Mask
Via Masks
0.3
0.14
both materials
mask misaligned
M1 contact to n-diffusion
Contact: 0.44 x 0.44
EE415VLSI Design
Intra-Layer Design Rules
Metal2
4
3
10
9
0
Well
Active
3
3
Polysilicon
2
2
Different Potential Same Potential
Metal1
3
3
2
Contact
or Via
Select
2
or
6
2
Hole
EE415VLSI Design
Transistor Layout
1
2
5
3
T
r
a
n
s
i
s
t
o
r
EE415VLSI Design
Viasand Contacts
1
2
1
Via
Metal to
Poly Contact
Metal to
Active Contact
1
2
5
4
3 2
2
8
EE415VLSI Design
Select Layer
1
3 3
2
2
2
Well
Substrate
Select
3
5
EE415VLSI Design
IC Layout
EE415VLSI Design
CMOS Inverter Sticks Diagram
1
3
In Out
V
DD
GND
Stick diagram of inverter
Dimensionless layout entities
Only topology is important
Final layout generated by
compaction program
EE415VLSI Design
CMOS Inverter maxLayout
V
DD
GND
NMOS (2/.24 = 8/1)
PMOS (4/.24 = 16/1)
metal2
metal1
polysilicon
In
Out
metal1-poly via
metal2-metal1 via
metal1-diff via
pfet
nfet
pdif
ndif
EE415VLSI Design
Layout Editor
EE415VLSI Design
Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um.
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EE415VLSI Design
CMOS Inverters
Polysilicon
In
Out
Metal1
V
DD
GND
PMOS
NMOS
1.2 m
=2
EE415VLSI Design
Well-well spacing = 9
M1- M1 spacing = 3
M1width = 4
Active to well edge = 5
Min active width = 3
Poly overlap of active = 2
M2 - M2 spacing = 4
All distances in
Layout Design Rule Violation
EE415VLSI Design
Building an I nverter
A
VCC
VSS
A
Output
Step 1 Step 2
A
Output P
N
A
P diffusion
N diffusion
Step 3 Step 4
VCC
Output
VSS
Withpermissionof WilliamBradbury
EE415VLSI Design
Building a 2 I nput NOR Gate
A A B A B A B B
A
B
Out
P
Output
Sharednode
A B
A
B
P
N N
Step1 Step3
O
u
t
p
u
t
O
u
t
p
u
t
S
h
a
r
e
d
n
o
d
e
V
S
S
V
C
C
V
S
S
Step2
P
N
Step4
V
S
S
O
u
t
p
u
t
V
C
C
Withpermissionof WilliamBradbury
EE415VLSI Design
Building a 2 Input NAND Gate
Withpermissionof WilliamBradbury
A A B A B B
Step1 Step3
O
u
t
p
u
t
O
u
t
p
u
t
S
h
a
r
e
d
n
o
d
e
V
S
S
V
C
C
V
S
S
Step2
P
N
Step4
A B
V
S
S
O
u
t
p
u
t
V
C
C
Sharednode
Output
P B A P
A
N
B
N
A
B
Out
EE415VLSI Design
Combining Logic Functions
Withpermissionof WilliamBradbury
A
Out
B
B
B
B
B
A P
Out
P
B
A
B
N
N
A B
VCC
VSS
B
B
VSS
VCC
Out
A B
Out
B
VSS
VCC
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EE415VLSI Design
Cell Symbol to Logic to
Transistor Schematic to Layout
Withpermissionof WilliamBradbury
INPUT OUTPUT
LD LD
SRAM
OUTPUT
P1.4
N1.4
LD
LD
P1.8
N2.0
P2.0
N2.0
P.5/ 1.0
N.6/ 1.0
INPUT B
A
SRAMBITLOGIC
Minimumpoly width
L =0.20
OUTPUT
SRAMBITTRANSISTORSCHEMATIC
INPUT
P2, 1.8
N2, 2.0
P3, .5/ 1.0
P4, 2.0
N4, 2.0
P1, 1.4
N1, 1.4
LD
LD
B
A
N3, .6/ 1.0
Notethelistingof theL dimension
whichisnot theminimumdefinedby
theprocess
EE415VLSI Design
Schematic to Transistor
Withpermissionof WilliamBradbury
A
INPUT
LD
P1
VCC
A
B
P2
VCC
OUTPUT
B
P4
VCC
A
B
P3
A
INPUT
LD
N1
VSS
A
B
N2
VSS
B
OUTPUT
N4
VSS
A
B
N3
EE415VLSI Design
Assembling the Transistors by
Type and Node Name
Withpermissionof WilliamBradbury
VC
C
A
B
A
IN
PU
T
LD
VC
C
A
B
VCC
O
U
T
P
U
T
B
VSS
A
INPUT
LD
VSS
B
OUTPUT
VS
S
A
B
B
EE415VLSI Design
Connecting the Nodes
Withpermissionof WilliamBradbury
INPUT
VCC A
A
INPUT
LD
A
VC
C
B
B
VCC OUTPUT
B
VSS
A
LD
B
OUTPUT
VSS
A
B
VSS
B
EE415VLSI Design
Connecting the Dotes
Withpermissionof WilliamBradbury
INPUT
V
C
C
A
B
A
I
N
P
U
T
LD
VC
C
B
V
C
C
O
U
T
P
U
T
B
V
S
S A
I
N
P
U
T
LD
V
SS
B
O
U
T
P
U
T
A
B
A
B
A
UNMERGEDDATA:
Noticetheadditionof contacts
wherenecessary andalso theuseof
redundant contactsto improve
reliability
VSS
EE415VLSI Design
Cleaning Connections and
Completing the layout
Withpermissionof WilliamBradbury
.
P-TAP
V
C
C B
A
V
C
C
B
O
U
T
P
U
T
VS
S
A
IN
PU
T
VS
S
B
OU
TP
UT
VS
S
B
A
A
B
OUTPUT INPUT
LD
B
B
B
P-IMPLANT
N-TAP
N-WELL
P1
P2
P
3
P4
N1 N3 N4
N-IMPLANT
N2
VC
C
IN
P
U
T
A
LD
DD
Added:
1.Taps
2.Implants
3.Cell boundry
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EE415VLSI Design
Using sticks
Withpermissionof WilliamBradbury
.
N diffusion
Metal1
P diffusion
Contact
Poly
B A B
VSS
VCC
Output
EE415VLSI Design
Same cell, different shape
Withpermissionof WilliamBradbury
.
A B
B
VSS
VCC VCC
Out
A B
VCC
B
Out B
VSS
B A B
VSS
VCC
Output
EE415VLSI Design
Cells Designed for Sharing
Withpermissionof WilliamBradbury
.
1Bit
1Bit
MemoryRow1
CompareRow1
ReferenceVoltage
Sense
Ckt. for
OneRow
Height of 1
MemoryBit
1Bit
1Bit
MemoryRow1
CompareRow1
ReferenceVoltage
Dual
SenseAmp
Cell Height
CompareRow2
MemoryRow2
ReferenceVoltage
DualSenseAmps Dual WriteLineCkts
CourtesyMentorGraphicsCorp. Layout createdusingIC-Station.
EE415VLSI Design
Cells Designed for Sharing
Withpermissionof WilliamBradbury
.
EE415VLSI Design
Packaging
EE415VLSI Design
Packaging Requirements
l Electrical: Low parasitics
l Mechanical: Reliable and robust
l Thermal: Efficient heat removal
l Economical: Cheap
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EE415VLSI Design
Chip to package connection
l Wire bonding
Only periphery of chip available for IO connections
Mechanical bonding of one pin at a time (sequential)
Cooling from back of chip
High inductance (~1nH)
l Flip-chip
Whole chip area available for IO connections
Automatic alignment
One step process (parallel)
Cooling via balls (front) and back if required
Thermal matching between chip and substrate required
Low inductance (~0.1nH)
EE415VLSI Design
Bonding Techniques
Lead Frame
Substrate
Die
Pad
Wire Bonding
EE415VLSI Design
Tape-Automated Bonding (TAB)
(a) Polymer Tape with imprinted
(b) Die attachment using solder bumps.
wiring pattern.
Substrate
Die
Solder Bump
Film + Pattern
Sprocket
hole
Polymer film
Lead
frame
Test
pads
EE415VLSI Design
New package types
l BGA (Ball Grid Array)
Small solder balls to connect
to board
small
High pin count
Cheap
Low inductance
l CSP (Chip scale Packaging)
Similar to BGA
Very small packages
Package inductance:
1 - 5 nH
EE415VLSI Design
Flip-Chip Bonding
Solder bumps
Substrate
Die
Interconnect
layers
EE415VLSI Design
Package-to-Board Interconnect
(a) Through-Hole Mounting
(b) Surface Mount
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EE415VLSI Design
Package Types
EE415VLSI Design
Package Parameters
EE415VLSI Design
Signal Interface
l Transfer of IC signals to PCB
Package inductance.
PCB wire capacitance.
L - C resonator circuit generating oscillations.
Transmission line effects may generate reflections
Cross-talk via mutual inductance
L
C
Package
Chip
PCB trace
L-C Oscillation
Z
Transmission line reflections
R
f =1/(2(LC)1/ 2)
L = 10 nH
C= 10 pF
f = ~500MHz
EE415VLSI Design
Packaging Faults
Small Ball Chip Scale Packages (CSP) Open
EE415VLSI Design
CSP Assembly on 6mil Viain 12mil pad
Void over via structure
Packaging Faults
EE415VLSI Design
Multi-Chip Modules
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EE415VLSI Design
Multiple Chip Module (MCM)
l Increase integration level of system (smaller size)
l Decrease loading of external signals > higher performance
l No packaging of individual chips
l Problems with known good die:
Single chip fault coverage: 95%
MCM yield with 10 chips: (0.95)
10
= 60%
l Problems with cooling
l Still expensive
EE415VLSI Design
Complete PC in MCM