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Synopsys
VCS/VCSi
Tutorial
Watch Design
UG108 (v1.0) July 28, 2000
Synopsys VCS/VCSi Tutorial www.xilinx.com UG108 (v1.0) July 28, 2000
1-800-255-7778
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4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390;
5,155,432; 5,166,858; 5,224,056; 5,243,238; 5,245,277; 5,267,187; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704;
5,329,174; 5,329,181; 5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153;
5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,399,924; 5,399,925; 5,410,189; 5,410,194; 5,414,377;
5,422,833; 5,426,378; 5,426,379; 5,430,687; 5,432,719; 5,448,181; 5,448,493; 5,450,021; 5,450,022; 5,453,706; 5,455,525; 5,466,117;
5,469,003; 5,475,253; 5,477,414; 5,481,206; 5,483,478; 5,486,707; 5,486,776; 5,488,316; 5,489,858; 5,489,866; 5,491,353; 5,495,196;
5,498,979; 5,498,989; 5,499,192; 5,500,608; 5,500,609; 5,502,000; 5,502,440; 5,504,439; 5,506,518; 5,506,523; 5,506,878; 5,513,124;
5,517,135; 5,521,835; 5,521,837; 5,523,963; 5,523,971; 5,524,097; 5,526,322; 5,528,169; 5,528,176; 5,530,378; 5,530,384; 5,546,018;
5,550,839; 5,550,843; 5,552,722; 5,553,001; 5,559,751; 5,561,367; 5,561,629; 5,561,631; 5,563,527; 5,563,528; 5,563,529; 5,563,827;
5,565,792; 5,566,123; 5,570,051; 5,574,634; 5,574,655; 5,578,946; 5,581,198; 5,581,199; 5,581,738; 5,583,450; 5,583,452; 5,592,105;
5,594,367; 5,598,424; 5,600,263; 5,600,264; 5,600,271; 5,600,597; 5,608,342; 5,610,536; 5,610,790; 5,610,829; 5,612,633; 5,617,021;
5,617,041; 5,617,327; 5,617,573; 5,623,387; 5,627,480; 5,629,637; 5,629,886; 5,631,577; 5,631,583; 5,635,851; 5,636,368; 5,640,106;
5,642,058; 5,646,545; 5,646,547; 5,646,564; 5,646,903; 5,648,732; 5,648,913; 5,650,672; 5,650,946; 5,652,904; 5,654,631; 5,656,950;
5,657,290; 5,659,484; 5,661,660; 5,661,685; 5,670,896; 5,670,897; 5,672,966; 5,673,198; 5,675,262; 5,675,270; 5,675,589; 5,677,638;
5,682,107; 5,689,133; 5,689,516; 5,691,907; 5,691,912; 5,694,047; 5,694,056; 5,724,276; 5,694,399; 5,696,454; 5,701,091; 5,701,441;
5,703,759; 5,705,932; 5,705,938; 5,708,597; 5,712,579; 5,715,197; 5,717,340; 5,719,506; 5,719,507; 5,724,276; 5,726,484; 5,726,584;
5,734,866; 5,734,868; 5,737,234; 5,737,235; 5,737,631; 5,742,178; 5,742,531; 5,744,974; 5,744,979; 5,744,995; 5,748,942; 5,748,979;
5,752,006; 5,752,035; 5,754,459; 5,758,192; 5,760,603; 5,760,604; 5,760,607; 5,761,483; 5,764,076; 5,764,534; 5,764,564; 5,768,179;
5,770,951; 5,773,993; 5,778,439; 5,781,756; 5,784,313; 5,784,577; 5,786,240; 5,787,007; 5,789,938; 5,790,479; 5,790,882; 5,795,068;
5,796,269; 5,798,656; 5,801,546; 5,801,547; 5,801,548; 5,811,985; 5,815,004; 5,815,016; 5,815,404; 5,815,405; 5,818,255; 5,818,730;
5,821,772; 5,821,774; 5,825,202; 5,825,662; 5,825,787; 5,828,230; 5,828,231; 5,828,236; 5,828,608; 5,831,448; 5,831,460; 5,831,845;
5,831,907; 5,835,402; 5,838,167; 5,838,901; 5,838,954; 5,841,296; 5,841,867; 5,844,422; 5,844,424; 5,844,829; 5,844,844; 5,847,577;
5,847,579; 5,847,580; 5,847,993; 5,852,323; 5,861,761; 5,862,082; 5,867,396; 5,870,309; 5,870,327; 5,870,586; 5,874,834; 5,875,111;
5,877,632; 5,877,979; 5,880,492; 5,880,598; 5,880,620; 5,883,525; 5,886,538; 5,889,411; 5,889,413; 5,889,701; 5,892,681; 5,892,961;
5,894,420; 5,896,047; 5,896,329; 5,898,319; 5,898,320; 5,898,602; 5,898,618; 5,898,893; 5,907,245; 5,907,248; 5,909,125; 5,909,453;
5,910,732; 5,912,937; 5,914,514; 5,914,616; 5,920,201; 5,920,202; 5,920,223; 5,923,185; 5,923,602; 5,923,614; 5,928,338; 5,931,962;
5,933,023; 5,933,025; 5,933,369; 5,936,415; 5,936,424; 5,939,930; 5,942,913; 5,944,813; 5,945,837; 5,946,478; 5,949,690; 5,949,712;
5,949,983; 5,949,987; 5,952,839; 5,952,846; 5,955,888; 5,956,748; 5,958,026; 5,959,821; 5,959,881; 5,959,885; 5,961,576; 5,962,881;
5,963,048; 5,963,050; 5,969,539; 5,969,543; 5,970,142; 5,970,372; 5,971,595; 5,973,506; 5,978,260; 5,986,958; 5,990,704; 5,991,523;
5,991,788; 5,991,880; 5,991,908; 5,995,419; 5,995,744; 5,995,988; 5,999,014; 5,999,025; 6,002,282; and 6,002,991; Re. 34,363, Re. 34,444,
and Re. 34,808. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free
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UG108 (v1.0) July 28, 2000 www.xilinx.com Synopsys VCS/VCSi Tutorial
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Synopsys VCS/VCSi Tutorial
UG108 (v1.0) July 28, 2000
The following table shows the revision history for this document.
Date Version Revision
07/28/00 1.0 Initial Xilinx release.
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Preface .................................................................................iv
About This Manual ............................................................................................iv
Manual Contents ............................................................................................................. iv
Conventions ........................................................................vi
Typographical ...................................................................................................... v
Online Document ...............................................................................................vi
Synopsys VCS/VCSi Tutorial ..............................................1
Design Description ............................................................................................. 1
Inputs ................................................................................................................................ 1
Outputs ............................................................................................................................. 1
Functional Blocks ............................................................................................................ 2
Before Beginning the Tutorial .......................................................................... 2
Tutorial Installation ............................................................................................ 2
Tutorial Directory and Files ........................................................................................... 2
Copying the Tutorial Files ............................................................................................. 3
Verilog Design Files ........................................................................................................ 3
Script Files ........................................................................................................................ 3
Verilog Libraries .................................................................................................. 3
UniSim Library ................................................................................................................ 3
CORE Generator Library ................................................................................................ 3
SimPrim Library .............................................................................................................. 4
Creating the Tenths CORE Generator Component ...................................... 4
Instantiating the CORE Generator Module ................................................... 7
RTL Simulation ................................................................................................... 7
Using the glbl.v Module ................................................................................................. 8
Running Verilog Simulation .......................................................................................... 8
Using Library Source Files with Compile Time Options .......................................... 8
Using Shared Pre-compiled Libraries .......................................................................... 8
Compiling the Verilog Libraries ................................................................................... 9
Starting VirSim .................................................................................................... 9
Copying Source Files to the RTL Simulation Directory ............................................ 9
Invoke the Simulator .................................................................................................... 10
Viewing the Simulation ................................................................................................ 10
Implementing the Watch Design ................................................................... 13
Verilog Timing Simulation ............................................................................. 14
Contents
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Preface
About This Manual
This manual is a tutorial that describes how to use Synplicity Synplify (VHDL) for
XC4000E/EX/XL/XV designs using MTI for simulation.
Before using this manual, you should be familiar with the operations that are common to
all Xilinx software tools: how to bring up the system, select a tool for use, specify
operations, and manage design data. These topics are covered in the Quick Start Guide.
You must consult The Programmable Logic Data Book for device-specific information on
Xilinx device characteristics, including readback, boundary scan, configuration, length
count, and debugging. The Programmable Logic Data Book is available in hard copy and on
the Xilinx web site (http://www.xilinx.com). See
http://www.xilinx.com/partinfo/databook.htm for the current version of this book.
For specific design issues or problems, use the Answers Search function on the Web
(http://www.xilinx.com/support/searchtd.htm) to access the following:
Answers Database: current listing of solution records for the Xilinx software tools
Applications Notes: descriptions of device-specific design techniques and approaches
Data Sheets: pages from The Programmable Logic Data Book
XCELL Journal: quarterly journals for Xilinx programmable logic users
Expert Journals: the latest news, design tips, and patch information on the Xilinx
design environment
If you cannot access the Web, you can install and access the Answers book with the
DynaText online browser in the same manner as the Xilinx book collection. The Answers
book includes information in the Answers Database at the time of this release.
Manual Contents
This manual covers the following topics.
Synopsys VCS/VCSi Tutorial, describes how to use Exemplar Leonardo/Galileo
Extreme (VHDL) for XC4000E/EX/XL/XV designs using MTI for simulation. It is based
on the Watch design.
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Conventions
Typographical
This manual uses the following conventions. An example illustrates each convention.
Courier font indicates messages, prompts, and program files that the system
displays.
speed grade: -100
Courier bold indicates literal commands that you enter in a syntactical statement.
However, braces { } in Courier bold are not literal and square brackets [ ] in
Courier bold are literal only in the case of bus specifications, such as bus [7:0].
rpt_del_net=
Courier bold also indicates commands that you select from a menu.
File Open
Italic font denotes the following items.
Variables in a syntax statement for which you must supply values
edif2ngd design_name
References to other manuals
See the Development System Reference Guide for more information.
Emphasis in text
If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.
Square brackets [ ] indicate an optional entry or parameter. However, in bus
specifications, such as bus [7:0], they are required.
edif2ngd [option_name] design_name
Square brackets also enclose footnotes in tables that are printed out as hardcopy in
DynaText

.
Braces { } enclose a list of items from which you must choose one or more.
lowpwr ={on|off}
A vertical bar | separates items in a list of choices.
lowpwr ={on|off}
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A vertical ellipsis indicates repetitive material that has been omitted.
IOB #1: Name = QOUT
IOB #2: Name = CLKIN
.
.
.
A horizontal ellipsis . . . indicates that an item can be repeated one or more times.
allow block block_name loc1 loc2 ... locn;
Online Document
Xilinx has created several conventions for use within the DynaText online documents.
Red-underlined text indicates an interbook link, which is a cross-reference to another
book. Click the red-underlined text to open the specified cross-reference.
Blue-underlined text indicates an intrabook link, which is a cross-reference within a
book. Click the blue-underlined text to open the specified cross-reference.
There are several types of icons.
Iconized figures are identified by the figure icon.
Iconized tables are identified by the table icon.
The Copyright icon displays in the upper left corner on the first page of every Xilinx
online document.
The DynaText footnote icon displays next to the footnoted text.
Double-click these icons to display figures, tables, copyright information, or footnotes
in a separate window.
Inline figures display within the text of a document. You can display these figures in a
separate window by clicking the figure.
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Synopsys VCS/VCSi Tutorial
This tutorial shows you how to use Synopsys VCS/VCSi for simulation. It guides you
through a typical FPGA HDL-based design procedure using an unfinished design that you
download from the Xilinx Web site. The tutorial design is named watch and is intended
to perform like a track coach's stopwatch. This tutorial contains the following sections.
Design Description
Before Beginning the Tutorial
Tutorial Installation
Verilog Libraries
Creating the Tenths CORE Generator Component
Instantiating the CORE Generator Module
RTL Simulation
Starting VirSim
Implementing the Watch Design
Verilog Timing Simulation
Design Description
The design used in this tutorial is a hierarchical, HDL-based design. The top-level design
file is an HDL file that references several other lower-level macros. The lower-level macros
are either HDL modules or CORE Generator modules.
The tutorial begins with an unfinished design. You will complete the design by generating
some of the modules from scratch, and by completing other modules from existing files.
When the design is complete, it is simulated to verify functionality.
The Watch design is intended to perform like a track coachs stopwatch. There are three
external inputs, and three external output buses in the completed design. The system clock
is an externally generated signal. The inputs, outputs, and functional blocks are listed
below.
Inputs
STRTSTOP This is an active low signal that starts and stops the stopwatch.
RESETResets the stopwatch to 00.0 after it has been stopped.
CLKExternally generated system clock.
Outputs
TENSOUT[6:0]7-bit bus that represents the tens digit of the stopwatch value. This
bus is in 7-segment display format as viewable on the 7-segment LED display on the
Xilinx demonstration board.
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ONESOUT[6:0]Similar to TENSOUT, but represents the ones digit of the stopwatch
value.
TENTHSOUT[9:0]10-bit one-hot encoded bus that represents the tenths digit of the
stopwatch value.
Functional Blocks
STATMACH
State Machine module.
CNT60
HDL-based module that counts from 0 to 59 in decimal. This macro has two 4-bit
outputs that represent the ones and tens digits of the decimal values, respectively.
TENTHS
CORE Generator 4-bit, binary encoded counter. This macro outputs a 4-bit code that is
decoded to represent the tenths digit of the stopwatch value as a 10-bit one-hot
encoded value.
HEX2LED
HDL-based macro. This macro decodes the ones and tens digit values from
hexadecimal to 7-segment display format.
SMALLCNTR
A simple counter.
Before Beginning the Tutorial
Before you begin this tutorial, set up your system to use the Synopsys and Xilinx software
as follows.
1. Install the following software.
- Xilinx Development System 3.1i
- Synopsys VCS/VCSi 5.2 or later
2. Verify that your system is properly configured. Consult the release notes and
installation notes that came with your software package for more information.
Tutorial Installation
The Watch tutorial file is available for download from the Xilinx Web site at
http://support.xilinx.com/support/techsup/tutorials.
Tutorial Directory and Files
The tutorial directory and files needed to complete the design are provided for you. The
following table lists the contents of the tutorial directories.
Directory Description
vcs_vlog/watch working directory
vcs_vlog/watch_source Verilog source and script files
vcs_vlog/watch_solution Verilog solution files
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Copying the Tutorial Files
In this tutorial, watch is the name of the directory where the tutorial will be performed.
Copy all of the files from the vcs_vlog/watch_source directory to the vcs_vlog/watch
directory.
Verilog Design Files
Watch is the top-level design. The tutorial uses the following Verilog files.
stopwatch.v
statmach.v
smallcntr.v
decode.v
cnt60.v
hex2led.v
stopwatch_tb.v (Verilog test fixture for simulation)
Script Files
The following script files are provided to automate the steps in this tutorial.
rtl_sim.f
time_sim.f
Verilog Libraries
To simulate the Watch design, you need the following simulation libraries.
UniSim Library
The UniSim library is used for functional simulation only. The models in this library
contain only unit delays. This library includes all Xilinx Unified Library primitives that are
inferred by most popular synthesis tools.
For Verilog, separate libraries are provided for common technologies that share the same
functionality. This combined library makes it easy to retarget designs to other technologies.
It is not necessary to change the library mapping statements when switching from Virtex
to Virtex-E or from Spartan to Virtex.
The Verilog UniSim Library source files are provided in $XILINX/verilog/src/unisims
(Series 4KE, 4KX, 4KL, 4KXV, Spartan, Virtex).
CORE Generator Library
CORE Generator is a graphical interactive design tool for creating high-level modules such
as counters, shift registers, RAM and multiplexers. You can customize and pre-optimize
the modules to take advantage of the inherent architectural features of FPGAs, such as Fast
Carry Logic for arithmetic functions, and on-chip, dual-port and synchronous RAM. You
can also select the appropriate HDL model type as output.
The CORE Generator HDL library models are used for RTL simulation. The models do not
use library components for global signals.
The Verilog CORE Generator source files are provided in
$XILINX/verilog/src/XilinxCoreLib.
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SimPrim Library
The SimPrim library is used for post-NGDBuild (gate-level functional), post-Map (partial
timing), and post-PAR (full timing) simulations. This library is architecture independent.
The Verilog SimPrim Library source files are provided in $XILINX/verilog/src/simprims.
Creating the Tenths CORE Generator Component
If you have previously created the CORE Generator component, you may skip this section
without loss of contiuity in the tutorial.
The first step in this tutorial is creating the CORE Generator component. When you create
the component, you will create a behavioral simulation netlist for RTL simulation and an
implementation netlist.
The CORE Generator module is named Tenths, and is a 4-bit binary encoded counter. The
4-bit number is decoded to count the tenths digit of the stopwatch time value.
To create the CORE Generator component, follow these steps.
1. To invoke the CORE Generator, type coregen at the UNIX prompt, or if you are
using a PC, click on the CORE Generator icon in the Xilinx Program group.
2. From Project Project Options, select Verilog and your synthesis vendor of
choice for your design entry.
3. In the Target Architecture field, select Virtex.
4. Click OK to close the dialog box.
5. A list of possible COREs are available. Double click on Basic Elements -
Counters.
6. Double click on Binary Counter to open the Binary Counter dialog box. This dialog
box allows you to customize the counter to the design specifications.
7. Fill in the Binary Counter dialog box with the following settings.
- Component Name: tenths
Defines the name of the module.
- Output Width: 4
Figure 1: CORE Generator Setup Dialog
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Defines the width of the output bus.
Operation: Up
Defines how the counter will operate. This field is dependent on the type of
module you select.
- Count Restrictions: Restrict Count to A
This specifies the maximum count value.
- Output Options: Threshold 0 set to A
Signal goes high when the value specified has been reached.
- Output Options: Registered
8. Click on the Register Options button to open the Register Options dialog box.
Enter the following settings.
- Clock Enable: Selected
Asynchronous Settings: Init with a value of 1
Synchronous Settings: None
Click OK.
Figure 2: CORE Generator Module Selection
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9. Check that only the following pins are used.
- AINIT
- CE
- Q
- Q_Thresh0
- CLK
10. Click Generate to create the module.
11. Select Cancel and close CORE Generator.
CORE Generator generates the following output files.
- tenths.edn
Netlist file that is used during the Translate phase of implementation
- tenths.veo
Instantiation template that is used to incorporate the CORE Generator module in
your source Verilog file
- tenths.xco
Stores the configuration information for the Tenths module
- coregen.prj
Stores the CORE Generator configuration for the project
Figure 3: Register Options Dialog
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Instantiating the CORE Generator Module
If you have previously instantiated the CORE Generator component, you may skip this
section without loss of contiuity in the tutorial.
To instantiate the CORE Generator module, you must copy information from the
tenths.veo file to the stopwatch.v file, as described in the following steps.
1. Open stopwatch.v in your favorite editor, and then open the tenths.veo file. Copy the
module declaration from the tenths.veo file to the stopwatch.v file at the following
location.
// Place the Coregen Module Declaration for Tenths here
The template module declaration for the Coregen instantiation is inserted.
2. From the tenths.veo file, copy from the line Tenths your_instance_name to
.AINIT=(AINIT)); to stopwatch.v at the following location.
3. --Place the CoreGen Component Instantiation for Tenths here.
4. In the stopwatch.v file, change your_instance_name to XCOUNTER.
5. Edit the following code in the stopwatch.v file to connect the signals in the stopwatch
design to the ports of the CoreGen module.
tenths XCOUNTER (.Q(Q), .CLK(CLK), .Q_THRESH0(xtermcnt), .CE(clkenable),
.AINIT(rstint));
6. Save stopwatch.v and exit the editor.
RTL Simulation
RTL-level (behavioral) simulation allows you to verify or simulate a description at the
system or chip level. This first pass simulation is typically performed to verify code syntax,
and to confirm that the code is functioning as intended. At this step in the tutorial, no
timing information is provided and simulation is performed in a unit-delay mode to avoid
the possibility of a race condition.
RTL simulation is not architecture-specific unless the design contains instantiated UniSim,
CORE Generator, or LogiBLOX components.
A general suggestion during the initial design creation is to keep the code behavioral.
Avoid instantiating specific components unless necessary. This allows for more readable
code, faster and simpler simulation, code portability (the ability to migrate to different
device families) and code reuse (the ability to use the same code in future designs).
However, you may find it necessary to instantiate components structurally in order to
obtain the desired design structure or performance.
It is important to address the built-in reset circuitry behavior in a design starting with the
first simulation to ensure that subsequent simulations agree at different points.
Virtex devices have register (flip-flops and latches) set/reset circuitry that pulses at the end
of the configuration mode. This pulse is automatic and does not need to be programmed.
All the flip-flops and latches receive this pulse through a dedicated global set/reset (GSR).
The registers either set or reset, depending on how the registers are defined.
If the you do not simulate GSR behavior prior to synthesis and PAR, the RTL and possibly
post-synthesis simulations will not initialize to the same state as the post-route timing
simulation. As a result, various design descriptions are not functionally equivalent and
simulation results will not match.
Even if GSR behavior is not described, the actual chip initializes during configuration, and
the post-route netlist will have this net that must be driven during simulation.
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In addition to the set/reset pulse, all output buffers are tristated during configuration
mode with the dedicated global output tristate enable (GTS) net.
Using the glbl.v Module
The general procedure for specifying global signals for a Verilog simulation flow includes
defining the global signals with the $XILINX/verilog/src/glbl.v module. This module
allows a global signal to be modeled as a wire in a global module. The glbl.v module
enables the use of the global set/reset in the design, and it is referenced by the UniSim and
SimPrim libraries.
The glbl.v module must be loaded in the simulation process.
Running Verilog Simulation
There are two methods for running Verilog simulation. You can use library source files
with compile time options, or you can use shared pre-compile libraries.
VCS and VCSi are identical except that VCS is more highly optimized, resulting in greater
speed for RTL and mixed level designs. Pure gate level designs run with comparable
speed. VCS and VCSi are guaranteed to provide the exact same simulation results. VCSi is
invoked using the vcsi command instead of vcs.
Hereafter, all references to VCS in this manual pertain to VCSi as well.
Using Library Source Files with Compile Time Options
Depending on the type of design (Xilinx instantiated primitives, or CORE Generator
components) for RTL simulation, specify the following at the command-line:
vcs -y $XILINX/verilog/src/unisims +incdir+$XILINX/verilog/src +libext+.v
$XILINX/verilog/src/glbl.v -Mupdate -R testfixture.v design.v
For timing simulation or post-Ngd2ver, the Simprims-based libraries are used. Specify the
following at the command-line:
vcs +compsdf -y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v
+libext+.v -Mupdate -R testfixture.v time_sim.v
The -R option automatically simulates the executable after compilation .
The -Mupdate option enables incremental compilation. Modules will be recompiled
because of one of the following reasons:
1. Target of a hierarchical reference has changed.
2. Some compile time constant such as a parameter has changed.
3. Ports of a module instantiated in the module has changed.
4. Module inlining. For example, merging, internally in VCS, of a group of module
definitions into a larger module definition which leads to faster simulation. These
affected modules are again recompiled. This is done only once.
Using Shared Pre-compiled Libraries
Depending on the type of design (Xilinx instantiated primitives, or CORE Generator
components) for RTL simulation, specify the following at the command-line:
vcs -Mupdate -Mlib=<compiled_dir>/unisims_ver -y
$XILINX/verilog/src/unisims -Mlib=<compiled_dir>/xilinxcorelib_ver
+incdir+$XILINX/verilog/src +libext+.v $XILINX/verilog/src/glbl.v -R
testfixture.v design.v
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For timing simulation or post-Ngd2ver, the Simprims-based libraries are used. Specify the
following at the command-line:
vcs +compsdf -Mupdate -Mlib=<compiled_lib_dir>/simprims_ver -y
$XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v +libext+.v -R
testfixture.v time_sim.v
The -R option automatically simulates the executable after compilation. Finally, the -
Mlib=<compiled_lib_dir> option provides VCS with a central place to look for the
descriptor information before it compiles a module and a central place to get the object files
when it links together the executable.
The -Mupdate option enables incremental compilation. Modules will be recompiled
because of one of the following reasons:
1. Target of a hierarchical reference has changed.
2. Some compile time constant such as a parameter has changed.
3. Ports of a module instantiated in the module has changed.
4. Module inlining. For example, merging, internally in VCS, of a group of module
definitions into a larger module definition which leads to faster simulation. These
affected modules are again recompiled. This is done only once.
Compiling the Verilog Libraries
For VCS/VCSi, you may need to compile the HDL libraries before using them for design
simulations. The advantages of the compiled approach are speed of execution and
economy of memory.
Xilinx provides a utility to compile the HDL libraries for the VCS simulator. This utility is
available at $XILINX/bin/platform/compile_hdl.pl
Starting VirSim
VirSim is the graphical debug and analysis environment designed to operate with the VCS
simulator. If you are using the PC, invoke the simulator by selecting the following from the
Start menu.
Programs Synopsys VCS VIRSIMS Verilog Debugger
For UNIX workstations, enter the -RI option on the VCS command-line.
vcs -RI
Use the -RI if you want access to the complete environment. This invokes the VirSim main
window. The other components of the VirSim environment (Interactive Window,
Hierarchy Browser, Waveform Window, Register Window, Source Window, and the Logic
Browser windows) are all accessible through the Main Menu.
Copying Source Files to the RTL Simulation Directory
For the Verilog tutorial, copy the following files into the vcs_vlog/watch/rtl directory
from the vcs_vlog/watch_source/rtl directory.
stopwatch.v
statmach.v
smallcntr.v
decode.v
cnt60.v
hex2led.v
stopwatch_tb.v
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rtl_sim.f
glbl.v
Invoke the Simulator
Copy the $XILINX/verilog/src/glbl.v file to your working directory.
Type the following at the command-line prompt to invoke the VCS simulator.
vcs -RI -y $XILINX/verilog/src/unisims
+incdir+$XILINX/verilog/src +libext+.v -f rtl_sim.f
Viewing the Simulation
1. Launch the Hiearchy window from the Hiearchy button.
Figure 4: VirSim Cockpit
Figure 5: Hierarchy Window
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2. Expand to the test scope to see its signals by clicking the Hierarchy Tree button. The
Signal Select box now displays the available signals for the currect scope.
3. Select all signals in the Signal Select box by selecting the first entry and dragging
through the list.
4. Add the signals from the selected region to a group by clicking the Add button. The
default group is AutoGroup0.
5. In the VirSim Main Window, launch the Waveform window from the Waveform
button.
6. Populate the Waveform Window with the default group name by clicking the Select a
Signal Group button.
Figure 1: Hierarchy Tree Button
Figure 2: Select a Signal Group Button
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7. To run the simulation, type a period at the cli_1> prompt in the Interactive Window.
Figure 3: Interactive Window Dialog
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8. The simulation output is displayed in the Wave window. You may have to zoom in or
out to view the waveforms.
Implementing the Watch Design
To implement the Watch design, refer to the Xilinx Design Manager Tutorial. You need the
following files for implementation.
watch.edf
tenths.edn
Before you implement the Watch design with the Xilinx Design Manager, you need to set
the Implementation Options Timing Template to VCS to produce the time_sim.v file, and
time_sim.sdf for timing simulation. To set these options, follow these steps.
1. In the Design Manger Implement window, select Design Options to open the
Options dialog box.
2. In the Program Options section of the dialog box, set Simulation to VCS.
Figure 4: Simulation Output in Wave Window
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3. Proceed with the Design Manager Tutorial.
Note: Although not included in this tutorial, it is possible to run a post-NGDBuild and post-Map
simulation, which may be helpful for debugging the design.
Verilog Timing Simulation
You need two files from the Xilinx tools.
time_sim.v
time_sim.sdf
To perform timing simulation, follow these steps.
1. Copy time_sim.v, time_sim.sdf, and testfixture.v to the following directory.
vcs_vlog/watch/time_sim
At this point, the HDL netlist has been resolved into simulation primitives, and the
next step is to provide the simulation models of the SimPrim library.
2. Navigate to the vcs_vlog/watch/time_sim directory.
3. Read in the SDF file for timing simulation. NGD2VER automatically writes out a
directive, $sdf_annotate, within the time_sim.v file. This directive specifies the
appropriate SDF file to use in conjunction with the generated netlist. Consequently,
you do not need to specify an option for VCS to read the SDF, but you do need the
+compsdf plus option to compile the SDF file.
vcs -RI +compsdf -y $XILINX/verilog/src/simprims +libext+.v -f
time_sim.f
4. View and add the signals of the design to the waveform window by following steps
outlined in the RTL simulation section.
5. After simulating, you can zoom in and view the delay from the clock edge to the
TENSOUT, ONESOUT, and TENTHSOUT output change.
The Synopsys VCS/VCSi/Xilinx Tutorial is now completed!
Figure 5: Design Manager Options Dialog Box