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The University of the South Pacific

Embedded Systems

LABORATORY 4 Date: August 2014 Dr. ASSAF M.

Four-bit Adder Design and Implementation

Overview
In this experiment you will learn to design and implement a simple logic circuit using the ISE
tool and the Adept software. You will generate a bitstream representing your design, program,
and test your design on the Atlys Spartan-6 Development Board.

Methodology
The following primary steps are to be executed in order to download design onto the
Development Board:
1) Creating the project using the ISE tool.
2) Adding Source (Hardware/logic).
3) Assigning Pins using the PlanAhead software.
4) Generating design schematic.
5) Analyzing the created project.
6) Creating a bitstream.
7) Configure and test the Atlys Spartan-6 Development Board.
8) Download bitstream onto the Development Board using the Adept software.
9) Verifying design on the Development Board.











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Create a new project and name it fourbit_adder.




3

Select Project.

Select Add Source.
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Copy files full_adder.vhd and fourbit_adder.vhd in working directory.



Select files full_adder.vhd and fourbit_adder.vhd -> click Open.
Explain the two VHDL codes full_adder.vhd and fourbit_adder.vhd.
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Notice added VHDL files.

Draw the 1-bit Full Adder and the 4-bit Adder circuit diagrams.
Double click Implement Design.

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Expand (+) User Constraints -> Double-click on I/O Pin Planning (PlanAhead) - Post-
Synthesis.
Explain the role of design constraints.
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PlanAhead software is launched.
What role does the PlanAhead software play?
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Expand a(4).
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Select desired pin number (Site) -> check the pin number (Fixed).


Repeat for the rest of the signals a, b, z, and cout using the pin numbers as shown the figure
below that shows the connection of the pushbuttons, slide switches, and LEDs to the Spartan-6
(FPGAs) pins:

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The PlanAhead window should look like:

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Explain the above schematic.
Zoom-in multiple times.
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In the Package window zoom-in to pin A10 and verify that it is assigned to a[0]. You should
see a[0] written inside the cell at location row A column 10.

Verify the correct assignment of the other pins (a[1], a[3], a[3], b[0], b[1], b[2], b[3], b[4],
z[0], z[1], z[2], z[3], and cout) as well.
Select File -> Save Constraints.
Select File -> Exit.
Select OK.
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Re-implement design by double-clicking on Implement Design.

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Double-click on Generate Programming File.

Select Tools -> Schematic Viewer -> RTL
What does RTL stand for?
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Click Ok.



Expand the (+) sign of the Signals area, select all of the signals, and click the Add -> button.
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Click Create Schematic.



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Describe in details the generated schematic.
Click on Generate Programming file.

Power on Spartan-6 board and connect USB cable to PROG port and to PC.
Open Digilent Adept software.
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Select Browse and locate the generated bit file (fourbit_adder.bit).
What does a (.bit) file represent?


Click Program.
What is the role of the Program button?
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Once the programming is finished, and if successful, the Adept software should print the
message Programming Successful and LED (DONE) is lit on the board.

To verify that the four-bit adder works correctly, use the slide switches to set inputs a and
b and watch the LEDs. Try different combinations of input values.
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For example, if we wanted to test a = 2, b = 5, a + b = 7 we would set input a = 0010 and b =
0101 via the slide switches and the output should turn ON the LEDs (LD2, LD1, and LD0) as
shown in the figure below:




Turn off power then power on again the Spartan-6 board. Re-verify the four-bit adder
operations by trying different combinations of input values and observing the output LEDs.
Explain whats happening.


Conclusions
The ISE tools were used to create and analyze a simple project. The PlanAhead software was
used to assign pins, verify pin assignments, and generate design schematic. Then the Adept
software was used to configure and test the Atlys Spartan-6 Development Board.



References
[1] Atlys schematics http://www.digilentinc.com/Data/Products/ATLYS/Atlys_C2_sch.pdf
[2] Atlys reference manual http://www.digilentinc.com/Data/Products/ATLYS/Atlys_rm.pdf
[3] "Xilinx ISE Webpack 11". Gentoo Wiki. Gentoo Community, 2012.
[4] "Adept Application Users Manual, Digilent, 2010.