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CHAPTER 13 OUTPUT STAGES AND POWER AMPLIFIERS

Chapter Outline

13.1 Classification of Output Stages

13.2 Class A Output Stage

13.3 Class B Output Stage

13.4 Class AB Output Stage

13.5 Biasing the Class AB Circuit

13.6 CMOS Class AB Output Stages

13.1 CLASSIFICATIONS OF OUTPUT STAGES

Output Stages

Class A output stage:

Bias current is greater than the magnitude of the signal current

Conduction angle is 360

Class B output stage:

Biased at zero dc current

Conduction angle is 180

Another transistor conducts during the alternate half-cycle

Class AB output stage:

An intermediate class between A and B

Biased at a nonzero dc current much smaller than the peak current of the signal

Conduction angle is greater than 180but much smaller than 360

Two transistors are used and currents are combined at the load

Class C output stage:

Conduction angle is smaller than 180

The current is passed through a parallel LC network to obtain the output signal

Class A, B and AB are used as output stage of op amps

Class AB amplifiers are preferred for audio power amplifier

Class C amplifiers are usually used at higher frequencies

Collector current waveforms for the transistors operating in different classes

The classification also applies for output stages with MOSFETs 13.2 CLASS A OUTPUT STAGE

Transfer Characteristics

Q 1 biased with a constant current I supplied by Q 2

v

v

O

O

v v V

I

BE1

CC

max

V

CE sat

1

v

|

  IR

L

V

CC

or

V

O

min

I

v

O

min

|

CE sat

2

R

L

V

 

CC

V

CE sat

2 Signal Waveforms

The output swing from V CC to V CC for I = V CC / R L

The instantaneous power dissipation in Q 1 : P D1 = v CE1 i C1   Power Dissipation Power dissipation for R L = V CC / I:

The maximum instantaneous power dissipation in Q 1 is V CC I

This is equal to the power dissipation in Q 1 with no input signal applied (quiescent power dissipation)

The transistor Q 1 much be able to withstand a continuous power dissipation of V CC I

p

Maximum power dissipation occurs when v O = V CC

The maximum

ower dissi ation in Q is 2 V

p

1

I

CC

Power dissipation for an output short circuit:

The output stages are usually equipped with short-circuit protection to guard against such a situation

Power dissipation in Q 2 :

Q 2 conducts a constant current I

Maximum voltage across the collector and the emitter is 2 V CC

Maximum instantaneous power dissipation in Q 2 is 2 V CC I

A more significant quantity for design purposes is the average power dissipation of V CC I

Power Conversion Efficiency

The power conversion efficiency is defined as P L (load power) / P S (supply power)

The load power (P L ) with an sinusoid output with a peak value of

V

o

is

P

L

  2  ( V o / 2)  2 1 V o

R

L

2 R

L

The total average supply power is P S = 2 V CC I

The conversion efficiency is given by

1

V

2

o

1 V   V

o

o

 

 

4 IR V

L CC

4 IR

L

V

CC

Maximum efficienc

Class A output stage is rarely used in high-power applications

The efficiency achieved in practice is usually in the range of 10% to 20%

 (25%) is obtained when  V  V  IR o C C L

y

13.3 CLASS B OUTPUT STAGE Circuit Operation

Both transistors are cut off when v I is zero v O is zero

One of the transistor turns on as v I exceeds 0.5 V v O follows v I

The circuit operates in a push-pull fashion

The class B stage is biased at zero current and conducts only when the input signal is present

Transfer Characteristic

There exists a range of input centered around zero where both Q N and Q P are off

The transfer characteristic shows a dead band which results in the crossover distortion at the output  Power Conversion Efficiency

The average load power by neglecting the cross-over distortion is

P

L

1 V

2

o

2 R

L

The current drawn from each supply consists of half-sine waves of peak amplitude

The average power drawn from each of the two power supply is

P

S

P

S

1 V

o

R

L

V

CC

The total supply power is

P

S R

L

2 V

o

V

CC

The efficiency is given by

V

o

4

V

CC

V

o

/ R

L

Maximum efficiency is obtained when the output swing is maximized (V CC ):

4

78.5%

The maximum average power available from a class B stage is

P

L

1

V

2

o

2

R

L

Power Dissipation

The quiescent power dissipation of the class B stage is zero (unlike class A)

The average power dissipation of the class B stage is given by P D = P S P L

P

D

2

V o

R L

V

CC

1

V

2

o

2

R

L

Q N and Q P must be capable of safely dissipating half of P D

P D depends on the output swing and the worst-case power dissipation is given by

V

o

P

D max

2

V

CC

P

D

max

2

2

CC

V

R

L

The maximum power dissipation of Q N and Q P occurs at = 50%:

 P  P  DN max D P max

1

2

CC

V

R

L Reducing Crossover Distortion

The distortion can be reduced by employing a high-gain op amp and overall negative feedback

The 0.7V dead band is reduced by a factor of the dc gain of the op amp

The slew rate limitation of the op amp may cause the alternate turning on and off to be noticable

Single-Supply Operation

The class B stage can be operated from a single supply

The derivations are directly applicable with supply of 2 V CC  13.4 CLASS AB OUTPUT STAGE

Circuit Operation

Cross-over distortion can be eliminated by biasing Q N and Q P at a small nonzero current

The bias current i N = i P = I Q = I s exp(V BB /2 V T )

When v I goes positive by a certain amount:

v

v

O

v V / 2 v

I

BB

BEN

v V

BEP

BB

BEN

V

T

ln

i

N

I

S

V

T

ln

i

P

I

S

2

V

T

ln

I

Q

i

i

I N P

S

I

2

Q

 

i

2

N

i

i

N L

I

2

Q

0

The load current is supplied by Q N which acts as the output emitter follower

Q P will be conducting a current that decreases as v O increases (negligible for large v O )

Q P acts as the output emitter follower when v I goes negative

The power properties are almost identical to those derived for the class B stage  Output Resistance

The output resistance is estimated by assuming the source supply v I ideal

R

out

r

eN

||

r

eP

V

T

||

V

T

V

T

i

N

i

P

i

N

i

P

The output resistance remains approximately constant in the region around v I = 0

The output resistance decreases at larger load currents 13.5 BIASING THE CLASS AB CIRCUIT

Biasing Using Diodes

The bias voltage V BB is generated by passing a constant current I BIAS through a pair of diodes

The diodes need not to be large devices

Quiescent current I Q in Q N and Q P will be I Q = nI BIAS where n is the ratio of the areas of the emitter junction of the BJT and the junction area of the diodes

I BN increases from I Q /N to I L /N for a positive v O

I BIAS has to be greater than the I BN for maximum I L case

The ratio n cannot be a large number as n = I Q / I BIAS

This biasing arrangement provides thermal stabilization of the quiescent current in the output stage

Collect current increases with temperature for a fixed V BE

Heat from power dissipation increases with current

Positive feedback may cause thermal runaway

V BB decreases at the same rate of V BEN + V EBP

Thermal runaway is alleviated with close thermal contact Biasing Using the Voltage Multiplier

The class AB stage can be biased by V BE multiplier

I

V

V

1

/

BE

R

BB

V

BE

1

R

(1

1

/

R R

2

1

)

The value of V BE1 is determined by the portion of I BIAS that flows through the collector of Q 1

I

V

1

C

BE

I

BIAS

I

R

1

V

T

ln

I

C

1

I

S

V

T

ln

I

C 1

I

BIAS

I

R

The quiescent current can be adjusted by the resistance value  13.6 CMOS CLASS AB OUTPUT STAGES The Classical Configuration
 Circuit operation
1
1
V
V
V
V
|
V
|
2
I
GG
GS
1
SG
2
tn
tp
BIAS
k  W L
(
/
)
k W L
 (
/
)
n
1
p
2
1
1
V
V
V
V
|
V
|
2
I
GG
GSN
SGP
tn
tp
Q
k W L
 (
/
)
k W L
 (
/
)
n
n
p
p
2
1/
k
 W L
(
/
)
1/
k
 W
(
/
L
)
p
2
n
1
I
 I
Q
BIAS
1/
k
 W L
(
/
)
1/
k
 W L
(
/
)
n
n
p
p
 For the case Q and Q are matched and Q and Q
are matched:
1
2
P
N
(
W
/
L
)
n
I
I
Q
BIAS
(
W
/
L
)
1

A drawback of the CMOS class AB circuit is the restricted range of output voltage swing

v

v

O

max

O min

V

DD

V

|

OV BIAS

V v

tn

OVN

V V

SS

|

OV I

V

|

tp

|

v

|

OVP

|

where v OVN is the overdrive voltage of Q N when it is supplying i Lmax and |v OVP | is the overdrive voltage of Q P when sinking the maximum negative value of i L

An Alternative Circuit Using Common-Source Transistors

The allowable output range can be increased by replacing the source followers with a pair of complementary transistors in the common-source configuration

Q P supplies the load current when v O is positive, allowing an output as high as V DD |v OVP |

Q N sinks the load current when v O is negative, allowing an output as low as V SS + v OVN

The disadvantage is its high output resistance R out = r on ||r op

Negative feedback (error amplifiers) is employed to reduce the output resistance  Output Resistance

The output resistance is derived by two half circuits:

The analysis techniques for feedback (shunt-series feedback) is utilized:

R

out

R

|| R

outn

outp

1

and

A

v

o

v

i

g

mp

(

r

op

||

R

L

)

The open-loop output resistance:

The output resistance with feedback:

The output resistance excluding R L :

Overall output resistance:

R R || r

o

L

op

R R

of

o

R

outp

(

g

mp

/(1

A R

)

(

L

||

1/(1/

g

mn

)

R

of

1/ R )

L

R

out

1/

r

op

r

op

) /[1

g R r

(

L

||

m

op

||

1

g

mp

1

g

mp

)]  The Voltage Transfer Characteristics

For the case where Q N and Q P are matched:

Drain currents:

i

L

i

DN

i

I

Q

DP

i

1

DN

v

v

O

I

V

OV

2

and

Output voltage:

Gain error:

v

 

 

/ 1

V

OV

  

V

V OV

v

O

v

I

4 I R

Q



L

OV

v

I

v 

O I

4I R

Q

L

2g R

m

L

 

 

1

i

1

I kV

Q

2

2

OV

DP

I

Q

1

V OV

4

I R

Q

L v

v

O

I

V

OV

2 