Bonfring International Journal of Power Systems and Integrated Circuits, Vol. 3, No.

2, June 2013 7
ISSN 2277-5072 | 2013 Bonfring
Abstract--- A low power voltage source is generated by
altering the device size in existing topology has been
presented. Bandgap voltage reference is generated by
combination of start-up, supply independent, operational
amplifier (Op-amp) and bandgap core circuits which has been
designed such that low sensitivity of temperature and supply
variation. It has been designed with minimum supply of 0.8 V
without use of low threshold device, and the maximum supply
current is 35 A. It has been implemented in 180 nm standard
digital CMOS Process. The circuit generates a reference
voltage of 540 mV and has a temperature coefficient of 14
ppm /C from 40 C to 120 C. The generated reference
voltage is independent of temperature and supply variations
have been mathematically proved by analyzing the circuit
design. Also, proper selection of on-chip passive components
and its values has been chosen which is based on low noise.
Comparing the pre and post layout simulation results has been
presented.
Keyword--- Gain Calculations, Device Mismatch, Temperature
Independent Biasing, Supply Independent

I. INTRODUCTION
reference circuit is used to generate a voltage, which is
independent of supply voltage (V
DD
), and temperature
variations (V
T
). It is one of the core functional blocks in both
analog and digital systems and should be capable to operate as
low as 1 V supply [1]. Todays wireless applications
everything moves onto battery operated portable system. To
make longer battery life time, a system needs to design such
that it will consume low power. CMOS technology is the best
choice to achieve these performances as it has low power
consumption than other technology like BiCMOS etc.,
However, due to scaling down; the devices cannot operate
much lower than 1 V supply in the near future. To overcome
thisdifficulty, the transistor should capable to operate either in
subthreshold region (or) increase the device sizes such that to
reduce threshold voltage of transistor, which helps to operate
in low supply voltage. The output voltage of the conventional
bandage reference (BGR) is 1.25 V, which is nearly equal to
bandgap as 1 V supply.The output voltage of 1.25 V limits the

P. Arivazhagan, Assistant Professor, Department of Electronics and

Communication Engineering, Kodaikanal Institute of Technology,
Kodaikanal, Tamil Nadul, India E-mail:astm_codes@hotmail.com

DOI: 10.9756/BIJPSIC.10229
low V
DD
operation. With the help of resistive subdivision [1]
or by using BiCMOS process [2] or by using low threshold
voltage devices [3], BGR circuit should be capable to operate
as low as 1 V supply. In this design, resistive subdivision
without using low threshold device is used to operate in 1 V
supply in 0.18 m CMOS technology instead of 1.8 V by
altering the device size of transistor.
This paper is organized as follows. Section 2 describes
about the overview of all the sub-blocks which contains the
proposed block diagram of bandgap reference. Section 3
proves that output current is independent of supply and
temperature variations. Section 4 describes about bandgap
reference followed by layout design and comparing pre and
post layout results. Section 5 shows the final conclusion and
future enhancement of this design.
II. BLOCK DIAGRAM OF BANDGAP REFERENCE
The architecture of the reference generator block is shown
in Fig.1. It includes the start-up, supply independent, CMOS
Op-amp and bandgap core. The start-up is used to turn on the
entire transistor which is incorporated in supply independent
biasing circuit when the supply voltage varies from 0 to V
DD

during transients. Supply independent biasing circuit is used to
generate the current reference for biasing the op-amp, which is
independent of supply voltage (V
DD
) variations. Op-amp
senses V
in-
and V
in+,
which is coming from bandgap core, then

output of Op-amp is bandgap core as shown in Fig. 1 such that
to stabilize the V
in-
and V
in+
is approximately equal, which is
independent of V
T
. Op-amp needs to design with low power
consumption, high stability during transients and device
mismatch to make V
in-
and V
in+
. Bandgap core is used to
generate the voltage references, which is independent of V
T
.
Design and Implementation of Op-Amp Based
Low-Power CMOS Bandgap Voltage Reference
with Minimum Supply oF 0.8-V
Arivazhagan P


A
Bonfring International Journal of Power Systems and Integrated Circuits, Vol. 3, No. 2, June 2013 8
ISSN 2277-5072 | 2013 Bonfring

Fig. 2: Schematic of Bandgap Core


Fig. 1: Block Diagram of Bandgap Reference
III. SUPPLY AND TEMPERATURE INDEPENDENT BIASING
CURRENT
3.1 Supply Independent Biasing
To generate the reference currents as this is independent of
supply voltage (V
DD
) variations shown in Fig. 2 for biasing the
subsequent blocks like Op-amp. The transistor M
1
-M
4

designed such that it should operate in saturation region,
whereas M
2-3
is connected in diode configuration. The Rs
called source degeneration resistance used for stabilize the g
m

variation is added in the supply independent circuit shown in
Fig. 2 to make equalize current of nMOS transistors (M
3
-M
4
)
such that I
ref
equal to I
out
[4] instead of I
out
equal to

times
I
ref
due to R
s
.
3..1.1 Calculation of Output Current
At node V
x
,
s out DD x
R I V V = (1)
At node V
y
,
2 2 sg s out DD sg x y
V R I V V V V = =
(2)
2 1 1 1
) (
sg s out y g s sg
V R I V V V V + = = (3)
Equation (3) becomes,
s out sg sg
R I V V =
2 1

s out
ox p
out
ox p
out
R I
L
W
C
I
L
W
C
I
=

1 1
2 2

(4)
2
2
1
2
1
1 2

s
ox p
out
R
L
W
C
I
(5)

Equation (5) is the output reference current, which shows
that output current is independent of supply voltage variation
but depends on temperature variations.
Condition for M
1
& M
4
to be operated in saturation
region shown in Fig. 2 is,

1
2
1
thp sg s out DD thp y z
V V R I V V V V
1
2

L
W
C
I
R I V V
ox p
out
s out DD z

(6)

4 thn z y
V V V
(7)
3.1.2 Analysis
The small signal model of supply independent circuit is
shown in Fig. 3 to estimate the output current to supply
voltage (I
out
/V
DD
). The term is called sensitivity factor.

Fig. 3: Small Signal Model of Supply Independent Biasing
Circuit
By Kirchoffs Current Law (KCL),
out ref
I I I + =

+ =
04 4 04
2
02
1
r V g I r
g
r R V I
z m ref
m
s DD ref
(8)
Where,

=
3
03
1
m
ref z
g
r I V

Equation (8) becomes,

Vdd
M M
M M
Rs
2
3 4
Cc
Vdd
M M
M
M M M
M
M
M M
M
1 2
3 4
5 6
7
8
9
10
11
Vdd
R
1
R
R
R
R
2
2
1
R
C
M
1 M
2
M
A
nA
Vout
Ckt.
Supply independent Ckt.
Op amp Schematic
Bandgap Reference
Vbias
Vin-
Vin+
V
X
V
y
V
z
M
6
M
5
I
I
ref
I
out
I
ref
I
1
I
2
Q
1
Q
2
1

V V
V
V
1
2
3
0
V
1
V
2
N
N
R
Startup
Startup
Op-amp Bandgap
core
bias
V
in+
V
in-
V
ref
V
ref
V
ref
1
2
Supply Independent
Biasing
& I
V
y V
z
+
i
I
ref
I
o
u
t
r
03
1
g
m3
r
02
1
g
m2
R
s
+
r
04
g
m
4
V
z
V
g
m
1
y
r
01
Bonfring International Journal of Power Systems and Integrated Circuits, Vol. 3, No. 2, June 2013 9
ISSN 2277-5072 | 2013 Bonfring
01
3
03 04 4 04
2
02
1 1
R
g
r r g r
g
r R
I
V
m
m
m
s
ref
DD
=

+ =
(9)
Similarly, as shown in Fig 3,
( )
02 04 1 04
3
03 4 1
3
03 01
1 1
R r g r
g
r g g
g
r r
I
V
m
m
m m
m out
DD
=

+ =
(10)

02 02 01
1 1
R R R V
I
DD
out
=
(11)
Equation (11) shows the output current varies by V
DD

based on the values R
01
and R
02,
as it chosen by design
parameters.
3.1.3 Startup Problem
Startup problem defines as when the supply voltage is
turned on; all the transistors which is incorporated to make
system remain off as it have zero current. To solve this
problem, the transistors M
5-6

is connected closer to supply
voltage. During transients, when supply voltage varies from
0 to V
DD
, it generates the bias point at node V
y
by injecting
amount of charges through transistor M
5-6
, to turn on the
transistor M
1
. The transistor M
1
gives the output reference
current (I
ref
) when V
SG1
> V
thp1
then mirroring the current
through M
3-4
to turn on. The gate potential of transistor M
4

reaches V
GS4
>V
thn1
, it will generate the output current (I
out
)
then mirroring M
2
to M
1
. The process will continue until it
reaches the maximum supply voltage V
DD
. If it reach the V
DD
,
the condition for entire transistor, which is incorporated in
supply independent circuit to operate in saturation region as it
satisfy the equation (6) & (7) at the same time M
5-6
should be
turn off.
3.2 Principle of Operational Amplifier
Fig. 2 shows a two stage Op-amp, where M
3
and M
4
acts
as differential pMOS input pair, M
1-2
acts as current mirror.
M
5
acts to generate the bias current based on mirroring the
current through M
6-7
used for biasing the differential pair. This
topology is best suited for low voltage operation due to
nobody effect and low flicker noise than differential nMOS
input pair. M
8-9
acts as single stage amplifier using active load
to increase the gain. To biasing the transistor M
9,
mirroring the current through M
10-11.
The resistance (R) and
compensation capacitor (Cc) used for compensation to make
stability of the system as it introduce the zeros between poles.
3.2.1 Analysis
Fig. 4 shows the small signal model of op-amp shown in
Fig. 2 to find the gain of the system. In the figure below, the
subscript number 5,6,7,8 changes in
to 8, 9, 10 and 11 i.e., r
05
= r
08
by Fig. 2.

Fig. 4: Small Signal Model of Two Stage Miller Compensated
Op Amp used in Band-Gap Reference

+
=
09 08
09 08 04 02
04 02
2
8
0
2
2 1
r r
r r r r
r r
g
g
v
V
m
m
id
(12)
Equation (12) is the gain of the Operational amplifier.
3.2.2 Device Mismatch
To design a low systematic offset Op-amp for bandgap
applications, device mismatch is major issue. In these design
current drawn from M
8
and M
9
are perfectly matched as it
depends on input arise from node V
1
& V
2
. The current
relationship between I
8
and I
9
in terms of bias current (I) is
generated by M
5
.

1
10
11
9
2
8

L
W
L
W
L
W
L
W
L
W
L
W (13)
Equation (13) is device size relationship to get I
8
and I
9
are
perfectly matched without delay difference.
3.3 Temperature Independent Biasing
To generate the reference voltage as it independent of
temperature variation by adding the two currents as it depends
on positive and negative temperature coefficient (TC). The
resultant output is zero TC.
By KCL, at node (V
1
) shown in Fig. 2 (bandgap reference)
is,

2 1
i i i
ref
+ =
(12)
Where,

R
n V
R
V V
i
T EB EB
ln
2 1
1
=

=
(13)

2 1
1
2
R R
V
i
EB
+
=
(14)
Substitute (13) & (14) in (12),


2 1
1
ln
R R
V
R
n V
i
EB T
ref
+
+ =
(15)
To make a design such that change in reference current to
change in temperature is less sensitivity (=0) based on the
values of active and passive devices, which is used in the
design.
Equation (15) becomes,

0
ln
2 1
1
=

+
+

=
R R
V
dT
d
R
n V
dT
d
dT
di
EB T
ref
(16)
Where,
( )
2
0
) ( ) ln( ) ln(
ln
R
T R TCR n V
dT
dV
n R
R
n V
dT
d
T
T
T

=

(17)
( ) ( )
( )
2
2 1
0 2 0 1 1
1
2 1
2 1
1
)) ( ) ( (
R R
T R T R TCR V
dT
dV
R R
R R
V
dT
d
EB
EB
EB
+
+ +
=

+
(18)
g
1
g
m
3
r
0
1
r
0
4
r 0
2
m
1v
i
d 2
g
m
g
m
v
i
d 2
4
V
1
2
V
1
V
2
r
g
m
g
m
V
V
r 0
5
0
6
0
56
2
V
3
g
m
7
V
1
1
g
m
8
V
3
Bon
T=
Fig
is
per


coe
val
3.3
equ
Wh
to
of
dep
wh
im
ind
lay
sim
nfring Internationa
Assume all
=300K,
/ 160
(
08617 . 0
C ppm
temperatu TCR
dT
dV
T
=
=
To make the
g. 2 in bandgap
n times th
rceptive, chose
Equation (6) b
At room temp
R
N
=
Equation (17)
R
n V
dT
d
T
=
=

179 . 0
07 . 2
ln
Equation (18)
2 1
1
R R
V
dT
d
EB
=
=

+
Add the equ
efficients.
/ 1791 . 0
R
mV

Equation (24)
lue, which is in
3.1 Determi
Equation (15
uation (24),

N
re
R
R
V
here, N is 1, 2
Equation (25)
get different
temperature v
pendence [6] s
IV. LAY
The three di
hich is indepe
mplemented in 0
dependent of th
yout design a
mulation results
al Journal of Powe
the design
/ 0000006 . 0
2 , / 7
of t coefficien e ur
V K mV
T
=
=
node voltage
p reference. Fo
he size of tr
en n is equal t
becomes,
perature,
R
N
=R
N
(T
0
) (1
=R
N
(T
0
) [5],
) becomes by e
R
K mV
K mV

/ 91
/ 08617 . 0
79
) becomes,
(
2 1
1
/ 50045 . 1
75 / 5 . 1
R R
mV
R
K mV
+

=

uation (8) and
50045 . 1 /
1

R
K
R R 8
2 1
= +
) shows the va
ndependent of
ine the RN in T
5) represents
N
N
ef
R
R
965 . 6
065 . 54
=
=
2, 3
) shows the di
N reference
variations but
hown in Fig. 2
YOUT DESIGN A
ifferent referen
endent of supp
0.18 m CMO
hree different v
and comparis
s is shown in F
er Systems and Inte
values at ro
.
, 26
K
silico poly P f
mV
+
at V
1
and V
2
i
or that the size
ransistor Q
1

to 8.
1+TCR (TT
0
)

equation (20),
R
K mV / 0000156 . 0
)
2
0000006 . 0 ( 50
K
R
mV
+
(9) to make
0
/ 5
2
=
+

R
K mV
R 38 .

lues of resistan
temperature va
Terms of (R1+R
by room te
refN
V R
m mV
7
38 . 8
750

+
fferent N val
voltages, whic
the value cha
2
AND SIMULATI
nce voltages s
ply varies fro
OS technology.
voltages is sho
son of pre a
Fig. 7 and table
egrated Circuits, V
ISSN 2277-
oom temperat
) on
(19)
is equal shown
of transistor Q
. With vario
)
(20)
K

(21)
)
(22)
zero temperat
0
(23)
(24)
nce assuming
ariations.
R2) & VrefN
emperature us
R
V
(25)
lue of resistor
ch is independ
anges by volta
ION RESULTS
shown in Fig
om 0.8 to 1.8
The temperat
wn in Fig. 6. T
and post lay
e I.
Vol. 3, No. 2, June
-5072 | 2013 Bo
ture
)
n in
Q
2

ous
)
ture
R
ing
for
dent
age
. 5
V
ture
The
yout
Fig.
Ta
T
(
P
(
P
(
P
(V
(0
Fig. 6
Fig
Op-
referenc
of 0.8 V
work is
Also, im
e 2013
onfring
5: Output Volt
Vol
able 1: Compar
Temperature
40 ~ 125 )
C
Pre Layout
(V
ref
) (mV)
Post Layout
(V
ref
) (mV)
Post Layout
V
DD
) (V
ref
)
0.8 1.2 V)
: Output Volta
g. 7: Layout De
V. CO
amp based l
ce is designed
V in 180 nm
s to fabricate t
mplement the
tage and Curre
ltage at Typica
rison of Pre and
FF T
553 ~
530
551
552 ~
535
551
554 ~
534
550

age and Curren
Typical Corn
esign of Sub-1
ONCLUSION AND
low power C
and implemen
standard CMO
the chip in 18
design by sca
ent Varying wit
al Corner
d Post Layout
TT S
~ 527 550 ~
~ 531 549 ~
~ 530 547 ~
t Varying Tem
ner
V Bandgap Re
D FUTURE WOR
CMOS bandg
nted with mini
OS technology
80 nm CMOS
aling down t
10

th Supply
Results
SS
~ 524
~ 529
~ 527

mperature at

eference
RK
gap voltage
mum supply
y. The future
technology.
the channel
Bonfring International Journal of Power Systems and Integrated Circuits, Vol. 3, No. 2, June 2013 11
ISSN 2277-5072 | 2013 Bonfring
length like 130 nm, 90 nm, 60 nm, 45 nm etc., in standard
CMOS technology and tapeout the IC in different channel
lengths. Compare the pre and post layout simulation with
tapeout results .
REFERENCES
[1] Ka Nang Leung and Philip K.T. Mok, A Sub-1-V 15-ppm/C CMOS
Bandgap Voltage Reference without Requiring Low Threshold Voltage
Device, IEEE Journal of Solid-State Circuits, Vol. 37, No. 4, Pp. 526
530, 2002.
[2] P. Malcovati, F. Maloberti, M. Pruzzi, and C. Fiocchi, Curvature
compensated BiCMOS bandgap with 1-V supply voltage, Proceedings
in ESSCIRC 2000:
[3] H. Banba, H. Shiga, A. Umezawa, T. Tanzawa, S. Atsumi, and K. Sakui,
A CMOS bandgap reference circuit with sub-1-V operation, IEEE
Journal of Solid-State Circuits, Vol. 34, Pp. 670674, 1999.
[4] B. Razavi, Design of Analog CMOS integrated Circuits. Tata Mc Graw
Hill; 2001.
[5] Sedra/Smith, Microelectronics Circuits. Oxford.University Press, Inc.
2005.
[6] R. Jacob Baker, CMOS circuit design, layout and Simulation, Wiley-
IEEE Press, 2005.


Arivazhagan P was born in Krishnapuram, vettikkadu
(po), orathanadu (tk), thanjavur (dt), Taminadu,India-
614902 on july 28, 1981. About school life, from 1984
to 2000 studied from surrounding places where I am
leaving. From there moved to Madras (now Chennai)
and received the B.E degree in Electronics and
Instrumentation Engineering from the University of
Madras, TamilNadu in 2004. From 2003 to 2005,
NCCT Limited, Chennai as a project staff involved
with guidance for students. In 2006, received Advanced PG diploma in VLSI
Design and worked as project trainee from Semiconductor Complex Limited
(Vedant), Chandigarh, India under Cadence university Programme. From
2007 to 2011, joined as senior Project Assistant in Advanced VLSI Design
Laboratory, Indian Institute of Technology (IIT), kharagpur, and involved
with designing the ICs for high frequency applications and teaching assistant.
I received MS (by research) in the department of Electronics and Electrical
Communication Engineering from IIT Kharagpur in 2012. Spiritual
achievement between 2010 to 2011 (at that time pursuing MS IIT-Kharagpur),
succeeded based on six years spiritual truth love with The Hindu religion -
God, Goddess frequent temple visit. From Feb 2012 to July 2012 worked as
an assistant Professor in Oxford Engineering College, Trichirappalli affiliated
by anna university, chennai. Currently, working as an assistant professor in
the department of Electronics and Communication Engineering, Kodaikanal
Institute of Technology, Machur, Kodaikanal affiliated by anna university,
Chennai. Achievements like gold medalist, Best project award, Best Paper
award in ICVSP 2012. (e-mail: astm_codes@hotmail.com)