Esd 2

1.
Course overview
2. Intro to PICOBLAZE, C and Number systems and Boolean Alebra
!. Course overview wit" mi#ro$ro#essor %&' (I)
*. Course overview wit" mi#ro$ro#essor %&' (II)
+. ,erilo -.L
/. .iital system #om$onents usin s#"emati#s and ,erilo
0. Combinational loi# standard 1orms. 2arnau" ma$s
3. Combinational ##ts and #on4urable loi# devi#es
5. 6im$le 6e7uential #ir#uits, 8i$ 8o$s
1'. 6e7uential #ir#uits, #ounters, reisters, memories
11. Non9ideal e11e#ts in diital #ir#uits
12. :inite 6tate %a#"ines
1!. .esin o1 :6%s
1*. .esin o1 :6%s
1+. .ata$at"s
1/. An introdu#tion to Pro#essor .esin
10. ;"e A<% Ar#"ite#ture
13. A<% Asssembly Lanuae Prorammin
15. Prorammin in C
...
3213: Digital Systems & Microprocessors: L#14_15
:ollow 6teve :urber =A<% 6ystem on a C"i$ Ar#"ite#ture Le#ture Notes
ARM history
193 !e"elope! #y Acor$ comp%ters
&o replace '5(2 i$ ))* comp%ters
4+ma$ ,LS- !esig$ team
-ts simplicity comes .rom the i$e/perie$ce!
team
Match the $ee!s .or ge$erali0e! So* .or
reaso$a#le po1er2 per.orma$ce a$! !ie si0e
199( ARM 3A!"a$ce! R-S* Machi$e42 o1$e!
#y Acor$2 Apple a$! LS-
ARM Ltd
Design and license ARM core design but not fabricate
5hy ARM6
7$e o. the most lice$se! a$! th%s 1i!esprea! processor cores
i$ the 1orl!
8se! i$ 9DA2 cell pho$es2 m%ltime!ia players2 ha$!hel!
game co$sole2 !igital &, a$! cameras
ARM:: ;)A2 i9o!
ARM9: <DS2 9S92 So$y =ricsso$2 )e$>
ARM11: Apple i9ho$e2 <o?ia <932 <((
:5@ o. 32+#it em#e!!e! processors
*orte/ A #eagle#oar! ope$ har!1are
8se! especially i$ porta#le !e"ices !%e to its lo1 po1er
co$s%mptio$ a$! reaso$a#le per.orma$ce
3213: Digital Systems & Microprocessors: L#1'+1:
http:BB#eagle#oar!CorgB
http:BBal1aysi$$o"ati$gCcom
ARM L9*23' De"C )oar!
i$ DLA)s 3Furturlec)
ARM L9*23' De"C )oar! 3Furturlec)
E -$cl%!es <F9 L9*23' ARM Microco$troller 1ith a h%ge 512?# -$ter$al Glash 9rogram
Memory
E 7perati$g Spee! %p to :2 MD0
E Direct -$+*irc%it 9rogrammi$g "ia RS232 *o$$ectio$ .or =asy 9rogram 8p!ates
E 8p to 25 -B7 poi$ts 1ith easy to co$$ect sta$!ar! hea!ers
E G%ll Spee! 8S) 2C( 9ort
E =ther$et LA< 1(B1((M# *o$$ectio$ .or .%ll $et1or?i$g
E Large 5? Data RAM
E ' *ha$$els 1(+)it ABD
E 1 *ha$$el 1(+)it DA*
E 2 *ha$$els sta$!ar! *A< $et1or?
E Real &ime *loc? 1ith )attery )ac?+8p
E SD *ar! *o$$ector .or Data Storage a$! &ra$s.er
E H&A; *o$$ector .or 9rogram Do1$loa! a$! De#%g
E L*D *o$$ectio$ 1ith *o$trast A!I%stme$t
E Loa! a$! Reset )%tto$
E 7$+)oar! 3C3, Reg%lator
E -!eal as a$ -$tercha$gea#le *o$troller .or Real+&ime Systems
Computers
All mo!er$+ge$eral p%rpose comp%ters employ the pri$ciples o.
a store! program !igital comp%ter 3!ates to 194(s4
Girst impleme$te! SS=M 3J)a#yJ4 H%$e 194 8$i Ma$chester
The Small-Scale Experimental Machine, known as SSEM, or the "Baby", was desined and
built at The !ni"ersity o# Manchester, and made its #irst success#ul run o# a proram on $une
%&st &'()* +t was the #irst machine that had all the components now classically rearded as
characteristic o# the basic computer* Most importantly it was the #irst computer that could store
not only data but any ,short-) user proram in electronic memory and process it at electronic
speed*
%ost advan#es in #om$utin due to ele#troni#s... but ..
Com$uter Ar#"ite#ture > &ser view? instru#tion set, visible reisters,
memory manaement...
Com$uter Oranisation? user9invisible @ $i$eline stru#ture,
trans$arent #a#"e, ...
;"e state in a stored9$roram diital #om$uter
a!!ress
i$str%ctio$s
$ro#essor
memory
registers
i$str%ctio$s
!ata
((CC((
1'
GGCCGG
1'
a$! !ata
MU0 A simple microprocessor
A simple .orm o. processor ca$ #e #%ilt 1ith 9rogram co%$ter 9*
Acc%m%lator or 1or?i$g register
Arithmetic logic %$it
-$str%ctio$ register 3-*4
-$str%ctio$ !eco!e a$! co$trol logic that employs the a#o"e
compo$e$ts to achie"e the !esire! res%lts .rom each i$str%ctio$
M8( is a 1' #it machi$e 1ith a 12 #it a!!ress space
-$str%ctio$s are 1' #its lo$g 1ith a 4 #it opco!e a$! a 12 #it a!!ress 1or!
;"e data$at"? All the compo$e$ts carryi$g 3#%ses42 stori$g 3registers4 or

processi$g 3al%2 m%/4 #its i$ parallel .orm the compo$e$ts o. the
!atapathC &se t"e <;L des#ri$tion @ a#tually data$at" 1or usA
;"e Control Loi#? ="erythi$g else s%ch as !eco!e a$! co$trol %se :6%
a$$roa#".
MU0 Datapath design
<ee! a g%i!i$g pri$ciple to limit !esig$ possi#ilities A %s%ally #ase! o$ cloc?
co$strai$t i$ microprocessors
Each instruction takes the number of clock cycles equal to the number
of memory accesses it must make
5e ass%me a$ i$str%ctio$ starts 1he$ the i$str%ctio$ appears i$ the
i$str%ctio$ registerC &here are ge$erally t1o steps to e/ec%te a$ i$str%ctio$
14 Access the memory opera$! a$! per.orm the !esire! operatio$
24 Getch the $e/t i$str%ctio$ to #e e/ec%te!
&he processor m%st start i$ a ?$o1$ locatio$ A 1e ca$ !o this 1ith a resetC
M8( co$trol logic
The MU0 instruction format
opco!e S
12 #its 4 #its
12 #it a!!ress space KL ? memory
4(9' i$!i"i!%ally a!!ressa#le memory locatio$s
4 #it opco!e KL 1' possi#le assem#ly la$g%age
*omma$!s o$ly %se M + goo! practice
&he M8( i$str%ctio$ set
Instructi
on
Opcod
e
Effect
LDA S 0000 ACC := mem
16
[S]
STO S 0001 mem
16
[S] := ACC
ADD S 0010 ACC := ACC +
mem
16
[S]
SUB S 0011 ACC := ACC -
mem
16
[S]
JMP S 0100 PC := S
JGE S 0101 if ACC >= 0 PC := S
JNE S 0110 if ACC !=0 PC := S
STP 0111 !"#
Girst .o%r ha"e t1o memory accesses a$! 1ill $ee! t1o cloc? cycles
Last .o%r co%l! e/ec%te i$ o$e cycle
&he M8( co$trol
<e/t 1e $ee! to !etermi$e e/actly 1hat co$trols 3logic le"els4 are $ee!e! to
ma?e the !atapath e/ec%te the correct .%$ctio$s gi"e$ the op+co!e
5e ass%me that all registers cha$ge state o$ the risi$g e!ge o. the cloc?
3cC. $egati"e e!ge G%r#er A pro#a#ly #eca%se e/ter$al SRAM %se! .or the
act%ally memory is pose!ge triggere!664C
Gor the registers the co$trol sig$als pre"e$t or !isallo1 tra$sitio$s at the cloc?C
&here are also .ee!#ac? co$trol sig$als .rom the !atapath to the co$trol GSM
N opco!e #its2 sig$als .rom the a##umulator i$!icati$g 1hether its co$te$ts
are 0ero or $egati"e 1hich co$trol the respecti"e co$!itio$al I%mp i$str%ctio$sC
All we need to do is develop a two state FSM to generate the control signals
Since there are just two states and lots of control
outputs = do a !S table and forget the S" approach
GSMs ha"e $o memory o.
o%tp%ts
6tate 1
BBBBBB
6ome
Out$uts
...
6tate 2
BBBBBB
Ot"er
Out$uts
...
In$uts
In$uts
...
In$uts
In$uts
...
In$uts
In$uts
...
In$uts
In$uts
...
module "re&., clk, /, d, en, rs )0
output 1&2345 /0
input 1&2345 d0
input clk0
input en0
input rs0
re 1&2345 /0
always 6,posede clk) bein
i#,en 77 8rs) / 9: d0
else i#,en 77 rs) / 9: &.;h40
else / 9: /0
end
endmodule << "=re&.
Memory comes from memory
#ere is how $ a %& bit register'''
.ealin wit" out$ut CdonDt #aresE
Grom G%r#er
&he O!o$Pt caresQ i$ GSM o%tp%ts set ha"e a !i..ere$t mea$i$gC
As the control state must generate these signals we must eventually
define what they will be (!ot )*s+
<ote that Eno is al1ays !e.i$e!R this is #eca%se it is esse$tial to ?$o1 i. the total
register is to cha$ge or $ot o$ a$y gi"e$ cloc? e!geC -. it is cha$gi$g 3Eno K 14
the$ ,-. a$! /lr co$trol 1hat it is !oi$gR ho1e"er i. it is $ot cha$gi$g
3Eno K (4 the$ it !oes$Pt matter 1hat "al%e is prese$te! to the register A it 1ill
ig$ore itC
Allo1i$g latit%!e at this time gi"es more .ree!om i$ the logic
re!%ctio$2 simpler eS%atio$s a$! th%s smaller 3& .aster4 circ%itsC
Memory
Register =$a#le 3Eno+
*lear (/lr4
Rea!B5rite 3,-.+
-$p%t Data#%s
7%tp%t Data#%s
A!!ress
#%s
M8( !atapath e/ample
-R 9*
A**
AL8
memory
co$trol
a!!ress #%s
!ata #%s
MU0 datapath example
M8(
register
tra$s.er
le"el
orga$i0atio$
memory
A**
-Rce
9*ce
AL8.s
)sel
A**ce
A**oe
M=MrS R$5
m%/
( 1
Asel
AL8
A )
9*
A**T15U
A**0
-R
opco!e
%&'
MU0 control logic
Input s Out put s
Opco de Ex / f t ACC1 5 Bs el PCce ACCo e MEMrq Ex / f t
Ins t ruct i o n Res et ACCz As el ACCce IRce ALUf s Rn
Reset xxxx 1 x x x 0 0 1 1 1 0 = 0 1 1 0
LDA S 0000
0000
0
0
0
1
x
x
x
x
1
0
1
0
1
0
0
1
0
1
0
0
= B
B+1
1
1
1
1
1
0
STO S 0001
0001
0
0
0
1
x
x
x
x
1
0
x
0
0
0
0
1
0
1
1
0
x
B+1
1
1
0
1
1
0
ADD S 0010
0010
0
0
0
1
x
x
x
x
1
0
1
0
1
0
0
1
0
1
0
0
A+B
B+1
1
1
1
1
1
0
SUB S 0011
0011
0
0
0
1
x
x
x
x
1
0
1
0
1
0
0
1
0
1
0
0
A-B
B+1
1
1
1
1
1
0
JMP S 0100 0 x x x 1 0 0 1 1 0 B+1 1 1 0
JGE S 0101
0101
0
0
x
x
x
x
0
1
1
0
0
0
0
0
1
1
1
1
0
0
B+1
B+1
1
1
1
1
0
0
JNE S 0110
0110
0
0
x
x
0
1
x
x
1
0
0
0
0
0
1
1
1
1
0
0
B+1
B+1
1
1
1
1
0
0
STOP 0111 0 x x x 1 x 0 0 0 0 x 0 1 0
M8( machi$e la$g%age program
pro*lst
'''/
!''0
1''/
'''/
+'''
0'''
'''*
'''1
Instructi
on
Opcod
e
Effect
LDA S 0000 ACC := mem
16
[S]
STO S 0001 mem
16
[S] := ACC
ADD S 0010 ACC := ACC +
mem
16
[S]
SUB S 0011 ACC := ACC -
mem
16
[S]
JMP S 0100 PC := S
JGE S 0101 i f ACC >= 0 PC := S
JNE S 0110 i f ACC !=0 PC := S
STP 0111 !"#
M8( G%$ctio$
M8( A =/te$sio$s
M8( is a simple processor #%t $ot %se.%l as a compiler targetC
Some e/te$sio$s seem appropriate
E0tending the address space
Adding more addressing modes
Allowing the 1/ to be saved in order to support a
subroutine mechanism
Adding more registers2 supporting interrupts2 etc'''
More peripherals $ watchdog timer2 ''
C 7"erall M8(Js i$str%ctio$ set is $ot a goo! place to start so let
%s re!esig$C
>here to start?
Let %s start 1ith the core o. the microprocessor .%$ctio$ality
3 4he instruction
5et us looking at a basic A"" for e0ample
Some #its to !i..ere$tiate .rom other i$str%ctio$s
Some #its to speci.y opera$! a!!resses
Some #its to speci.y 1here the res%lts sho%l! #e
place! + desitnation
Some #its to speci.y the a!!ress o. the $e/t i$str%ctio$

A 4+a!!ress i$str%ctio$ .ormat
.%$ctio$ op 1 a!!rC op 2 a!!rC !estC a!!rC $e/t_i a!!rC
$ #its
$ #its $ #its $ #its . #its
6 Assembly language instruction format might look like
A.. d, s1, s2, neFtBi G d ?> s1 H s2
Requires (4n + f bits)
.%$ctio$ op 1 a!!rC op 2 a!!rC !estC a!!rC
$ #its $ #its $ #its . #its
7$e 1ay to re!%ce the $%m#er o. #its reS%ire! .or each i$str%ctio$
is to ma?e the a!!ress o. the $e/t i$str%ctio$ implicitC
>e assume that the next instruction is @AB SiCeo#,instruction),
,note that in M!4 the de#ault next instruction was at @AB&* But i#
>e eneralise then maybe there can be more than one address to
contain the contents o# an instruction)
A"" d2 s%2 s78 d 9= s% : s7
.%$ctio$ op 1 a!!rC !estC a!!rC
$ #its $ #its . #its
A further saving can be made by making the
destination register the same as one of the source registers
A"" d2 s%8 d 9= d : s7
A 1+a!!ress 3acc%m%lator4
i$str%ctio$ .ormat
.%$ctio$ op 1 a!!rC
$ #its . #its
If the destination register is implicit then it is often
Called the accumulator
A"" s%8 accumulator 9= accumulator : s7
A (+a!!ress i$str%ctio$ .ormat
.%$ctio$
. #its
Gi$ally all registers may #e ma!e implicit #y i$tro!%ci$g
A$ e"al%atio$ stac?
A"" 8 top;of;stack 9= top;of;stack : ne0t;on;stack
=/amples o. $+a!!ress %se
All o. the a#o"e ha"e #ee$ %se! i$ processor i$str%ctio$ sets
apart .rom the 4+a!!ress .orm 1hich2 altho%gh it is %se!
i$ter$ally i$ some microcode(<<+ !esig$s is
unne#essarily eF$ensive
;"e Inmos trans$uter uses a '9address evaluation

sta#I ar#"ite#ture
;"e %&' eFam$le in t"e $revious se#tion is a 19address

ar#"ite#ture
;"e ;"umb instru#tion set used 1or "i" #ode density in t"e
A<% mi#ros is $redominatly o1 t"e 29address 1orm
;"e standard A<% instru#tion set uses a !9address

ar#"ite#ture
Typical dynamic instruction usage
Instruction t!pe "!n#$ic us#%e
Data movement 4!
"ont#o$ %$o& '!
A#(t)met(* o+e#at(ons 1,!
"om+a#(sons 1!
Lo-(*a$ o+e#at(ons ,!
Ot)e# 1!
Pipelined instruction execution
.etch !ec reg AL8 mem res
1
2
!
time
i$str%ctio$
Read-after-write pipeline hazard
1
2
time
stall
i$str%ctio$
Pipelined branch behaviour
1 (bran#")
2
!
time
i$str%ctio$
*
+ (bran#" taret)
Naming ARM
ARMxyzTDMIEJFS
x: series
y: MMU
z: cache
T: Thumb
D: debugger
M: Multiplier
I: Interrupt
E: Enhanced
J: Jazelle
F: Floating-point
S: Source
Popular ARM architecture
ARM7TDMI
3 pipeline stages
One of the most used ARM-version (for low-end
systems)
ARM9TDMI
Compatible with ARM7
5 pipeline stages
Separate instruction and data cache
ARM11
ARM architecture
Load/store architecture
A large array of uniform
registers
Fixed-length 32-bit
instructions
3-address instructions
Processor modes
ARM architecture
37 registers
1 Program counter
1 current program status
registers
5 saved program status
registers
30 general purpose
registers
Registers
Only 16 registers are visible to a specific mode. A
mode could access
A particular set of r0-r12
r13 (sp, stack pointer)
r14 (lr, link register)
r15 (pc, program counter)
Current program status register (cpsr)
Register organization
General-purpose registers
0 $ % 16 1& '( ') )1
$-*i! B+!e
16-*i! ,-.f /"01
)'-*i! /"01
6 data types (signed/unsigned)
All ARM operations are 32-bit. Shorter data types
are only supported by data transfer operations.
Program counter
Store the address of the instruction to be executed
All instructions are 32-bit wide and word-aligned
Thus, the last two bits of pc are undefined.
m"1e *i!
Program status register (CPSR)
"2e0f."/
3-00+4*"00"/
5e0"
6e7-!i2e
!-!e *i!
89: 1i-*.e
9;: 1i-*.e
Summary
Load/store architecture
Most instructions are RISCy, operate in single

cycle.
Some multi-register operations take longer.
All instructions can be executed conditionally.

3213: Digital Systems & Microprocessors: L#1
LinuF usae on Intel (* level ,on Neuman)

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1.

M8( is a 1' #it machi$e 1ith a 12 #it a!!ress space

;"e data$at"? All the compo$e$ts carryi$g 3#%ses42 stori$g 3registers4 or

;"e Inmos trans$uter uses a '9address evaluation

;"e %&' eFam$le in t"e $revious se#tion is a 19address

;"e standard A<% instru#tion set uses a !9address

Most instructions are RISCy, operate in single

Some multi-register operations take longer.

All instructions can be executed conditionally.

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