Leakage Power Optimization of Standard Cells Using Gate-Length Biasing, Multiple Vt & Multi Channel Technique

Project Objective: - Leakage Power Optimization of Standard Cells Using Gate-Length Biasing, Multiple
Vt and Multi-Channel Technique
Project Formulation: - With CMOS technology being scaled to ever smaller dimensions to achieve higher
performance and integration levels, power dissipation has become a major concern in VLSI designs. The
high leakage current in nanometre regimes is becoming a significant portion of power dissipation in CMOS
circuits as threshold voltage, channel length, and gate oxide thickness are scaled. So leakage power becomes
a top concern for IC designer in deep sub-micron process technology node (65nm & below). In this project
the leakage power design of several standard cell such, Inverter, NAND, NOR, Flip Flop, 1 bit Adder are
introduced in Nangate 45NM CMOS libraries. The Basic standard cell are optimized to achieve low leakage
power delay product (PDP) using Gate-Length Biasing (GLB), Multi Vt (MVt) and Multi-channel technique.

I. INTRODUCTION
Power dissipation in CMOS circuits has two components: dynamic and static power consumption [1]. The
dynamic power dissipation includes switching power due to charging and discharging of load capacitances,
and short circuit power due to the direct path from supply to the ground. The static power dissipation is
caused by leakage current of MOS devices. Leakage is become an ever-increasing component of total
dissipated power with its contribution projected to increase from 18% to 130nm to 54% at 65nm node [2].
Intel power graph illustrates it perfectly in figure 1 [3].
Leakage is composed of three major components: subthreshold leakage, gate leakage, and reverse biased
drain substrate and source-substrate junction band-to-band tunnelling leakage [4]. Subthreshold leakage is
the dominant contributor to total leakage at 130nm and remains so in the future [5].
Transistor Leakage Mechanism:-
We describe six short-channel leakage mechanisms as illustrated in Fig. 2. I1 is the reverse-bias pn junction
leakage; I2 is the subthreshold leakage; I3 is the oxide tunnelling current; I4 is the gate current due to hot-
carrier injection; I5 is the GIDL; and I6 is the channel punch through current. Currents I2, I5, and I6 are off-
state leakage mechanisms, while I1 and I3 occur in both ON and OFF states. I4 can occur in the off state, but
more typically occurs during the transistor bias states in transition [2].
Leakage Power Optimization of Standard Cells Using Gate-Length Biasing, Multiple Vt & Multi Channel Technique





Figure1.Intel Design Power Road Map

A. pn Junction Reverse-Bias Current (I 1)
Drain and source to well junctions are typically reverse biased, causing pn junction leakage current. A
reverse-bias pn junction leakage (I1) has two main components: one is minority carrier diffusion/drift near
the edge of the depletion region; the other is due to electron-hole pair generation in the depletion region of
the reverse-biased junction [6].

Figure 2. Leakage Currents in MOSFET
Leakage Power Optimization of Standard Cells Using Gate-Length Biasing, Multiple Vt & Multi Channel Technique




For an MOS transistor, additional leakage can occur between the drain and well junction from gated diode
device action (overlap of the gate to the drain-well pn junctions) or carrier generation in drain to well
depletion regions with influence of the gate on these current components [7]. PN junction reverse- bias
leakage (IREV) is a function of junction area and doping concentration [6]. If both n and p regions are
heavily doped (this is the case for advanced MOSFETs using heavily doped shallow junctions and halo
doping for better SCE), band-to-band tunnelling (BTBT) dominates the pn junction leakage [8].
Band-to-Band Tunneling Current: High electric field (>106 V/cm) across the reverse-biased pn junction
causes significant current to flow through the junction due to tunneling of electrons from the valence band
of the p region to the conduction band of the n region[8].

B. Subthreshold Leakage (I2)
Subthreshold or weak inversion conduction current between source and drain in an MOS transistor occurs
when gate voltage is below [9].
Drain-Induced Barrier Lowering: In long-channel devices, the source and drain are separated far enough
that their depletion regions have no effect on the potential or field pattern in most part of the device. Hence,
for such devices, the threshold voltage is virtually independent of the channel length and drain bias. In a
short-channel device, however, the source and drain depletion width in the vertical direction and the source
drain potential have a strong effect on the band bending over a significant portion of the device. Therefore,
the threshold voltage, and consequently the subthreshold current of short-channel devices, vary with the
drain bias. This effect is referred to as DIBL.
DIBL occurs when the depletion regions of the drain and the source interact with each other near the channel
surface to lower the source potential barrier. When a high drain voltage is applied to a short-channel device,
it lowers the barrier height, resulting in further decrease of the threshold voltage. The source then injects
carriers into the channel surface (independent of gate voltage). DIBL is enhanced at high drain voltages and
shorter channel lengths. The surface DIBL typically occurs before the deep bulk punch through [10].

Leakage Power Optimization of Standard Cells Using Gate-Length Biasing, Multiple Vt & Multi Channel Technique



C. Tunneling into and Through Gate Oxide (I3)
Reduction of gate oxide thickness results in an increase in the field across the oxide. The high electric
field coupled with low oxide thickness results in tunneling of electrons from substrate to gate and also from
gate to substrate through the gate oxide, resulting in the gate oxide tunneling current.
The mechanism of tunneling between substrate and gate poly silicon can be primarily divided into two parts,
namely: (1) FowlerNordheim (FN) tunneling; and (2) Direct tunneling.
In the case of FN tunneling, electrons tunnel through a triangular potential barrier, whereas in the case of
direct tunneling, electrons tunnel through a trapezoidal potential barrier. The tunneling probability of an
electron depends on the thickness of the barrier, the barrier height, and the structure of the barrier. Therefore,
the tunneling probabilities of a single electron in FN tunneling and direct tunneling are different, resulting
in different tunneling currents. In FN tunneling, electrons tunnel into the conduction band of the oxide layer.
Direct Tunneling: In very thin oxide layers (less than 34 nm), electrons from the inverted silicon surface,
instead of tunneling into the conduction band of SiO2, directly tunnel to the gate through the forbidden
energy gap of the SiO2 layer [11].
D. Injection of Hot Carriers from Substrate to Gate Oxide (I4)
In a short-channel transistor, due to high electric field near the SiSiO2 interface, electrons or holes can gain
sufficient energy from the electric field to cross the interface potential barrier and enter into the oxide layer.
This effect is known as hot-carrier injection. The injection from Si to SiO2 is more likely for electrons than
holes, as electrons have a lower effective mass than that of holes, and the barrier height for holes (4.5 eV) is
more than that for electrons (3.1 eV) [12].
E. Gate-Induced Drain Leakage (I5)
GIDL is due to high field effect in the drain junction of an MOS transistor. When the gate is biased to form
an accumulation layer at the silicon surface, the silicon surface under the gate has almost same potential as
the p-type substrate. Due to presence of accumulated holes at the surface, the surface behaves like a p region
more heavily doped than the substrate. This causes the depletion layer at the surface to be much narrower
than elsewhere. The narrowing of the depletion layer at or near the surface causes field crowding or an
increase in the local electric field, thereby enhancing the high field effects near that region [13]. When the
Leakage Power Optimization of Standard Cells Using Gate-Length Biasing, Multiple Vt & Multi Channel Technique


negative gate bias is large (i.e., gate at zero or negative and drain at VDD), the n+ drain region under the
gate can be depleted and even inverted. This causes more field crowding and peak field increase, resulting
in a dramatic increase of high field effects such as avalanche multiplication and BTBT [13]. The possibility
of tunneling via near-surface traps also increases. As a result of all these effects, minority carriers are emitted
in the drain region underneath the gate. Since the substrate is at a lower potential for minority carriers, the
minority carriers that have been accumulated or formed at the drain depletion region underneath the gate are
swept laterally to the substrate, completing a path for the GIDL [14]. Thinner oxide thickness and higher
VDD (higher potential between gate and drain) enhance the electric field and therefore increase GIDL. The
impact of drain and well doping on GIDL is rather complicated. At low drain doping, the electric field is not
high enough to cause tunneling. At very high drain doping, the depletion widthand, therefore, the
tunneling volumeare limited, causing less GIDL. Hence, GIDL is worse for moderate drain doping (in
between the extremes previously mentioned), where both the electric field and depletion width (tunneling
volume) are considerable. Very high and abrupt drain doping is preferred for minimizing GIDL, as it
provides lower series resistance required for high transistor drive currents [15].
F. Punchthrough (I6)
In short-channel devices, due to the proximity of the drain and the source, the depletion regions at the drain-
substrate and source-substrate junctions extend into the channel. As the channel length is reduced, if the
doping is kept constant, the separation between the depletion region boundaries decreases. An increase in
the reverse bias across the junctions (with increase in Vds) also pushes the junctions nearer to each other.
When the combination of channel length and reverse bias leads to the merging of the depletion regions,
punchthrough is said to have occurred. In submicrometer MOSFETs, a Vth adjust implant is used to have a
higher doping at the surface than that in the bulk. This causes a greater expansion of the depletion region
below the surface (due to smaller doping there) as compared to the surface. Thus, the punchthrough occurs
below the surface [16]. An increase in the drain voltage beyond the value required to establish the
punchthrough lowers the potential barrier for the majority carriers in the source. Thus, more of these carriers
cross the energy barrier and enter into the substrate, and the drain collects some of them. The net effect is
an increase in the subthreshold current. Furthermore, punchthrough degrades the subthreshold slope. The
device parameter commonly used to characterize the punchthrough is the punchthrough voltage VPT, which
estimates the value of for which the punchthrough occurs (i.e., the subthreshold current reaches a particular
value) at Vgs = 0. It is roughly estimated as the value of the Vds for which the sum of the widths of the drain
Leakage Power Optimization of Standard Cells Using Gate-Length Biasing, Multiple Vt & Multi Channel Technique


and source depletion regions is equal to effective channel length [16]. The most suitable method for
controlling the punchthrough is to use additional implants. A layer of higher doping at a depth equal to that
of the bottom of the junction depletion regions is one possible solution. Another approach could be to form
a halo implant at the leading edges of the drain and source junctions [16].
Leakage Reduction Techniques: -
For a CMOS circuit, the total power dissipation includes dynamic and static components during the active
mode of operation. In the standby mode, the power dissipation is due to the standby leakage current.
Dynamic power dissipation consists of two components. One is the switching power due to charging and
discharging of load capacitance. The other is short circuit power due to the nonzero rise and fall time of
input waveforms. The static power of a CMOS circuit is determined by the leakage current through each
transistor. The dynamic (switching) power and leakage power are expressed as
PD = CV
2
DD
PLEAK = ILEAK .Vdd
where is the switching activity; is the operation frequency; C is the load capacitance; Vdd is the supply
voltage; and is the cumulative leakage current due to all the components of the leakage current described in
Section 1. Due to all the leakage mechanisms, leakage current (power) increases dramatically in the scaled
devices. Particularly, with reduction of threshold voltage (to achieve high performance), leakage power
becomes a significant component of the total power consumption in both active and standby modes of
operation [17]. Hence, to suppress the power consumption in low-voltage circuits, it is necessary to reduce
the leakage power in both the active and standby modes of operation. The reduction in leakage current has
to be achieved using both process- and circuit-level techniques. At the process level, leakage reduction can
be achieved by controlling the dimensions (length, oxide thickness, junction depth, etc.) and doping profile
in transistors. At the circuit level, threshold voltage and leakage current of transistors can be effectively
controlled by controlling the voltages of different device terminals [drain, source, gate, and body (substrate)].
For short channel devices, with increasing of the gate length, the threshold voltage increases, so that the
leakage decreases exponentially and delay increases linearly [18]. The gate-length biasing (GLB) technology
increases the channel length of transistors to alter the threshold voltage and reduces leakage exponentially
in both active and standby modes, while delay increases linearly with increasing gate length [18].
Leakage Power Optimization of Standard Cells Using Gate-Length Biasing, Multiple Vt & Multi Channel Technique


Multiple threshold voltage techniques use both Low Vt and High Vt cells. Use lower threshold gates on non-
critical path while higher threshold gates off the critical path. This methodology improves performance
without an increase in power. Flip side of this technique is that Multi Vt cells increase fabrication
complexity. It also lengthens the design time. Improper optimization of the design may utilize more Low Vt
cells and hence could end up with increased power [19]. With the technologies shrinking to 90nm, 30nm
and below one of the common ways to reduce leakage power is to use multiple Vt libraries. Subthreshold
leakage varies exponentially with the Vt compare to the weaker dependence of delay over Vt [20].

II. Literature Survey
There are various method that have been formerly proposed to reduce leakage [21-26], but each method had
some drawback along with other limitations due to trade-off between power dissipation and delay. Standby
leakage reduction techniques focus mainly on reducing leakage of devices that are in an idle state, whereas
runtime leakage reduction techniques focus on reducing leakage of active devices. Notable standby
techniques are MTCMOS [9] and Substrate Biasing [23]. Among the previously proposed techniques, a
popular method is multiple threshold voltage assignment [24-26]. Multiple threshold voltages are used to
generate variants of an existing standard cell. High Vth cells are placed on non-critical paths and Low Vth
cells on critical paths. Most of the prior work focuses on cell-level Vth assignment, where all devices in a
cell have the same threshold voltage. The inherent asymmetries present in cells and circuit slack distributions
motivate the need for fine-grained optimization beyond the realm of cell-level assignment. Although Ref
[25] performs transistor-level Vth assignment, and use an exhaustive search method involving SPICE
simulations, making the variant generation runtime unacceptably large. Also, the high cost of the extra
masking steps required for different threshold implants limits the number of distinct Vt to a maximum of 2
or 3, constraining the available design space. Ref [26] proposes the use of small biases to device gate-lengths
for leakage reduction as well as leakage-variability reduction. We draw upon this idea to perform transistor-
level gate-length biasing. This method eliminates the high runtime, and limited design space constraints
associated with the techniques proposed in [25] and [26]. The need for a transistor level assignment scheme
is further motivated by the fact NMOS and PMOS devices have different Ioff/Ion dependencies on gate-
length [26], and that different devices in a cell affect cell characteristics differently. Ref [26] proposes biases
of less than 10% of nominal length. However, process and area considerations constrain the bias even further
and that are limited by bounds imposed by the technology.
Leakage Power Optimization of Standard Cells Using Gate-Length Biasing, Multiple Vt & Multi Channel Technique


Cell level biasing (CLB) and Transistor level biasing (TLB) [27] is technique for optimizing standard cell
library for low power leakage, but it is very less significant optimization of power as technology shrink. In
TLB techniques they come up with ideas of
1.) Taxonomization of various cell-variant classes
2.) Efficient algorithms to systematically augment a standard cell library to drive power design optimization.
Sub-threshold Standard Cell Library (SCL) Design has been proposed in References [28]. It designed SCL
according to sub threshold region of CMOS. Other work similar to standard cell design is based on leakage
optimization using dual threshold voltage cell library [29]. In this work where transistors within the same
cell are allowed to have different Vth to form the so-call mixed Vth (MVT) cell. However, it is impractical
to build a full MVT cell library and include it in the standard dual Vth design flow. To make this practical,
current approach adds another design phase after technology mapping to replace high leakage cells with
their low leakage MVT variants.
Ref [30] as in Ref [26], the same work carried by the author to overcome previous problem and it uses
channel length biasing for both low threshold & high threshold. In this experiment gate length biasing
reduced leakage power 24% to 38% for most commonly used cells. Gate length biasing based standard cell
library has proposed in References [30]. It optimized significant leakage power compared to other work.
In Ref [31] provide a method, system, and computer usable program product for multiple threshold voltage
cell (MVt) families based integrated circuit design Where the integrated circuit includes cells, and a cell
includes an electronic component. An embodiment initializes a design process by using cells from the MVt
families in the design. The embodiment includes the cells from the MVt families in iterative manipulation
of the design. The embodiment further includes the cells from the MVt families in violation clean-up and
subsequent steps of the design process. The embodiment produces a version of the design usable to
implement the circuit with the cells from the MVt families.
In this project, we proposed a Standard Cell library based on Gate length biasing (GLB) [32], Multi
Threshold voltage (MVt) and Multi-Channel cell libraries. Expected result from this work can have more
significant leakage power optimization compare to previous work. In Ref [32] has taken 130nm technology
libraries from SMIC. This project aims to work on 45nm technology libraries.
Leakage Power Optimization of Standard Cells Using Gate-Length Biasing, Multiple Vt & Multi Channel Technique


In Ref [33-34], below 65nm most of library cells using Multi channel techniques to reduce the leakage
power. 130nm 65nm Synopsys library uses multi Vt techniques & GLB, while below 65nm they use multi-
channel techniques to get multi Vt in library cell design

III. Project Description
Standard Cell Design
A standard cell library is a collection of basic building blocks providing Boolean logic functions (e.g. AND,
OR, NOT), storage functions (e.g. flip-flop) and physical design assistances. Our SCL development flow is
shown in Figure 3. Initially, the standard cell dimension is scaled to meet the design requirement with
simulation at global corners passed, followed by the layout drawing with no any DRC and LVS violations
encountered. Afterwards, cell characterization will be performed to extract timing, power and functionality
information that are included in the liberty format (.lib) file of the library. Meanwhile, the abstract view of
a cell will be generated from the corresponding layout, and the library exchange format (.lef) file is created.
Both the liberty format and exchange format files will be imported into the place and route tool for design
optimization and design layout automatic generation.

Figure 3. SCL development flowchart
Standard Cell Characterization: - Cell characterization is performed to generate timing models of the
library that are used for synthesizing behaviour codes of a design and also the timing optimization during
Leakage Power Optimization of Standard Cells Using Gate-Length Biasing, Multiple Vt & Multi Channel Technique


the place and route step. The library characterization process of a standard cell library is highlighted in
Figure 4. The main inputs are:
A SPICE-format netlist that contains the detailed transistor devices, resistance and capacitance for
each cell.
A setup file that have all the information about simulation condition (e.g. corners, voltage,
temperature, input slew, output loading).
A SPICE model file provided by foundry.
These files are passed to the Encounter Library Characterizer to generate a library database that contains
timing, power and logic function for each of the cells, namely, the liberty format (.lib) for synthesis,
placement and routing.

Figure 4. Library characterization process
Standard cell characterization is process to generate .lib file that we can use for synthesis and place & route
of the design.
The project aims to design different standard cell libraries using Gate Length Biasing, Multi-threshold
voltage and multi-channel techniques. These design cells go through standard cell characterisation process
to generate .lib file. A Perl script will be developed to automate the spice simulation for calculating leakage
power of standard cells and correlating the data with standard library.


Leakage Power Optimization of Standard Cells Using Gate-Length Biasing, Multiple Vt & Multi Channel Technique


Tools Used: Cadence spectre spice tool, Cadence Encounter, Autolib generator.
Library Used: TSMC 45nm layout netlist, TSMC 45nm Standard cell Library, Tech file, UPF file.

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