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Design of Efficient FIR Filter MAC unit Using

Parallel Prefix Adder


J.Ravi
Student, M.Tech , Department of Electronics &
Communication Engineerig, Indur Institute of Engineering
.Rama Rao
!ssociate "rofessor, Department of Electronics &
Communication Engineerig, Indur Institute of Engineering
& Technolog#, Siddipet, Meda$, J%T&' &niversit#, & Technolog#, Siddipet, Meda$, J%T&' &niversit#,
Telangana, India. Telangana, India.
(ravi)*+,gmail.com $ali$ivoi,gmail.com
Abstract- Digital Signal Processing (DSP) is a field of Utmost
imortance as it erforms t!e rocessing of a digital signal"
DSP tec!ni#ues imro$e signal #ualit% or extract imortant
information b% remo$ing un&anted arts of t!e signal" '!is
extraction of t!e un&anted arts of t!e signal is ossible
&it! t!e !el of filters" A Finite Imulse Resonse (FIR)
filters la% a crucial role in man% of t!e signal rocessing
alications" '!e outut is comuted using Multil% and
Accumulate (MAC) oerations" '!e functionalit% of MAC
unit enables !ig!(seed filtering and ot!er rocessing
t%ical for DSP alications" A MAC unit consists of a
multilier and accumulator" In t!is aer multilier is
designed using modified )allace multilier and t!e adder
used is Parallel Prefix Adder and is comared &it! ot!er
adders t!at is Carr% Sa$e Adder and Carr% Select Adder"
'!is Paer Presents Design of *o& Po&er and +ig! Seed
MAC unit &it! Modified )allace Multilier and Parallel
Prefix Adder (,ogge(Stone adder) for FIR filter" And it also
gi$es t!e Comarison of t!ree adders (Parallel Prefix Adder-
Carr% Sa$e Adder- and Carr% Select Adder) in Case of
Po&er- Dela% and Area" Modified )allace multilier &it!
t!ree different adders !as been &ritten Coded in .+D* and
t!en s%nt!esi/ed and simulated using 0ilinx ISE 1"2i" '!e
MAC unit &!ic! designed b% using Modified )allace
Multilier and Parallel Prefix adder !as consumes less
Po&er and !as less dela% b% &!en comared &it! ot!er
adders"
,e%&ords( Modified Wallace multiplier, Parallel prefix
adder, Kogge-Stone adder, Carry Select adder, Carry Save
adder.
I. INTRODUCTION
M!C unit is an inevita-le component in man# digital signal
processing .DS"/ applications involving multiplications
and0or accumulations. M!C unit is used for high performance
digital signal processing s#stems. The DS" applications
include filtering, convolution, and inner products. Most of
digital signal processing methods use nonlinear functions such
as discrete cosine transform .DCT/ or discrete 1avelet
transforms .D2T/. 3ecause the# are -asicall# accomplished
-# repetitive application of multiplication and addition, the
speed of the multiplication and addition arithmetic determines
the e4ecution speed and performance of the entire calculation
567. Multiplication8and8accumulate operations are t#pical for
digital filters. Therefore, the functionalit# of the M!C unit
ena-les high8speed filtering and other processing t#pical for
DS" applications. Since the M!C unit operates completel#
independent of the C"&, it can process data separatel# and
there-# reduce C"& load. The application li$e optical
communication s#stems 1hich is -ased on DS", re9uire
e4tremel# fast processing of huge amount of digital data. The
:ast :ourier Transform .::T/ also re9uires addition and
multiplication. *) -it can handle larger -its and have more
memor#.
! M!C unit consists of a multiplier and an accumulator
containing the sum of the previous successive products. The
M!C inputs are o-tained from the memor# location and given
to the multiplier -loc$. The design consists of *) -it modified
2allace multiplier, 6;+ -it carr# save adder and a register.
This paper is divided into seven sections. In the first section
the introduction a-out M!C unit is discussed. In the second
section discuss a-out the detailed operation of M!C unit. The
third and fourth section deals 1ith the operation of modified
2allace multiplier and "arallel "refi4 !dder respectivel#. In
the fifth and si4th section deals 1ith carr# save adder and
carr# select adder. In the Seventh section o-tained result for
the *) -it M!C unit is discussed and finall# the conclusion is
made in the eighth section.
II. MAC OPERATION
The Multiplier8!ccumulator .M!C/ operation is the $e#
operation not onl# in DS" applications -ut also in multimedia
information processing and various other applications. !s
mentioned a-ove, M!C unit consist of multiplier, adder and
register0accumulator. In this paper, 1e used *) -it modified
2allace multiplier. The M!C inputs are o-tained from the
memor# location and given to the multiplier -loc$. This 1ill
-e useful in *) -it digital signal processor. The input 1hich is
-eing fed from the memor# location is *) -it. 2hen the input
is given to the multiplier it starts computing value for the
given *) -it input and hence the output 1ill -e 6;+ -its. The
multiplier output is given as the input to carr# save adder
1hich performs addition.
The function of the M!C unit is given -# the
follo1ing e9uation 5)7<
:= > "(?( 8888888888 .6/
The output of carr# save adder is 6;@ -it i.e. one -it is for
the carr# .6;+-itsA 6 -it/. Then, the output is given to the
accumulator register. The accumulator register used in this
design is "arallel in "arallel out ."I"B/. Since the -its are
huge and also carr# save adder produces all the output values
in parallel, "I"B register is used 1here the input -its are ta$en
in parallel and output is ta$en in parallel. The output of the
accumulator register is ta$en out or fed -ac$ as one of the
input to the carr# save adder. The figure 6 sho1s the -asic
architecture of M!C unit.
Figure: 1 Basic architecture of MAC unit
IIIMODIFIED !A"" ACE MU"TIP"IER
! modified 2all ace multiplier is an efficient
'ard1are implementation of digital circuit multipl#ing t1o
integers. Cenerall# in conventional 2allace multipliers man#
full adders and half adders are used in their reduction phase.
'alf adders do not reduce the num-er of partial product -its.
Therefore, minirniDing the num-er of half adders used in a
multiplier reduction 1ill reduce the comple4it# 5;7. 'ence, a
modification to the 2allace reduction is done in 1hich the
dela# is the same as for the conventional 2allace reduction.
The modified reduction method greatl# reduces the num-er of
half adders 1ith a ver# slight increase in the num-er of full
adders 5;7. Reduced comple4it# 2all ace multiplier reduction
consists of three stages 5;7. :irst stage the % 4 % product
matri4 is formed and -efore the passing on to the second phase
the product matri4 is rearranged to ta$e the shape of inverted
p#ramid. During the second phase the rearranged product
matri4 is grouped into non8overlapping group of three as
sho1n in the figure ;, single -it and t1o -its in the group 1ill
-e passed on to the ne4t stage and three -its are given to a full
adder. The num-er of ro1s in the in each stage of the
reduction phase is calculated -# the formula
r(A 6= ;5r(0E7Ar(modE 888888888 .;/
If r( modE = F, then r(A 6 = ;r0E 88888888 .E/
If the value calculated from the a-ove e9uation for
%um-er of ro1s in each stage in the second phase and the
num-er of ro1 that are formed in each stage of the second
phase does not match, onl# then the half adder 1ill -e used.
The final product of the second stage 1ill -e in the height of
t1o -its and passed on to the third stage. During the third
stage the output of the second stage is given to the carr#
propagation adder to generate the final output.
Figure: # Mo$ifie$ !a%%ace 1&-'it '( 1&-'it re$uction
Thus *) -it modified 2allace multiplier is constructed and
the total num-er of stages in the second phase is 6F. !s per the
e9uation the num-er of ro1 in each of the 6F stages 1as
calculated and the use of half adders 1as restricted onl# to the
6F
th
stage. The total num-er of half adders used in the second
phase is + and the total num-er of full adders that 1as used
during the second phase is slightl# Since the *) -it modified
2allace multiplier is difficult to represent, a t#pical 6F8-it -#
6F8-it reduction sho1n in figure ; for understanding. The
modified 2allace tree sho1s -etter performance 1hen carr#
save adder is used in final stage instead of ripple carr# adder.
The carr# save adder 1hich is used is considered to -e the
critical part in the multiplier -ecause it is responsi-le for the
largest amount of computation. Increased that in the
conventional 2allace multiplier. Since the *) -it modified
2allace multiplier is difficult to represent, a t#pical 6F8-it -#
6F8-it reduction sho1n in figure ; for understanding. The
modified 2allace tree sho1s -etter performance 1hen three
adders are used once at a time in final stage instead of ripple
carr# adder. The "arallel "refi4 !dder 1hich is used is
considered to -e the critical part in the multiplier -ecause it is
responsi-le for the largest amount of computation.
IG. CARR) *A+E ADDER
In this design 6;+ -it carr# save adder 5*7 is used since the
output of the multiplier is 6;+ -its .;%/. The carr# save adder
minirniDe the addition from E num-ers to ; num-ers. The
propagation dela# is E gates despite of the num-er of -its. The
carr# save adder contains n full adders, computing a single
sum and carries -it -ased mainl# on the respective -its of the
three input num-ers. The entire sum can -e calculated -#
shifting the carr# se9uence left -# one place and then
appending a F to most significant -it of the partial sum
se9uence. %o1 the partial sum se9uence is added 1ith ripple
carr# unit resulting in n A 6 -it value. The ripple carr# unit
refers to the process 1here the carr#out of one stage is fed
directl# to the carr# in of the ne4t stage. This process is
continued 1ithout adding an# intermediate carr# propagation.
Since the representation of 6;+ -it carr# save adder is
infeasi-le , hence a t#pical + -it carr# save adder is sho1n in
the figure E5*7.'ere 1e are computing the sum of t1o 6;+ -it
-inar# num-ers, then 6;+ half adders at the first stage instead
of 6;+ full adder. Therefore , carr# save unit comprises of 6;+
half adders, each of 1hich computes single sum and carr# -it
-ased onl# on the corresponding -its of the t1o input
num-ers.
If 4 and # are supposed to -e t1o 6;+ -it num-ers then it
produces the partial products and carr# as S and C
respectivel#.

Si = Hi I Ji 8888888888 )
Ci = Hi & Ji 8888888888 K
During the addition of t1o num-ers using a half adder, t1o
ripple carr# adder is used. This is due the fact that ripple carr#
adder cannot compute a sum -it 1ithout 1aiting for the
previous carr# -it to -e

"roduced, and hence the dela# 1ill -e e9ual to that of n
full adders. 'o1ever a carr#8save adder produces all the
output values in parallel, resulting in the total computation
time less than ripple carr# adders. So, "arallel In "arallel But
."I"B/ is used as an accumulator in the final stage.

Figure: , - 'it carr( sa.e a$$er
G. PARA""E" PREFI/ ADDER
"arallel "refi4 adder is that it is primaril# fast 1hen compared
1ith ripple carr# adders. "arallel "refi4 adders .""!/ are
famil# of adders derived from the commonl# $no1n carr#
loo$ ahead adders. These adders are -est suited for adders
1ith 1ider 1ord lengths. ""! circuits use a tree net1or$ to
reduce the latenc# to B .log; n/ 1here Ln represents the
num-er of -its. "arallel "refi4 !dders .""!/ is variations of
the 1ell8$no1n carr# loo$ ahead adder .CM!/. The difference
-et1een a CM! and a ""! lies in the second stage 1hich is
responsi-le for the generation of the carr# signals of the -inar#
addition. ! parallel "refi4 !ddition is generall# a three step
process.
The first step involves the creation of generate .gi/ and
"ropagate .pi/ signals for the input operand -its. The second
step involves the generation of carr# signals and finall# a
simple adder to generate sum. The three stage structure of
carr# loo$ ahead adder and parallel prefi4 adder is sho1n

Figure: 0 three stage structure of the carr( %oo1 ahea$
an$ 2ara%%e% 2refi3 a$$er
"arallel8prefi4 adders, also $no1n as carr#8tree adders, pre8
compute the propagate and generate signals. These signals are
variousl# com-ined using the fundamental carr# operator
.fco/. 3eside fundamental carr# operator also $no1n as -lac$
operator or dot operator as sho1n in figure ; ,there is another
component called -uffer component 1hich translates the
generate and propagate signals. The t1o operators are sho1n
in the figure<
In a ) -it adder li$e the one sho1n in the picture to the right,
there are K outputs. 3elo1 is the e4pansion<
Figure: 4 5 'it 1ogge-stone a$$er
SF = .!F HBR 3F/ HBR
S6 = .!6 HBR 36/ HBR .!F !%D 3F/
S; = .!; HBR 3;/ HBR ...!6 HBR 36/ !%D .!F !%D
3F// BR .!6 !%D 36//
SE = .!E HBR 3E/ HBR ....!; HBR 3;/ !%D .!6 HBR
36// !%D .!F !%D 3F// BR ...!; HBR 3;/ !%D .!6
!%D 36// BR .!; !%D 3;///
S) = .!) HBR 3)/ HBR ....!E HBR 3E/ !%D .!; HBR
3;// !%D .!6 !%D 36// BR ...!E HBR 3E/ !%D .!;
!%D 3;// BR .!E !%D 3E///
III. CARR) *E"ECT ADDER
In electronics, a carr#8select adder is a particular 1a#
to implement an adder, 1hich is a logic element that computes
the .nA6/ -it sum of t1o 8-it num-ers. The carr#8select
adder is simple -ut rather fast, having a gate level depth of
BNn.
The carr#8select adder generall# consists of t1o
ripple carr# adders and a multiple4er. !dding t1o n8-it
num-ers 1ith a carr#8select adder is done 1ith t1o adders
.therefore t1o ripple carr# adders/ in order to perform the
calculation t1ice, one time 1ith the assumption of the carr#
-eing Dero and the other assuming one. !fter the t1o results
are calculated, the correct sum, as 1ell as the correct carr#, is
then selected 1ith the multiple4er once the correct carr# is
$no1n.
Figure: 6 5 'it carr( *e%ect a$$er
IG. RE*U"T
The design is developed using in G'DM and then
s#nthesiDed and simulated using Hilin4 ISE @.;i. !nd "o1er
Calculations have found for Different M!C &nit .1ith
different adders/ using Hilin4 !nal#se "o1erH.
Figure: - 5 *i7u%ation re2ort of ,5 'it 5 Ta2 fir fi%ter
Mac Unit
! Multiplier is designed Modified Multiplier and 1ith Three
adders .Carr# Save !dder, Carr# Select !dder and "arallel
"refi4 !dder/. !rea, "o1er and Dela# results are "resent
3elo1
POWER CALCULATIONS:
8ra2h 1: Co72arison 8ra2h 'et9een M!C*A:
M!C*"A an$ M!PPA

M2CS!< Modified 2allace Carr# save !dder
M2CSM!< Modified 2allace Carr# Select !dder
M2""!< Modified 2allace "arallel "refi4 !dder
AREA COMPARI*ION: ;On%( A$$ers<
De.ice Uti%i=ation *u77ar(
"ogic
Uti%i=ation
Use$ '(
C*A
Use$ '(
C*"A
Use$ '(
PPA
No of *%ices #&0- #165 #40>
No of *%ice
F%i2 F%o2
#&5 #&0 #&0
No of ?
in2ut
"UT@s
0,-0 0>55 5,50
No of
Boun$e$
IAO@s
0-6 0-6 0-6
DE"A) COMPARI*ION: ;On%( A$$ers<
G. CONC"U*ION
'ence a design of 'igh Speed "o1er Efficient and Mess
Dela# *) -it ) T!" :IR :ilter Multiplier and !ccumulator
.M!C/ &nit is designed in this paper. The total estimated
po1er consumed -# *) -it M!C unit .2hich is designed
using Modified 2allace Multiplier and "arallel "refi4 !dder/
is #-> 7! The total Dela# Time for "arallel "refi4 !dder
1hen compared to other adders is #,,,> ns Since the dela#
of *) -it is less, this design can -e used in the s#stem 1hich
re9uires high performance in processors involving large
num-er of -its of the operation. The M!C unit is designed
using G'DM and then s#nthesiDed and simulated using Hilin4
ISE @.;i.
REFERENCE*

Total estimated power
consumption
MWCSA !" mW
MWCSLA #$mW
MWPPA %&'mW
567.Joung8'o Seo and Dong82oo$ im, O%e1 GMSI
!rchitecture of "arallel Multiplier8!ccumulator 3ased on
Radi48; Modified 3ooth !lgorithm,O IEEE Transactions on
ver# large scale integration .vlsi/ s#stems, vol. 6+, no.
;,fe-ruar# ;F 6F
.;/. Ron S. 2aters and Earl E. S1artDlander, Jr., O! Reduced
Comple4it# 2all ace Multiplier Reduction, O IEEE
Transactions on Computers, vol. K@, no. +, !ug ;F 6F
5E7. C. S. 2allace, O! suggestion for a fast multiplier,O IEEE
Trans. ElectronComput., vol. EC86E, no. I, pp. 6)86P, :e-.
6@*)
5)7. Shanthala S, C#ril "rasanna Ra(, Dr.S.J.ul$arni,
ODesignand GMST Implementation of "ipelined Multipl#
!ccumulate &nit,O IEEE International Conference on
Emerging Trends in Engineering and Technolog#, ICETET8F@
5K7. 3.Ram$umar, 'arish M ittur and ".Mahesh annan,
O!SIC Implementation of Modified :aster Carr# Save !dder
O, European Journal of Scientific Research, Gol. );, Issue 6,
;F6F.
5*7. 2J. To1nsend, E.E. S1artDlander Jr., and J.!. !-raham,
O! Comparison of Dadda and 2all ace Multiplier Dela#s,O
"roc. S"IE, !dvanced Signal "rocessing !lgorithms,
!rchitectures, and Implementations HIII, pp. KK;8K*F, ;FFE
5P7. :a-riDio Mam-erti and %i$os !ndri$os, O Reducing the
Computation Time in .Short 3it82idth/ T1oQs Complement
MultipliersO, IEEE transactions on computers, Gol. *F, %B. ;,
:E3R&!RJ ;F 6 6
5+7 J. im and M.8S. im, R*)8-it carr#8select adder 1ith
reduced area,S Electron. Lett., vol. EP, no. 6F, pp. *6)T*6K,
Ma# ;FF6.
5@7 J. M. Ra-ae#, Digtal Integrated CircuitsA Design
Perspective. &pper Saddle River, %J< "rentice8'all, ;FF6.
56F7 J. 'e, C. '. Chang, and J. Cu, R!n area efficient *)8-it
s9uare root carr#8select adder for lo1po1er applications,S in
Proc. IEEE Int. Symp.Circuits Syst., ;FFK, vol. ), pp. )F+;T
)F+K.
5667 Cadence, REncounter user guide,S Gersion *.;.), March
;FF+.
56;7 ".Ramanathan, ".T.Ganathi, R%ovel "o1er Dela#
BptimiDed E;8-it"arallel "refi4 !dder for 'igh Speed
ComputingS, International Journal of Recent Trends in
Engineering, Gol ;, %o. *, %ovem-er ;FF@.
56E7 R. Uimmermann, 3inar# !dder !rchitectures for Cell8
3ased GMSI and their S#nthesis, ET' Dissertation 6;)+F,
S1iss :ederal Institute of Technolog#, 6@@P.
56)7 David 'arris, R! Ta4onom# of parallel prefi4 net1or$s,S
"roceedings of the EPth !silomar Conference on Signals,
S#stems and Computers "acific Crove, California, pp.;;6E8
;;6P, %ovem-er ;FFE.
56K7 no1les, R! famil# of addersS, "roceedings of the 6Kth
IEEE S#mposium on Computer !rithmetic. Gail, Colorado,
pp.;PP8;+6, June;FF6.