MSR PROJECTS

(AN SSI CERTIFIED INSTITUTION)

TRAINING | DEVELOPMENT |
PLACEMENTS
VLSI IEEE-2014 PROJECTS LIST (M.Tech)
CODE TITLE EAR
MSR01
A novel approach to realize Built-in-self-test(BIST) enabled
ART usin! "#$%
&01'
MSR0&
A h(brid-radi) approach for efficient i*ple*entation of unfolded
+,R$I+ architectures for -./A platfor*s0
&01'
MSR01
#i!h throu!hput architecture for the Advanced 2ncr(ption
Standard Al!orith* &01'
MSR0' Area-$ela( 2fficient Binar( Adders in 3+A &01'
MSR04
+o**ents on Self-+hec5in! +arr(-Select Adder $esi!n Based on
T6o-Rail 2ncodin!
&01'
MSR07
A $eci*al Binar( Multi-operand Adder usin! a -ast Binar( to
$eci*al +onverter
&01'
MSR08 .ipelined Architecture for "edic Multiplier &01'
MSR09
I*ple*entation of #i!h Speed %o6 .o6er +o*binational and
Se:uential +ircuits usin! Reversible lo!ic
&01'
MSR0; #i!h Speed +onvolution and $econvolution Al!orith* &01'
MSR010
$esi!n and Si*ulation of .o6er 2fficient Traffic
%i!ht +ontroller (.T%+)
&01'
MSR011
I*ple*entation of R</ in -./A usin! 2fficientResource
tilization
&011
MSR01& Multi operand Redundant Adders on -./As0 &011
MSR011 17-Bit =ave-.ipelined Sparse-Tree RS-3 Adder0 &011
MSR01'
A #i!h Speed Binar( -loatin! .oint Multiplier sin! $adda
Al!orith*0
&011
Head Ofce: #302, 3
nd
Floor, Gyan Arcade, Ammerpet, HYDERABAD-00 0!2"
E-ma#l: m"$"r"pro%ect$"#eee&'ma#l"com, (e): Face)oo*"com+m"$"r"pro%ect , R#n'
on: ,-. -!./0/./2
MSR PROJECTS
(AN SSI CERTIFIED INSTITUTION)
TRAINING | DEVELOPMENT |
PLACEMENTS
MSR014
An -./A Based #i!h Speed Ieee-84' $ouble .recision -loatin!
.oint Multiplier sin! "erilo! #$%0
&011
MSR017
I*ple*entation And +o*parison ,f 2ffective Area 2fficient
Architectures -or +S%A0
&011
MSR018 $esi!n A $S. ,perations sin! "edic Mathe*atics0 &011
MSR019
$esi!n of #i!h Speed %o6 .o6er Multiplier sin! Reversible
%o!ic> A "edic Mathe*atical Approach0
&011
MSR01;
<ovel #i!h Speed "edic Mathe*atics Multiplier sin!
+o*pressors0
&011
MSR0&0 $esi!n ,f hi!h .erfor*ance 7' Bit MA+ nit0 &011
&10%o6 po6er S:uare and +ube Architectures sin! "edic Sutras ( &01' I222 )
&0#i!h Speed "edic Multiplier $esi!ns ( &01' I222 )
10 Binar( $ivision .o6er Models for #i!h-%evel .o6er 2sti*ation of -./A-Based $S.
+ircuits ( &01' I222 )
'0$esi!n of $edicated Reversible 3uantu* +ircuitr( for S:uare +o*putation ( &01' I222 )
40ASI+ $esi!n of Reversible Multiplier +ircuit ( &01' I222 )
70All ,ptical Reversible Multiple)er $esi!n usin! Mach-?ehnder Interfero*eter ( &01'
I222 )
80+ircuit for Reversible 3uantu* Multiplier Based on Binar( Tree ,pti*izin! Ancilla and
/arba!e Bits ( &01' I222 )
90$esi!n of 2fficient Binar( +o*parators in 3uantu*-$ot +ellular Auto*ata ( &01' I222 )
;02li*inatin! S(nchronization %atenc( sin! Se:uenced %atchin! ( &01' I222 )
100Area-$ela( 2fficient Binar( Adders in 3+A ( &01' I222 )
110"%SI I*ple*entation ,f -ast Addition sin! 3uaternar( Si!ned $i!it <u*ber
S(ste*( &011 I222
Head Ofce: #302, 3
nd
Floor, Gyan Arcade, Ammerpet, HYDERABAD-00 0!2"
E-ma#l: m"$"r"pro%ect$"#eee&'ma#l"com, (e): Face)oo*"com+m"$"r"pro%ect , R#n'
on: ,-. -!./0/./2
MSR PROJECTS
(AN SSI CERTIFIED INSTITUTION)
TRAINING | DEVELOPMENT |
PLACEMENTS
1&0$esi!n And I*ple*entation ,f Truncated Multipliers -or .recision I*prove*ent0 ( &011
I222 )
Head Ofce: #302, 3
nd
Floor, Gyan Arcade, Ammerpet, HYDERABAD-00 0!2"
E-ma#l: m"$"r"pro%ect$"#eee&'ma#l"com, (e): Face)oo*"com+m"$"r"pro%ect , R#n'
on: ,-. -!./0/./2