What is VHDL and Verilog?

In what cases do you need to double clock a signal before presenting it to a synchronous state
machine?
What is meant by term snooping?
What is meant by the term MEI?
E!plain the difference between write through and write back cache" ?
What are the main issues associated with multiprocessor caches and how they can be sol#ed ?
E!plain the operation considering a two processor computer system with a cache for each processor
?
$or a single computer processor computer system% what is the purpose of a processor cache and
describe its operation?
How many bit combinations are there in a byte?
E!plain about pipelining? List the & stages of a & stage pipeline" 'ssuming ( clock per stage% what is
the latency of an instruction in a & stage machine? What is the throughput of this machine ?
E!plain the Insights of a )ri*tate In#erter?
Which gate is normally preferred while implementing circuits using +M, logic% -'-D or -,.?
Why?
E!plain the concept of a +lock Di#ider +ircuit? Write a VHDL code for the same?
Differences between 'rray and /ooth Multipliers?
If an0ap 1 2"&% an0ap 1 (% an0ap 1 3% for 3 in#erters draw the transfer characteristics?
What is $owler*-ordheim )unneling?
Implement an In#erter using a single transistor?
What is clock feed through?
What are the phenomenon which come into play when the de#ices are scaled to the sub*micron
lengths?
Different ways of implementing a comparator?
What is +ross )alk?
What is #alidation?
Who pro#ides the D.+ rules?
What is LV% D.+?
Why is E!traction performed?
E!plain +ustom Design $low?
E!plain 'I+ Design $low?
E!plain the Various steps in ynthesis?
E!plain the #arious +apacitances associated with a transistor and which one of them is the most
prominent?
Why do we use a +lock tree?
E!plain +lock kew?
$actors affecting 4ower +onsumption on a chip?
Define threshold #oltage?
What is hot electron effect?
What is component binding?
Differences between functions and 4rocedures in VHDL?
Differences between ignals and Variables in VHDL? If the same code is written using ignals and
Variables what does it synthesi5e to?
Differences between blocking and -on*blocking statements in Verilog?
What is 6*) 7,. gate?
E!plain the Working of a 8*stage ,4'M4?
Implement $ 1 '/9+ using +M, gates?
If the current through the poly is 82n' and the contact can take a ma!imum current of (2n' how
would you o#ercome the problem?
Draw the Layout of an In#erter?
Draw the +ross ection of an In#erter? +learly show all the connections between M( and poly% M(
and diffusion layers etc?
What is $4:'?
Differences between netlist of H4I+E and pectre?
Differences between I.IM and 4I+E?
What is 4I+E?
E!plain about stuck at fault models% scan design% /I) and IDD; testing?
What is pipelining and how can we increase throughput using pipelining?
Write a pseudo code for sorting the numbers in an array?
What is setup time and hold time?
What happens when the gate o!ide is #ery thin?
How can you construct both 4M, and -M, on a single substrate?
Implement a function with both rationed and domino logic and merits and demerits of each logic?
List out the differences between D.'M and .'M?
E!plain the operation of a 6)*.'M cell?
E!plain Id #s" Vds +haracteristics of -M, and 4M, transistors?
:i#e an 'd#antages and disad#antages of Mealy and Moore?
' circuit has ( input 7 and 8 outputs ' and /" If 7 1 HI:H for < clock ticks% ' 1 (" If 7 1 L,W for <
clock ticks% / 1 (" Draw a state diagram for this pec?
E!plain the working of <*bit =p0down +ounter?
E!plain #arious adders and differences between them?
$or f 1 '/9+D if / is *a*(% what are the test #ectors needed to detect the fault?
What are the Insights of a <bit adder0ub +ircuit?
Implement a 8 I04 and gate using )ran gates?
What is a linked list? E!plain the 8 fields in a linked list?
While using logic design% e!plain the #arious steps that are followed to obtain the desirable design in
a well defined manner?
What is charge sharing?
What is latchup? E!plain the methods used to pre#ent it?
Implement D flip*flop with a couple of latches? Write a VHDL +ode for a D flip*flop?
Differences between D*Latch and D flip*flop?
What is a D*latch? Write the VHDL +ode for it?
E!plain the +ross section of an -M, transistor?
E!plain the +ross section of a 4M, transistor?
What does the abo#e code synthesi5e to?
Why do we need both 4M, and -M, transistors to implement a pass gate?
Implement $1 not >'/9+D? using +M, gates?
What are the Insights of a 8 input -'-D gate" E!plain the working?
What are the Insights of a 8 input -,. gate" E!plain the working?
E!plain the Insights of an in#erter and its working?
What transistor le#el design tools are you proficient with? What types of designs were they used on?
E!plain the difference between write through and write back cache ?
What are the main issues associated with multiprocessor caches and how might you sol#e them?
E!plain the operation considering a two processor computer system with a cache for each processor
?
$or a single computer processor computer system% what is the purpose of a processor cache and
describe its operation?
What is interrupt latency?
How do you detect if two @*bit signals are same?
What are set up time and hold time constraints? What do they signify?
uppose you ha#e a combinational circuit between two registers dri#en by a clock" What will you do
if the delay of the combinational circuit is greater than your clock signal? E!plain the usage of the
shared 4I bus?
How to find the read failure probability in .'M?
What are the ways to ,ptimi5e the 4erformance of a Difference 'mplifier?
How can you model a .'M at .)L Le#el?
In a .'M layout% which metal layers would you prefer for Word Lines and /it Lines? Why?
What is the critical path in a .'M?
What happens if we use an In#erter instead of the Differential ense 'mplifier?
E!plain the +harge haring problem while sampling data from a /us?
:i#e the #arious techniAues you know to minimi5e power consumption?
What happens if we increase the number of contacts or #ia from one metal layer to the ne!t?
How does .esistance of the metal lines #ary with increasing thickness and increasing length?
What are the limitations in increasing the power supply to reduce delay?
What happens to delay if you increase load capacitance?
What is /ody Effect?
:i#e the e!pression for +M, switching power dissipation?
What is -oise Margin? E!plain the procedure to determine -oise Margin?
How do you si5e -M, and 4M, transistors to increase the threshold #oltage?
E!plain si5ing of the in#erter?
E!plain +M, In#erter transfer characteristics?
E!plain the #arious M,$E) +apacitances B their significance?
E!plain why B how a M,$E) works?
E!plain the +harge haring problem while sampling data from a /us?
What happens if we delay the enabling of +lock signal?
What is Latch up? How to a#oid Latch up?
How can you model a .'M at .)L Le#el?
What is the difference between )esting B Verification?
What happens if we delay the enabling of +lock signal?
What is the critical path in a .'M?
What happens if we use an In#erter instead of the Differential ense 'mplifier?
E!plain the working of differential sense amplifier?
Why donCt we use Dust one -M, or 4M, transistor as a transmission gate?
What is charge sharing?
:i#e the e!pression for calculating Delay in +M, circuit?
What happens to delay if we include a resistance at the output of a +M, circuit?
What are the different limitations in increasing the power supply to reduce delay?
What happens to delay if you increase load capacitance?
:i#e the e!pression for +M, switching power dissipation?
What is -oise Margin? E!plain the procedure to determine -oise Margin?
How do you si5e -M, and 4M, transistors to increase the threshold #oltage?
E!plain the si5ing of the in#erter?
E!plain the #arious M,$E) +apacitances B their significance ?
E!plain how M,$E) works?
How to impro#e these parameters? >+ascode topology% use long channel transistors?
How about #oltage source?
What is short +hannel effect ?
What is Early effects and their physical origin ?
E!plain the working of /E) ?
What is the ideal input and output resistance of a current source?
How does a /andgap Voltage reference work?
$or a 2"(@um and 2"@um technology M,$E)% which has a higher cutoff freAuency?
E!plain how M,$E) works ?
What is the build*in potential?
What are the two types of noise of M,$E)% how to eliminate them?>)hermal and $licker?"
What is the depletion region?
How does a pn Dunction works?
What is the doping?
What is +hannel length modulation?
If the substrate doping concentration increase% or temperature increases% how will Vt change? it
increase or decrease?
How does Vbe and Ic change with temperature?
What is $ermi le#el?
What is conductance and #alence band?