Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
S – L / MCT – SKCET1
Prepared By,
C.SIVAKUMAR,
L / MCT
2 MARKS QUESTIONS
1. What is Microprocessor?
2. What are the basic units of a microprocessor?
3. Define hardware and software?
4. What is an assembly language?
5. What is a low level language?
6. What is a high level language?
7. Differentiate compiler and an interpreter?
8. What is assembler?
9. What is cross assembler programs?
10. Define operating system?
11. What is Microcomputer?
12. What are the advantages of an assembly language in comparison with
high level languages?
13. What are the advantages of high level language in comparison with the
assembly languages?
14. Draw the block diagram of a microcomputer
15. Define bit, byte, word and instruction
16. What is a bus?
17. Define MPU
18. List the four operations commonly performed by the MPU?
19. Define the address bus
20. Mention the steps; the MPU needs to communicate with the peripheral.
21. Define data bus
22. Why 8085 is known as 8 – bit microprocessor?
23. Define control bus?
24. Why is the data bus bidirectional?
25. Why is the address bus unidirectional
26. How much memory location can be addressed by a microprocessor with n
address lines?
27. Specify the four control signals commonly used by the 8085 MPU?
28. How a 8085 microprocessor can qualify as an MPU.
29. List the four categories of 8085 instructions that manipulate data.
30. How many instructions are available in 8085 instruction set?
31. How 8085 microprocessor operations are classified?
32. Define opcode and operand?
33. How 8085 instructions are classified according to the work size or byte
size?
34. What is addressing and what are the addressing modes available in 8085.
35. Explain the immediate addressing with an example
36. Direct Addressing.
TWO MARKS
1. What is Microprocessor?
¾ Microprocessor is a multipurpose, programmable clock driven register based
electronic device that reads binary information from a storage device called
memory; accepts binary data as input and processes data according to those
instructions, and provides results.
¾ Interpreter reads are instruction at a time, produces its object code and executes the
instruction before reading the next instruction.
8. What is assembler?
¾ The assembler is a program that translates the mnemonics entered by the ASCII
keyboard into the corresponding binary machine codes of the microprocessor.
9. What is cross assembler programs?
¾ Cross – assemblers can be used to translate the 8085 mnemonics into appropriate
machine codes.
13. What are the advantages of high level language in comparison with
the assembly languages?
¾ The primary advantage of high – level language is in troubleshooting (debugging)
programs. It is much easier to find errors in a program written in a high – level
language than to find them in a program written in an assembly language.
29. List the four categories of 8085 instructions that manipulate data.
i. Data Transfer (copy) Instructions
ii. Arithmetic instructions.
iii. Logical instructions.
iv. Branch Instructions
Opcode:
Operation code is the task to be performed.
Operand:
Operand is the data to be operated on
Example:
MOV C, A Operand [C, A]→ Opcode [MOV]
33. How 8085 instructions are classified according to the work size or
byte size?
Instruction set is classified according to the word size as,
i. 1 - byte instructions
ii. 2 – byte instructions
iii. 3 – byte instructions
34. What is addressing and what are the addressing modes available in
8085
¾ Every instruction of a program has to operate on a data. Te method of
specifying the data to be operated by the instruction is called addressing (i.e the
various way of specifying data are called addressing modes)
The 8085 supports five addressing modes and they are,
i. Immediate addressing
ii. Direct addressing
iii. Register addressing
iv. Register indirect addressing
v. Implied addressing.
¾ In register indirect addressing mode, the instruction specifies the name of the
register I which the address of the data is available.. Here the data will be in
memory w and the address will be in a register pair
Example: MOV A, M – The memory data addressed by HL pair is moved ot
A – register.
40. In which unit arithmetic and logical operations are performed and
where the result is stored?
¾ The arithmetic and logical operations are performed in ALU. After the operation
the result will be stored in accumulator.
42. What are the arithmetic instructions that do not effect the flag?
¾ The 16 - bit increment and decrement instructions (IN X rp and DCX rp) will not
affect any flags.
43. What are the flags affected by 8 – bit increment and decrement
instructions?
¾ Except carry, all other flags are affected by 8 – bit increment and decrement
instructions.
3. ANI OOH
4. XRA A
46. Why the program counter and the stack pointer are 16 – Bit
registers?
¾ Program counter (Pc) and stack pointer (Sp) are 16 – bit registers used to hold
memory addresses. The size of these registers is 16 bits, because the memory
addresses are 16 bits.
50.What is flag?
¾ The data conditions, after an arithmetic or logical operation are indicated by
setting or resetting the flip-flops called flags.
Memory Write 0 0 1 WR = 0
I / O Read 1 1 0 RD = 0
I / O Write 1 0 1 WR = 0
Interrupt
Acknowledge 1 1 1 INTR = 0
Halt Z 0 0
Hold Z X X RD, WR = Z and INTA = 1
Reset Z X X
52. How 8085 can be used as an MPU?
¾ 8085 Microprocessor can be used as an MPU but with the following tow
limitations.
1. The low –order address bus of the 8085 multiplexer is multiplexed with
the data bus. Te buses need to be demultiplexed.
2. Appropriate control signals need to be generated to interface memory and
I/O with the 8085.
16 MARKS
1. Draw and explain the operation of 8085 MPU and its architecture.
Address Bus:
• The address bus is a group of 16 lines generally identified as A0 to A15.
• The address bus is unidirectional: bits flow in one direction—from the MPU to
peripheral devices.
• The MPU uses the address bus to perform the first function: identifying a
peripheral or a memory location.
Data Bus:
• The data bus is a group of eight lines used for data flow.
• These lines are bi-directional - data flow in both directions between the MPU and
memory and peripheral devices.
• The MPU uses the data bus to perform the second function : transferring binary
information .
• The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to
FF (28 = 256 numbers).
• The largest number that can appear on the data bus is 11111111.
Control Bus:
• The control bus carries synchronization signals and providing timing signals.
• The MPU generates specific control signals for every operation it performs. These
signals are used to identify a device type with which the MPU wants to
communicate.
Registers of 8085:
• The 8085 have six general-purpose registers to store 8-bit data during program
execution.
• These registers are identified as B, C, D, E, H, and L.
• They can be combined as register pairs—BC, DE, and HL—to perform some 16-
bit operations.
Accumulator (A):
• The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).
• This register is used to store 8-bit data and to perform arithmetic and logical
operations.
• The result of an operation is stored in the accumulator.
Flags:
• The ALU includes five flip-flops that are set or reset according to the result of an
operation.
• The microprocessor uses the flags for testing the data conditions.
• They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC)
flags. The most commonly used flags are Sign, Zero, and Carry.
• The bit position for the flags in flag register is,
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
(2) Zero Flag (z): If the result of arithmetic and logical operation is zero, then zero
flag is set otherwise it is reset.
(3) Auxiliary Carry Flag (AC): If D3 generates any carry when doing
any arithmetic and logical operation, this flag is set. Otherwise it is reset.
(4) Parity Flag (P): If the result of arithmetic and logical operation contains even
number of 1’s then this flag will be set and if it is odd number of 1’s it will be
reset.
(5) Carry Flag (CY): If any arithmetic and logical operation results any
carry then carry flag is set otherwise it is reset.
Temporary Register:
It is used to hold the data during the arithmetic and logical operations.
Instruction Register:
When an instruction is fetched from the memory, it is loaded in the instruction register.
Instruction Decoder:
It gets the instruction from the instruction register and decodes the instruction. It
identifies the instruction to be performed.
• It has three control signals ALE, RD (Active low) and WR (Active low) and
three status signals IO/M(Active low), S0 and S1.
• ALE is used for provide control signal to synchronize the components of
microprocessor and timing for instruction to perform the operation.
• RD (Active low) and WR (Active low) are used to indicate whether the operation
is reading the data from memory or writing the data into memory respectively.
• IO/M(Active low) is used to indicate whether the operation is belongs to the
memory or peripherals.
• If,
IO/M(Active
S1 S2 Data Bus Status(Output)
Low)
0 0 0 Halt
0 0 1 Memory WRITE
0 1 0 Memory READ
1 0 1 IO WRITE
1 1 0 IO READ
0 1 1 Opcode fetch
1 1 1 Interrupt acknowledge
2. Address Bus:
• A8 — A15 (output; 3-state)
• It carries the most significant 8 bits of the memory address or the 8 bits of the I/O
address;
5. Status Signals:
• It is used to know the type of current operation of the microprocessor.
IO/M(Active
S1 S2 Data Bus Status (Output)
Low)
0 0 0 Halt
0 0 1 Memory WRITE
0 1 0 Memory READ
1 0 1 IO WRITE
1 1 0 IO READ
0 1 1 Opcode fetch
1 1 1 Interrupt acknowledge
• 3 output states are high & low states and additionally a high impedance state.
• When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is
0, Q is 1, otherwise Q is 0). However, when E is low the gate is disabled and the
output Q enters into a high impedance state.
E A Q State
1(high) 0 1 High
1 1 0 Low
High
0(low) 0 0
impedance
High
0 1 0
impedance
• For both high and low states, the output Q draws a current from the input of the
OR gate.
• When E is low, Q enters a high impedance state; high impedance means it is
electrically isolated from the OR gate’s input, though it is physically connected.
Therefore, it does not draw any current from the OR gate’s input.
• When 2 or more devices are connected to a common bus, to prevent the devices
from interfering with each other, the tristate gates are used to disconnect all
devices except the one that is communicating at a given instant.
• The CPU controls the data transfer operation between memory and I/O device.
Direct Memory Access operation is used for large volume data transfer between
memory and an I/O device directly.
• The CPU is disabled by tri-stating its buses and the transfer is effected directly by
external control circuits.
• HOLD signal is generated by the DMA controller circuit. On receipt of this
signal, the microprocessor acknowledges the request by sending out HLDA signal
and leaves out the control of the buses. After the HLDA signal the DMA
controller starts the direct transfer of data.
READY (input)
• Memory and I/O devices will have slower response compared to microprocessors.
• Before completing the present job such a slow peripheral may not be able to
handle further data or control signal from CPU.
• The processor sets the READY signal after completing the present job to access
the data.
• The microprocessor enters into WAIT state while the READY pin is disabled.
DECODER:
• It is used to select the memory chip of processor during the execution of a
program.
• No of IC used for decoder is,
¾ 2-4 decoder (74LS139)
¾ 3-8 decoder (74LS138)
Y3(active low)
A
2-4 Y2(active low)
DECODER
74LS139 Y1(active low)
B
Y0(active low)
Consider a system in which the full memory space 64kb is utilized for
EPROM memory. Interface the EPROM with 8085 processor.
• The memory capacity is 64 Kbytes. i.e
n
2 = 64 x 1000 bytes where n = address lines.
So, n = 16.
• In this system the entire 16 address lines of the processor are connected to
address input pins of memory IC in order to address the internal locations
of memory.
• The chip select (CS) pin of EPROM is permanently tied to logic low (i.e.,
tied to ground).
• Since the processor is connected to EPROM, the active low RD pin is
connected to active low output enable pin of EPROM.
• The range of address for EPROM is 0000H to FFFFH.
• The address lines A13, A14 and A]5 are decoded using a 3-to-8 coder to generate
eight chip select signals. These eight chip select signals can be used to select one
of the eight memories at any one time.
Interfacing 4 no. 8Kb EPROM and 4 no. 8Kb RAM with 8085
• The address allocation for Interfacing 4 no. 8Kb EPROM and 4 no. 8Kb RAM
with 8085 is,
For data transfer from input device to processor the following operations are performed.
• The input device will load the data to the port.
• When the port receives a data, it sends message to the processor to read the data.
• The processor will read the data from the port.
• After a data have been read by the processor the input device will load the next
data into the port.
For data transfer from processor to output device the following operations are
performed.
• The processor will load the data to the port.
• The port will send a message to the output device to read the data.
• The output device will read the data from the port.
• After the data have been read by the output device the processor can load the next
data to the port.
The various INTEL 110 port devices are 8212, 8155/8156, 8255, 8355 and 8755.
8212
• The 8212 is a 24 pin IC.
• It consists of eight number of D-type latches.
• It has 8-input lines DI1 to DI8 and 8-output lines DO1 to DO8
• The 8212 can be used as an input or output device
• It has two selecting device DS1 (low) and DS2.
• If,
8155:
• It has two numbers of 8-bit parallel I/O port (port-A and B)
• One number of 6-bit parallel I/O port (port-C).
• It has 14 bit timer (operating in 4 modes).
• It has six internal addresses.
• It has one chip select pin CS (low).
Internal address of 8155
8156:
• It has two numbers of 8-bit parallel I/O port (port-A and B)
• One number of 6-bit parallel 1 port (port-C).
• It has 14 bit timer (operating in 4 modes).
• It has six internal addresses.
• It has one chip select pin CS (low).
Internal address of 8156
8255:
• It has 3 numbers of 8-bit parallel I/O ports (port A, B and C).
• Port-A can be programmed in mode-0 mode-1 or mode-2 as input or output port.
• Port-B can be programmed in mode-1 and mode-2 as 1/Oport.
• When ports A and B are in mode-0, the port-C can be used as I/O port.
• One logic low chip select (CS) pin.
• It requires four internal addresses
Internal address of 8255
8355:
• It has 2KB ROM.
• It has two number of 8 bit port (A,B).
• It has one CS(low).
• It has four internal addresses.
8755:
• It has 2Kb EPROM.
• It has two number of 8 bit port (A,B).
• It has one CS(low).
• It has four internal addresses.
The IC 2764 is selected for EPROM memory and the IC 6264 is selected for
RAM memory.
Both the memory lC have time compatibility with 8085 processor.
The 8kb EPROM, 2764 require 13 address tines. The 8kb RAM, 6264 require 13
address lines.
The address lines A0 to A12 are connected to both EPROM and RAM memory
ICs.
The 16 bit address for the memory and 8255 devices are,
A system requires 16kb EPROM and 16kb RAM. Also the system has 2
numbers of 8255, one number of 8279, one number of 8251 and one number of 8254.
(8255 - Programmable peripheral interface; 8279-Keyboard/display controller, 8251
– USART and 8254 - Timer). Draw the Interface diagram. Allocate addresses to all
the devices. The peripheral IC should be I/O mapped.
• The I/O devices in the system should be mapped by standard I/O mapping. Hence
separate decoders can be used to generate chip select signals for memory IC and
peripheral IC’s.
• For 16kb EPROM, we can provide 2 numbers of 2764(8k x 8) EPROM.
• For 16kb RAM we can provide 2 numbers of 6264 (8k x 8) RAM.
• The 8kb memories require 13 address lines. Hence the address lines A0 – A12 are
used for selecting the memory locations.
• The unused address lines A13, A14 and A15 are used as input to decoder 74LS138 (3-
to-8-deeoder) of memory IC. The logic low enables of this decoder are tied to IO/ M(low)
of 8085, so that this decoder is enabled for memory read/write operation. The other
enable pins of decoder are tied to appropriate logic levels permanently. The 4-outputs of
the decoder are used to select memory lCs and the remaining 4 are kept for future
expansion.
• The EPROM is mapped in the beginning of memory space from 0000H to 3FFF.
• The RAM is mapped at the end of memory space from C000 to FFFFH.
• There are five peripheral IC’s to be interfaced to the system. The chip-select signals
for these IC’s are given through another 3-to-8 decoder 74LS138 (I/O decoder). The
input to this decoder is A11, A12 and A13
• The address lines A13, A14 and A15 are logically ORed and applied to low enable of I/O
decoder.
• The logic high enable of I/O decoder is tied to IO / M(low) signal of 8085, so that this
decoder is enabled for I/O read/write operation.
A system requires 8kb EPROM and 8kb RAM. Also the system has 2
numbers of 8155. Draw the Interface diagram. Allocate addresses to all the devices.
The peripheral IC should be I/O mapped.
• The IC 2764 (8k x 8) is selected for EPROM memory and IC 6264 (8k x 8) is
selected for RAM memory. Both the memory IC has time compatibility with 8085
processor.
• The 8kb memory requires 13 address lines. Hence the address lines A0 – A12 are
used to select memory locations.
• The RAM locations of 8155 are selected by address lines A0 to A7.
• 3-to-8 decoder, 74LS138 is used for generating chip select signals by decoding
the address lines A13, A14 and A15.
• Eight bit addresses are allotted to ports of 8l55 and sixteen bit addresses are
allotted to RAM memory locations of 8155.
Instruction Cycle:
The time required to execute an instruction is called instruction cycle.
Machine Cycle:
The time required to access the memory or input/output devices is called machine
cycle.
T-State:
• The machine cycle and instruction cycle takes multiple clock periods.
• A portion of an operation carried out in one system clock period is called as T-
state.
The 8085 microprocessor has 5 (seven) basic machine cycles. They are
• Each instruction of the 8085 processor consists of one to five machine cycles, i.e.,
when the 8085 processor executes an instruction, it will execute some of the
machine cycles in a specific order.
• The processor takes a definite time to execute the machine cycles. The time taken
by the processor to execute a machine cycle is expressed in T-states.
• One T-state is equal to the time period of the internal clock signal of the
processor.
• The T-state starts at the falling edge of a clock.
¾ The memory read machine cycle is executed by the processor to read a data
byte from memory.
¾ The processor takes 3T states to execute this cycle.
¾ The instructions which have more than one byte word size will use the
machine cycle after the opcode fetch machine cycle.
¾ The I/O Read cycle is executed by the processor to read a data byte from I/O port
or from the peripheral, which is I/O, mapped in the system.
¾ The processor takes 3T states to execute this machine cycle.
¾ The IN instruction uses this machine cycle during the execution.
¾ The I/O write machine cycle is executed by the processor to write a data byte in
the I/O port or to a peripheral, which is I/O, mapped in the system.
¾ The processor takes, 3T states to execute this machine cycle.
¾ Assume the memory address for the instruction and let the content of
accumulator is C7H.
4200 6AH
4201 52H
4126 C0H
2001 43H
Types of Interrupts:
It supports two types of interrupts.
1. Hardware
2. Software
Software interrupts:
• The software interrupts are program instructions. These instructions are inserted
at desired locations in a program.
• The 8085 has eight software interrupts from RST 0 to RST 7. The vector address
for these interrupts can be calculated as follows.
Interrupt number * 8 = vector address
For RST 5, 5 * 8 = 40 = 28H
Vector address for interrupt RST 5 is 0028H
The Table shows the vector addresses of all interrupts.
Hardware interrupts:
• An external device initiates the hardware interrupts and placing an appropriate
signal at the interrupt pin of the processor.
• If the interrupt is accepted then the processor executes an interrupt service
routine.
• The 80S5 has five hardware interrupts
(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR
TRAP :
• This interrupt is a non-maskable interrupt. It is unaffected by any mask or
interrupt enable.
• TRAP bas the highest priority and vectored interrupt.
• TRAP interrupt is edge and level triggered. This means hat the TRAP must go
high and remain high until it is acknowledged.
• In sudden power failure, it executes a ISR and send the data from main memory to
backup memory.
• The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor
receives HOLD and TRAP at the same time then HOLD is recognized first and
then TRAP is recognized).
• There are two ways to clear TRAP interrupt.
2) By resetting microprocessor (External signal)
3) By giving a high TRAP ACKNOWLEDGE (Internal signal)
RST 7.5:
• The RST 7.5 interrupt is a maskable interrupt.
• It has the second highest priority.
• It is edge sensitive. ie. Input goes to high and no need to maintain high state until
it recognized.
• Maskable interrupt. It is disabled by,
DI instruction
System or processor reset.
After reorganization of interrupt.
• Enabled by EI instruction.
INTR:
• INTR is a maskable interrupt. It is disabled by,
DI, SIM instruction
System or processor reset.
After reorganization of interrupt.
• Enabled by EI instruction.
• Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply
the address of ISR.
• It has lowest priority.
• It is a level sensitive interrupts. ie. Input goes to high and it is necessary to
maintain high state until it recognized.
• The following sequence of events occurs when INTR signal goes high.
I) The 8085 checks the status of INTR signal during execution of each instruction.
2) If INTR signal is high, then 8085 completes its current instruction and sends
active low interrupt acknowledge signal, if the interrupt is enabled.
3) In response to the acknowledge signal, external logic places an instruction
OPCODE on the data bus. In the case of multibyte instruction, additional interrupt
acknowledge machine cycles are generated by the 8085 to transfer the additional bytes
into the microprocessor.
4) On receiving the instruction, the 8085 save the address of next instruction on
stack and execute received instruction.
• The status of pending interrupts can be read from accumulator after executing
RIM instruction.
• When RIM instruction is executed an 8-bit data is loaded in accumulator, which
can be interpreted as shown in fig.
Vector
Interrupt type Trigger Priority Maskable
address
st
TRAP Edge and Level 1 No 0024H
RST 7.5 Edge 2nd Yes 003CH
RST 6.5 Level 3rd Yes 0034H
RST 5.5 Level 4th Yes 002CH
th
INTR Level 5 Yes -