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Page 64
UNIT 4
ANALOG CIRCUITS
2013
4.1
ONE MARK
(B) 0.7 V
(D) 15 V
4.5
4.3
(A) 8
(B) 32
(C) 50
(D) 200
In the circuit shown below the op-amps are ideal. Then, Vout in Volts
is
(A) 4
(C) 8
2013
TWO MARKS
In the circuit shown below, the knee current of the ideal Zener
dioide is 10 mA. To maintain 5 V across RL , the minimum value of
RL in 8 and the minimum power rating of the Zener diode in mW
, respectively, are
(B) 6
(D) 10
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 65
(B) XY
(D) XY
4.11
The diodes and capacitors in the circuit shown are ideal. The voltage
v (t) across the diode D1 is
(A) sin Xt
(C) ^sin Xt sin Xt h /2
4.8
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(A) 20
(B) 30
(C) 40
(D) 50
2012
4.9
(B) 9.3 mA
(D) 6.2 mA
(A) 50 8
(C) 5 k8
(B) 100 8
(D) 10.1 k8
2012
ONE MARK
4.13
1
rad/s
(R1 R2) C
(B) high pass filter with f3dB 1 rad/s
R1 C
(C) low pass filter with f3dB 1 rad/s
R1 C
1
(D) high pass filter with f3dB
rad/s
(R1 R2) C
(A) low pass filter with f3dB
(A) 250 8
(C) 25 8
4.10
(B) 27.5 8
(D) 22.5 8
4.14
TWO MARKS
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 66
(A) Av . 200
(C) Av . 20
(B) Av . 100
(D) Av . 10
(A) 1 V
(C) 3 V
4.18
2011
4.15
ONE MARK
In the circuit shown below, capacitors C1 and C2 are very large and
are shorts at the input frequency. vi is a small signal input. The gain
magnitude vo at 10 M rad/s is
vi
(B) 2 V
(D) 3.67 V
(B) 25 ms
(D) 100 ms
For a BJT, the common base current gain B 0.98 and the collector
base junction reverse bias saturation current ICO 0.6 NA . This
BJT is connected in the common emitter mode and operated in the
active region with a base drive current IB 20 NA . The collector
current IC for this mode of operation is
(A) 0.98 mA
(B) 0.99 mA
(C) 1.0 mA
(D) 1.01 mA
(B) minimum
(D) zero
In the circuit shown below, for the MOS transistors, Nn Cox 100 NA/V 2
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
4.20
4.21
2010
(C) 1.5 mA
(D) 2 mA
Consider the common emitter amplifier shown below with the following circuit parameters:
C 100, gm 0.3861 A/V, r0 259 8, RS 1 k8, RB 93 k8,
RC 250 k8, RL 1 k8, C1 3 and C2 4.7 NF
2010
4.22
Page 67
TWO MARKS
ONE MARK
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4.25
4.26
In the silicon BJT circuit shown below, assume that the emitter
area of transistor Q1 is half that of transistor Q2
(A) R2
R1
R2 || R 3
(C)
R1
(B) R 3
R1
(D) b R2 R 3 l
R1
4.27
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
2009
4.28
TWO MARKS
Page 68
4.30
For small increase in VG beyond 1V, which of the following gives the
correct description of the region of operation of each MOSFET
(A) Both the MOSFETs are in saturation region
(B) Both the MOSFETs are in triode region
(C) n-MOSFETs is in triode and p MOSFET is in saturation
region
(D) n- MOSFET is in saturation and p MOSFET is in triode
region
4.31
4.32
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 69
4.37
(A) 0 V
(B) 0.1 V
(C) 0.7 V
(D) 1.1 V
ONE MARK
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4.38
TWO MARSK
4.39
4.36
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 70
4.40
(B) 2 mA
(D) 10 mA
4.43
(A) cut-off
(B) saturation
ONE MARK
4.47
4.44
For the BJT circuit shown, assume that the C of the transistor is
very large and VBE 0.7 V. The mode of operation of the BJT is
4.42
4.46
(B) -1 V
(D) 0.5 V
TWO MARKS
(A) 0 A
(C) 45 NA
4.48
(B) 25 NA
(D) 90 NA
For the Zener diode shown in the figure, the Zener voltage at knee is
7 V, the knee current is negligible and the Zener dynamic resistance
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 71
(A) 0 Volt
(D) 10 Volts
For the circuit shown below, assume that the zener diode is ideal
with a breakdown voltage of 6 volts. The waveform observed across
R is
4.49
4.50
4.52
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ONE MARK
The input impedance (Zi) and the output impedance (Z0) of an ideal
trans-conductance (voltage controlled current source) amplifier are
(B) Zi 0, Z0 3
(A) Zi 0, Z0 0
(C) Zi 3, Z0 0
(D) Zi 3, Z0 3
An n-channel depletion MOSFET has following two points on its
ID VGs curve:
(i) VGS 0 at ID 12 mA and
(ii) VGS 6 Volts at ID 0 mA
Which of the following Q point will given the highest trans conductance gain for small signals?
(B) VGS 3 Volts
(A) VGS 6 Volts
(C) VGS 0 Volts
(D) VGS 3 Volts
2006
4.53
If Vi V1 sin (Xt) and V0 V2 sin (Xt G), then the minimum and
maximum values of G (in radians) are respectively
(B) 0 and Q
(A) Q and Q
2
2
2
(C) Q and 0
(D) Q and 0
2
2006
4.51
TWO MARKS
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
4.55
4.56
Page 72
4.61
(C) 40 k8
(D) infinite
(D) decrease the input resistance and increase the output resistance
4.62
(B) 10 k8
4.57
(A) 30 k8
4
2005
4.63
(B) -5.3
(D) 10
4.64
A regulated power supply, shown in figure below, has an unregulated input (UR) of 15 Volts and generates a regulated output Vout .
Use the component values shown in the figure.
(A) 30 mA
(C) 49 mA
4.65
4.58
4.59
(B) 39 mA
(D) 20 mA
4.60
TWO MARKS
ONE MARK
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 73
The Op-amp circuit shown in the figure is filter. The type of filter
and its cut. Off frequency are respectively
4.70
4.71
The Zener diode in the regulator circuit shown in the figure has a
Zener voltage of 5.8 volts and a zener knee current of 0.5 mA. The
maximum load current drawn from this current ensuring proper
functioning over the input voltage range between 20 and 30 volts, is
(A) 23.7 mA
(C) 13.7 mA
4.69
(B) 14.2 mA
(D) 24.2 mA
(A) 1 V
(C) 3 V
(B) 2 V
(D) 4 V
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4.72
4.73
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
2004
4.74
Page 74
ONE MARK
4.75
(A) 1 NF
2Q
1
NF
(C)
2Q 6
4.79
2004
4.77
4.78
4.81
TWO MARKS
(D) 2Q 6 NF
(A) Vs
R2
(C) Vs
RL
4.80
(B) 2Q NF
(B) Vs
R2
(D) Vs
R1
In the voltage regulator shown in the figure, the load current can
vary from 100 mA to 500 mA. Assuming that the Zener diode is ideal
(i.e., the Zener knee current is negligibly small and Zener resistance
is zero in the breakdown region), the value of R is
(A) 7 8
(B) 70 8
70
(D) 14 8
(C)
8
3
In a full-wave rectifier using two ideal diodes, Vdc and Vm are the dc
and peak values of the voltage respectively across a resistive load. If
PIV is the peak inverse voltage of the diode, then the appropriate
4.82
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 75
2003
4.83
4.84
ONE MARK
(A) (2 V, 2 mA)
(B) (3 V, 2 mA)
(C) (4 V, 2 mA)
(D) (4 V, 1 mA)
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4.90
4.86
4.87
(B) 1/3
(D) 1/2
4.91
If the differential voltage gain and the common mode voltage gain
of a differential amplifier are 48 dB and 2 dB respectively, then
common mode rejection ratio is
(A) 23 dB
(B) 25 dB
(C) 46 dB
(D) 50 dB
Generally, the gain of a transistor amplifier falls at high frequencies
due to the
(A) internal capacitances of the device
(B) coupling capacitor at the input
(C) skin effect
(D) coupling capacitor at the output
2003
TWO MARKS
(B)
1
(2QRC)
(D)
6
(2QRC)
(A) 3 V
(C) 9 V
4.92
4.88
(D) 11 k8
(B) 6 V
(D) 12 V
If the op-amp in the figure is ideal, the output voltage Vout will be
equal to
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
(A) 1 V
(C) 14 V
4.93
(B) 6 V
(D) 17 V
Three identical amplifiers with each one having a voltage gain of 50,
input resistance of 1 k8 and output resistance of 250 8 are cascaded.
The opened circuit voltages gain of the combined amplifier is
(A) 49 dB
(B) 51 dB
(C) 98 dB
4.94
Page 76
(D) 102 dB
2002
4.98
In a negative feedback amplifier using voltage-series (i.e. voltagesampling, series mixing) feedback.
(A) Ri decreases and R0 decreases
(B) Ri decreases and R0 increases
(C) Ri increases and R0 decreases
(D) Ri increases and R0 increases
(Ri and R0 denote the input and output resistance respectively)
4.96
4.97
(A) R2 5R1
(C) R2 R1
6
ONE MARK
4.99
A 741-type opamp has a gain-bandwidth product of 1 MHz. A noninverting amplifier suing this opamp and having a voltage gain of 20
dB will exhibit a -3 dB bandwidth of
(A) 50 kHz
(B) 100 kHz
1000
kHz
(D) 1000 kHz
(C)
7.07
17
Three identical RC-coupled transistor amplifiers are cascaded. If
each of the amplifiers has a frequency response as shown in the
figure, the overall frequency response is as given in
(B) R2 6R1
(D) R2 R1
5
4.100
TWO MARKS
(D) 39.5 mV
(A) R # 18008
(C) 37008 # R # 40008
4.101
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 77
(A) +16
(B) -16
(C) +8
(D) -6
2001
4.102
(C) gm rQ
4.103
4.104
gm
r
gm
(D)
rQ
(B)
4.108
4.106
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of 100.
TWO MARKS
4.105
ONE MARK
14
4.109
(C) 10 - 4
2000
4.110
(B) 9
(D) 11
cos (100U) dU
(B) 10
cos (100U) dU
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
(A) zero
(C) indeterminate
4.111
4.113
4.114
(B) infinite
(D) Vin1 Vin2
2VT
(A) -1 V
(B) 2 V
(C) +1 V
(D) +15 V
4.112
Page 78
4.118
TWO MARKS
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 79
4.125
4.126
4.122
4.123
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4.127
4.128
In the cascade amplifier shown in the given figure, if the commonemitter stage (Q1) has a transconductance gm1 , and the common
base stage (Q2) has a transconductance gm2 , then the overall
transconductance g ( i 0 /vi) of the cascade amplifier is
(B) gm2
g
(D) m2
2
4.129
4.130
4.124
ONE MARK
(A) gm1
g
(C) m1
2
(B) 5 mV
(D) +50 V or -50 V
1999
4.121
(A) 0 V
(C) + 15 V or -15 V
4.120
ONE MARK
TWO MARK
4.131
TWO MARKS
(D) B
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
4.132
4.133
4.134
Page 80
(A) decrease the voltage gain and decrease the input impedance
(B) increase the voltage gain and decrease the input impedance
(D) increase the voltage gain and increase the input impedance
(C) decrease the voltage gain and increase the input impedance
4.138
Of these,
(A) only (1) and (2) are true
(B) only (1) and (3) are true
4.136
1997
(A) V1 V2
2
(B) V1 V2
2
(C) V1 2V2
(D) V1 2V2
4.140
4.141
ONE MARK
TWO MARKS
(A) 0 A
(C) 1 A
4.137
(B) 4 A
(D) None of the above
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
(A) 4 V
(C) 5 V
4.142
Page 81
(B) 6 V
(D) 5.5 V
with a forward resistance Rf . The
resistance is RL . The DC current
Vm
Q (R f RL)
(D) Vm
RL
(B)
(A) gm1
(C) gm2
4.147
1996
4.143
In the circuit of the given figure, assume that the diodes are ideal
and the meter is an average indicating ammeter. The ammeter will
read
(A) 0.4 2 A
(C) 0.8 A
Q
4.144
ONE MARK
(B) 0.4 A
(D) 0.4 mamp
Q
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1996
4.145
TWO MARKS
(A) Z b1 1 l
k
(C) Z
(k 1)
4.146
(B) Z (1 k)
(D) Z
(1 k)
A zener diode in the circuit shown in the figure is has a knee current
of 5 mA, and a maximum allowed power dissipation of 300 mW
. What are the minimum and maximum load currents that can
be drawn safely from the circuit, keeping the output voltage V0
constant at 6 V?
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 82
***********
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 83
SOLUTIONS
4.1
(1)
Since, voltage across zener diode is 5 V so, current through 100 8
resistor is obtained as
Is 10 5 0.05 A
100
Therefore, the load current is given by
IL 5
RL
Since, for proper operation, we must
have
IZ $ Iknes
So, from Eq. (1), we write
0.05 A 5 $ 10 mA
RL
50 mA 5 $ 10 mA
RL
40 mA $ 5
RL
3
40 # 10 $ 5
RL
i.e.,
This current will flow completely through the BJT since, no current will flow into the ideal op-amp ( I/P resistance of ideal opamp is infinity). So, for BJT we have
VC 0
VB 0
IC 5 mA
i.e.,the base collector junction is reverse biased (zero voltage)
therefore, the collector current (IC ) can have a value only if baseemitter is forward biased. Hence,
VBE 0.7 volts
&
VB VE 0.7
&
0 Vout 0.7
or,
Vout 0.7 volt
4.2
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1
# RL
5
40 # 103
5
#
R
L
40 # 103
or,
125 8 # RL
Therefore, minimum value of RL 125 8
Now, we know that power rating of Zener diode is given by
PR VZ IZ^maxh
IZ^maxh is maximum current through zener diode in reverse bias.
Maximum currrent through zener diode flows when load current is
zero. i.e.,
IZ^maxh Is 10 5 0.05
100
Therefore,
PR 5 # 0.05 W
250 mW
V1 k A 0 V1
^Vout A 0 V1h
V1 ^1 k A 0h
Therefore, if k is increased then input voltage is also increased so,
the input impedance increases. Now, we have
Vout A 0 V1
Vin
A0
^1 k A 0h
A 0 Vin
^1 k A 0h
Since, Vin is independent of k when seen from output mode, the
output voltage decreases with increase in k that leads to the decrease
of output impedance. Thus, input impedance increases and output
impedance decreases.
4.3
4.4
Is IZ I L
IZ Is I L
V1
gm Vi
1
1
RD R 1
L
sC
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
V0 V1 RL
RL 1
sC
RL
RL 1
sC
4.6
gm Vi
J
K 1
1
K RD
K
RL 1
sC
L
Page 84
N
O
O
O
P
4.7
VWX 0
VWX 0 for all t
VTh VCC
R2
R1 R 2
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 85
3R2
R1 R 2
and
RTh R2 R1
R 2 R1
Since, IC CIB has C . 3 (very high) so, IB is negative in
comparison to IC . Therefore, we can write the base voltage
VB VTh
So,
VTh 0.7 IC RE 0
or,
or,
or,
or,
Hence,
4.9
4.10
R2 60 # 1.2 40 k8
1. 8
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10 i # 1k v 0
v
0.7 (1000) v 0
10 :
500 D
ZTh Vtest
Itest
10 (v 0.7) # 2 v 0
10 3v 1.4 0
So,
4.11
(Assumption is true)
But
Ib Vtest Vtest
9k 1k
10k
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 86
IC - IE 13.7 VC (C 1) IB
12k
13.7 VC 100I
...(ii)
B
12 # 103
Solving equation (i) and (ii),
IB 0.01 mA
Small Signal Analysis :
Transforming given input voltage source into equivalent current
source.
0 Vi (jX) 0 Vo (jX)
0
1 R
R2
1
jXC
Vo (jX)
Vi (jX)
1 R
R2
1
jXC
Vi (jX) R2
R1 j 1
XC
1 " 3, so V 0
o
XC
Vo (jX)
At X " 0 (Low frequencies),
6H (3)@
v 0 428.72VQ
...(i)
Writing KCL at input node
vi v Q v Q v Q vo
Rs
Rs rQ
RF
vi v 1 1 1 v 0
Q:
Rs
Rs rQ RF D RF
vi v (5.1 104) v 0
#
Q
Rs
RF
Substituting VQ from equation (i)
H ^ jX0h 1 H (3)
2
R2
1 b R2 l
2 R1
R 12 21 2
X0 C
So,
vi 5.1 # 104 v v 0
0
428.72
Rs
RF
2R R 21 2
X0 C
1
2
R1 2 2
X C
X0 1
R1 C
2
1
4.14
2
1
vi
1.16 # 106 v 0 1 # 105 v 0
10 # 103
Rs 10 k8
(source resistance)
vi
1.116 # 105
10 # 103
1
- 8.96
Av v 0
vi
10 # 103 # 1.116 # 105
4.15
...(i)
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 87
4.16
Since
or
Transfer function
or
H (s) Vo sR1 L1
I1 R1 sL1
jXR1 L1
H (jX)
R1 jXL1
At X 0
At X 3
4.17
H (jX) 0
H (jX) R1 constant .
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Hence HPF.
with time, the capacitor charges and voltage across collector changes
from 0 towards negative.
When saturation starts,
VCE 0.7 & VC 5 V (across
capacitor)
Thus from (1) we get,
5 0.5 mA T
5 NA
For transistor M2 ,
VGS VG VS Vx 0 Vx
VDS VD VS Vx 0 Vx
Since VGS VT Vx 1 VDS , thus M2 is in saturation.
By assuming M1 to be in saturation we have
IDS (M ) IDS (M )
Nn C 0x
N C
(4) (5 Vx 1) 2 n 0x 1 (Vx 1) 2
2
2
1
or
Taking positive root,
or
4.20
4 (4 Vx ) 2 (Vx 1) 2
2 (4 Vx ) ! (Vx 1)
4.21
8 2Vx Vx 1
Vx 3 V
At Vx 3 V for M1,VGS 5 3 2 V VDS . Thus our assumption
is true and Vx 3 V .
4.18
...(1)
B 0.98
C B 4.9
1B
6
T 5 # 5 # 10
50 m sec
0.5 # 103
4.22
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 88
4.24
Ri RB || r Q
Voltage gain
AV gm RC
Now, if CE is disconnected, resistance RE appears in the circuit
Input impedance
So,
or
4.25
Input impedance
4.23
R in RB || [rQ (C 1)] RE
AV
Voltage gain
0 Vi 0 Vo 0
R1
R2
Vo R2
R1
Vi
gm RC
1 gm R E
fo
VB 10 ( 0.7) 9.3 V
Collector current
I1
0 ( 9.3)
1 mA
(9.3 k8)
C 1 700 (high), So IC . IE
Applying KCL at base we have
1 IE IB IB
1 (C 1 1) IB IB IB
1
1 (700 1 1)
IB
IB
2
IB . 2
702
2
I 0 IC C 2 : IB 715 # 2 . 2 mA
702
2
1
2Q (RC RL) C2
fo
1
271 Hz
2 # 3.14 # 1250 # 4.7 # 106
Lower cut-off frequency
f
fL . o 271 27.1 Hz
10
10
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 89
I 20 0 Vi 0 5 Vi
4R
R
R
If I 0, diode D2 conducts
So, for 5 VI 0 & VI 5, D2 conducts
2
Equivalent circuit is shown below
IC 10 5 1 mA
5k
Thus
Current
IE IC
VE IE RE 1m # 1.4k 1.4V
0. 6 1 . 4 2 V
Thus the feedback is negative and output voltage is V 2V .
4.33
hfe RC
Vi
hie
Thus
Output is Vo 0 . If I 0 , diode D2 will be off
5 VI 0 & V 5, D is off
I
2
R
The circuit is shown below
0 Vi 0 20 0 Vo 0
R
4R
R
4.28
4.29
4.30
4.31
4.32
or
Vo Vi 5
At Vi 5 V,
At Vi 10 V,
Vo 0
Vo 5 V
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For the positive half of Vi , the diode D1 is forward bias, D2 is reverse
bias and the zener diode is in breakdown state because Vi 6.8 .
Thus output voltage is
V0 0.7 6.8 7.5 V
For the negative half of Vi, D2 is forward bias thus
Then
V0 0.7 V
4.35
^ L h2
Ibias
W
^ L h1
W
Ix
Hence
4.36
Ix Ibias
Thus current will flow from -ive terminal (0 Volt) to -1 Volt source.
Thus the current I is
0 ( 1)
I
1
100k
100k
The voltage at non inverting terminal is 5 V because OP AMP is
ideal and inverting terminal is at 5 V.
I I 0 _eV 1i
V
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 90
Now VT 25 mV and I0 1 NA
Thus
or
Now
V
4.37
V
I 106 8e 25 # 10 1B 1 5
10
V 0.06 V
V0 I # 4k V 1 # 4k 0.06 0.1
100k
3
gm
Vo gm VQ # (3k 3k )
1 Vin (1.5k)
25
v
R2
sR2 C2 + 1
v0
R2
vi
(R1 sL)( sR2 C2 1)
or
4.42
and from this equation it may be easily seen that this is the standard form of T.F. of low pass filter
K
H (s)
(R1 sL)( sR2 C2 1)
and form this equation it may be easily seen that this is the standard form of T.F. of low pass filter
H (s) 2 K
as bs b
4.38
4.39
4.43
Option ( ) is correct.
The current in both transistor are equal. Thus gm is decide by M1.
Hence (C) is correct option.
Option (C) is correct.
Let the voltage at non inverting terminal be V1, then after applying
KCL at non inverting terminal side we have
15 V1 V0 V1 V1 ( 15)
10
10
10
V
0
or
V1
3
IC
1m 1 A/V
VT
25m
25
VQ Vin
60Vin
Am Vo 60
Vin
IC . IE
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
v+ vv - 0. 5 V
i 1 0.5 0.5 mA
1k
v0 0.5 mA
0
.
5
i
2k
We know that
Thus
Now
and
v0 0.5 1 0.5 V
or
4.45
Page 91
V+
Now
10 10IC VCE IC 0
VCE 4.3 V
VBC VBE VCE
Since VBC
4.46
0.7 ( 4.3) 5 V
0.7 V, thus transistor in saturation.
or
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V0 1 sRC
Vi
1 sRC
4.50
VD = 0 Vo1 = VT 1n 2
Is R
For the first condition
VD = 0 Vo1 = VT 1n 4
Is R
4.47
Vo1 Vo2 = VT 1n 4 VT 1n 2
Is R
Is R
4
Vo1 Vo2 = VT 1n = VT 1n2
2
Minimum value,
Maximum value,
4.51
4.52
4.53
From figure it may be easily seen that Vas for each NMOS and
PMOS is 2.5 V
NA
Thus
ID K (Vas VT ) 2 40 2 (2.5 1) 2 90 N A
V
4.48
1
V
1 sCR i
or
1
V
1 sCR i
Vi I eV /V
s
R
VD = VT 1n Vi
Is R
D
Vi
IR ID
or
1
sC
R sC1
V- V+
Now
Gmin
Gmax
2 tan - 2 XRC
= Q (at X 3)
= 0( at X = 0)
4.54
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 92
Now
VCE 15 9 6 V
The power dissipated in transistor is
4.60
...(1)
4.61
where
Ri
Rif
...(2)
4.62
...(3)
...(4)
4.63
Rof R0 (1 AC)
Input resistance without feedback
Input resistance with feedback.
C' 110 # 60 66
100
4.58
4.57
ADM gm RC
Thus only common mode gain depends on RE and for large value
of RE it decreases.
4.64
10
4.65
- 13
0.7
c e1 # 26 # 10
-3
1m 49 mA
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 93
or
4.69
4.70
...(1)
or
...(2)
or
V+ = I+ (1M)
Since for ideal OPAMP V+ V- , from (1) and (2) we have
4.71
e0 I (1M) I (1M)
(I I) (1M) = IOS (1M)
Thus if e0 has been measured, we can calculate input offset current
IOS only.
4.66
4.67
Z0 rd RD 20k 2k 20 k8
11
and
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Since the FET has high input resistance, gate current can be neglect
and we get VGS 2 V
Since VP VGS 0 , FET is operating in active region
2
( 2) 2
Now
ID IDSS c1 VGS m 10 c1
( 8) m
VP
5.625 mA
Now
4.72
IC CIB 50 # 40N 2 mA
VC VCC RC IC = 20 2m # 2k = 16 V
8.75 V
So,
4.73
VP
2
ID IDSS
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 94
or
2V+ Vo IL R2 0
Since V- V+ , from (1) and (2) we have
Vu 2k Vsat 2 ( 10) 5 V
2.5k
4
4.74
4.75
Vs IL R2 0
4.77
IL Vs
R2
or
4.80
Rif Ri (1 AC)
Ro
Rof
(1 AC)
4.76
...(2)
R 708
12
5
At IL 500 mA
500 mA
R
VZ 5 V
or
VZ 5 V
R 14 8
Thus taking minimum we get
or
R 14 8
4.81
4.82
IC
1mA 0.04 40 mA/V
VT
25mV
C
rQ
100 - 3 2.5 k8
gm
40 # 10
gm
4.78
4.79
VT
R1 V 1
#5 1 V
R1 R2 C
41
Now
CE
Ai
V- V+
Applying KCL at inverting terminal
V- Vs V- V0 0
R1
R1
Av
or
2V- Vo Vs
Applying KCL at non-inverting terminal
V+
V Vo
IL +
0
R2
R2
...(1)
4.84
4.85
CC
CB
High
High
Unity
High
Unity
High
Ri
Medium
High
Low
Ro
Medium
Low
High
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 95
or
Vi 4 sin Xt
The output of comparator will be high when input is higher than
Vref 2 V and will be low when input is lower than Vref 2 V.
Thus the waveform for input is shown below
4.91
Thus
4.86
R2 2k8
IB1 IC1 1.5m 0.01 mA
150
C1
will we equal to IB1 as there is no in R1.
IC2 C2 IB2 200 # 0.01 2 mA
or
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4.92
or
4.87
8 (3) = 8 k8
18
3
8
V+ V- V
3
gm
gb jXC
V+ =
4.89
4.93
1k
50V1 40V1
1k 0.25k
1k
V3
50V2 40V2
1k 0.25k
V2
In first case
or
Vo 6V- 10
6 # 8 10 6 V
3
or
Similarly
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
or
or
or
4.94
Page 96
V3 40 # 40V1
Vo 50V3 50 # 40 # 40V1
AV Vo 50 # 40 # 40 8000
V1
or
or
Now
Slew Rate
or
4.100
I
For satisfactory operations
Vin V0
R
When Vin 30 V,
30 10
R
20
or
R
Ln
2n 1
or
Thus R # 18188
$ 11 mA
R # 36368
2 2 1 0.5 kHz
$ (10 + 1) mA
40 $ 11 # 10 - 3
R
4.101
fHn fH
[IZ IL I]
23 1
IZ + IL
50 10 $ (10 1) mA
R
IZ IL
R # 1818 8
or
when Vin 50 V
6
6
BW 10 10 105 Hz 100 kHz
Gain
10
4.98
20 log x 20
or
x 10
Since Gain band width product is 106 Hz, thus
So, bandwidth is
4.97
dVO
AV Vm X AV Vm 2Qf
c dt m
max
Vm SR
AV V2Qf
1
10 - 6 # 100 # 2Q # 20 # 103
or
VM 79.5 mV
Rif Ri (1 AC)
Ro
Rof
(1 AC)
4.96
VO VV Vi Vm sin Xt
dVO A V X cos Xt
V m
dt
-3
3
4.95
20 # 10
1
idt
6
2 # 10 0
i (2 # 10 - 3 0) 6 # 10 - 6
i 3 mA
R2 5R1
or
4.99
Thus
VO (f)
1 R2
Vf (f)
R1
Vf (f)
1
C (f) +0
6
VO (f)
A
Now
and
Thus
IDSS
VG
VS
VGS
10 mA and VP 5 V
0
ID RS 1 # 2.58 2.5 V
VG VS 0 2.5 2.5 V
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
gm 2IDSS 81 ` 2.5 jB 2 mS
VP
5
V
0
gm RD
AV
Vi
Now
9
1 # 10 50.3 MHz
2Q 10
hfe gm rQ
4.103
1
2Q LCeq
Ceq C1 C2 2 # 2 1 pF
C1 C2
4
1
f
-6
2Q 10 # 10 # 10 - 12
f
2ms # 3k 6
So,
4.102
Page 97
4.104
4.105
4.106
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Vo AOL VNow applying KCL at inverting terminal we have
V- Vs V- V0 0
R1
R2
4.109
or
I IC IZ CIB IZ
CIZ IZ (C 1) IZ
IZ I 1 0.01 A
C 1 99 1
...(1)
...(2)
Since IC CIB
since IB IZ
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
or
4.110
Page 98
4.111
4.112
R1 V 5
# 15 5 V
R1 R2 C
10 5
Since C is large is large, IC . IE , IB . 0 and
IE VT VBE
RE
4.3
5 0.7
10 mA
0.430K8
0.430k8
VT
4.119
So,
4.120
4.121
4.122
gm
'
jX (C)
gbc
1
Ai \
Capacitance
1
Ai B
frequency
Ai
or,
and
4.115
4.116
4.117
4.118
by applying KCL at E2
gm1 VQ
1
VQ
gm2 VQ
rQ
2
at C2
from eq (1) and (2)
i 0 gm2 VQ
gm1 VQ
i 0 i
0
gm2 rQ
2
gm1 VQ i 0 :1 1 D
gm2 rQ
1
gm2 rQ C > 1
so
gm1 VQ i 0
i 0 g
m1
VQ
i0 g
a VQ Vi
m1
Vi
Option (B) is correct.
Crossover behavior is characteristic of calss B output stage. Here 2
2
4.123
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
transistor are operated one for amplifying +ve going portion and
Page 99
4.133
and
So,
R in 1 # 103 (1 0.99 # 100) 100 k8
Similarly output impedance is given by
R0
ROUT
R 0 output impedance
(1 Cv Av)
100
Thus
18
ROUT
(1 0.99 # 100)
4.125
4.127
4.128
4.134
4.135
and
4.126
In series voltage regulator the pass transistor is in common collector configuration having voltage gain close to unity.
R in Ri (1 Cv Av)
Cv feedback factor ,
Av openloop gain
Ri Input impedance
where
V1 2V2
4.136
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4.137
4.129
4.130
Ri RB || r Q
Voltage gain
AV gm RC
Now, if CE is disconnected, resistance RE appears in the circuit
Input impedance
Input impedance
R in RB || [rQ (C 1)] RE
Input impedance increases
gm RC
Voltage gain
Voltage gain decreases.
AV
1 gm R E
So, R in Ri
Similarly
ROUT
R0
(1 CA)
4.138
ROUT R 0
Thus input & output impedances decreases.
4.139
4.131
4.132
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Page 100
2Va 4 Va V0 0
V0 3Va 4
Va V0 Va 0 0
100
10
So
VP Vn
by calculating
VP 10 # 4 5 Volt
44
V0 5.5 Volts
4.142
Vn 2 # 1 2 Volt
here VP Vn (so diode cannot be in reverse bias mode).
so current
4.141
6Va 10 8
Va 3 Volt
Ib 0 3 10 3
4
4
Ib 10 6 1 amp
4
Va V0 10Va 0
11Va V0
Va V0
11
V0 3V0 4
11
8V0 4
11
Vm
Q (R f RL)
4.145
Va Q Va V0
0
5
10
GATE Electronics and Communication Topicwise Solved Paper by RK Kanodia & Ashish Murolia
Ii Vi kVi
Z
V
i
Zin Z
Ii
(1 k)
input impedance
4.146
4.147
Page 101
4.148
V0 6 volt
I 96
50 8
I 60 m amp
Maximum allowed power dissipation in zener
PZ 300 mW
Maximum current allowed in zener
PZ VZ (IZ ) max 300 # 103
&
6 (IZ ) max 300 # 103
&
(IZ ) max 50 m amp
Given knee current or minimum current in zener
In given circuit
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