MOS Transistors as Switches

G
(gate)
D
(drain)
S
(source)
G
D S
nMOS transistor:
Closed (conducting) when
Gate = 1 (V
DD
)
Open (non-conducting) when
Gate = 0 (ground, 0V)
pMOS transistor:
Closed (conducting) when
Gate = 0 (ground, 0V)
Open (non-conducting) when
Gate = 1 (V
DD
)


For nMOS switch, source is typically tied to ground and is used to pull-down signals:

G
Out
S
when Gate = 1, Out = 0, (OV)

when Gate = 0, Out = Z (high impedance)


For pMOS switch, source is typically tied to V
DD
, used to pull signals up:

Out
G
S
when Gate = 0, Out = 1 (V
DD
)
when Gate = 1, Out = Z (high impedance)


Note: The MOS transistor is a symmetric device. This means that the drain and source terminals
are interchangeable. For a conducting nMOS transistor, V
DS
> 0V; for the pMOS transistor, V
DS

< 0V (or V
SD
> 0V).
The CMOS Inverter

Out
I I Out
Truth Table
I Out
0 1
1 0
GND
V
DD
R
in


Note: Ideally there is no static power dissipation. When "I" is fully is high or fully low, no
current path between V
DD
and GND exists (the output is usually tied to the gate of another MOS
transistor which has a very high input impedance).

Power is dissipated as "I" transistions from 01 and 10 and a momentory current path exists
between Vdd and GND. Power is also dissipated in the charging and discharging of gate
capacitances.

Parallel Connection of Switches

A
Y
B
Y = 0, if A or B = 1



A + B


Y
A B
Y = 1 if A or B = 0



A + B


Series Connection of Switches

A
Y
B
Y = 0, if A and B = 1



A B


A
B
Y
Y = 1, if A and B = 0



A B

NAND Gate Design
p-type transistor tree will provide "1" values of logic function
n-type transistor tree will provide "0" values of logic function

Truth Table (NAND):

AB
00 1
01 1
10 1
11 0

K-map (NAND):

1 1
1 0
0
1
0
1
A
B


NAND circuit example:

Y
A
B
Vdd
P
tree
= A + B
N
tree
= A B
Y
A
B


NOR Gate Design
p-type transistor tree will provide "1" values of logic function
n-type transistor tree will provide "0" values of logic function

Truth Table:

AB
00 1
01 0
10 0
11 0

K-map:

1 0
0 0
0
1
0
1
A
B


NOR circuit example:

Y
A
B
Vdd
Y
A
B
P
tree
= A B
N
tree
= A + B


What logic gate is this?

Y
A
B
Vdd
Y = 1 when A B
Y = 0 when A + B


Answer: AND function, but poor design!
Why? nMOS switches cannot pass a logic "1" without a threshold voltage (V
T
) drop.

G
D S
V
DD
V
DD
V
DD
- V
T


where V
T
= 0.7V to 1.0V (i.e.,
threshold voltage will vary)
output voltage = 4.3V to 4.0V,
a weak "1"

The nMOS transistor will stop conducting if V
GS
< V
T
. Let V
T
= 0.7V,

G 5V
S D
0V 5V
D ?
0V ?


As source goes from 0V 5V, V
GS
goes from 5V 0V.
When V
S
> 4.3V, then V
GS
< V
T
, so switch stops conducting.
V
D
left at 5V V
T
= 5V 0.7V = 4.3V or V
DD
V
T
.


What about nMOS in series?

5V
0V 5V
0V 4.3V
0V 4.3V
0V 4.3V
5V - 0.7V
4.3V
5V 5V 5V
0V (V
DD
V
T
)


Only one threshold voltage drop across series of nMOS transistors


For pMOS transistor, V
T
is negative.
pMOS transistor will conduct if |V
GS
| > |V
Tp
| (V
SG
> |V
Tp
|),
or V
GS
< V
Tp


G
0V
5V
S D


conducting



V
Tp
= 0.7V
V
GS
= 0V 5V = 5V


V
GS
< V
Tp
or |V
GS
| > |V
Tp
|
5V < 0.7V 5V > 0.7V
How will pMOS pass a "0"?

G 0V
S D
5V ?
D ?
5V 0V



When |V
GS
| < |V
Tp
|, stop conducting

So when |V
GS
| < |0.7V|, V
D
will go from 5V
0.7V,
a weak "0"

How are both a strong "1" and a strong "0" passed?
Transmission gate pass transistor configuration

I
A B

When I = 1,
B = strong 1, if A = 1;
B = strong 0, if A = 0

When I = 0, non-conducting

About that AND Gate...

Y
A
B
Vdd
No!!!
Poorly designed AND
(circuit designer fired)


Instead use this,

Y
A
B
A
Vdd
Y
B


More Complex Gates

F = AB + CD N
tree
will provide 0's, P
tree
will provide 1's

0's of function F is F, F = AB + CD = AB + CD

nMOS transistors need high true inputs, so it is desirable for all input variables to be high true,
just as above.

Y
A
B
C
D
AB + CD


Likewise, a P
tree
will provide 1's.
F = AB + CD, need a form involving A, B, C, D

Apply DeMorgan's Theorem:

F = AB CD = ( A + B) (C + D)

Implementation
Y
A B
C D

Can also use K-maps:


F = AB + CD

1 1
1
AB
CD
0
0 1
0
0 0 0
1 1 1
0
1
1


For N
tree
, minimize 0's; for P
tree
, minimize 1's

AB
CD
0
0
0
0 0 0 0






N
tree
= AB + CD





1 1
1
AB
CD
1
1 1 1
1
1




P
tree
= AC + AD + BC + BD
= A (C + D) + B (C + D)
= (A + B) (C + D)




Introduction to Static Load Inverters

1)
I
R
O
resistor load


V
OH
= 5V,
V
OL
close to 0V, depends on ratio R/R
ON



When I = 1, inverter dissipates static power.

Switching point of inverter depends on ratio of
R to R
ON
(on resistance of nMOS device.


Note: output can swing from almost 0V to 5V (V
DD
)

2)
I
O
D
S




Load is enhancement-mode nMOS device.


Again, static power dissipation occurs when
I = 1.



Note: output swings from nearly 0V to (V
DD
V
Tn
)

Using a transistor as a load tends to require much less silicon area than a resistor.

V
OH
= V
DD
V
Tn
,
V
OL
can be close to 0V, depending on ratio of R
ON
of

two enhancement devices

Depletion-mode nMOS


nMOS device with V
Tn
< 0V (negative threshold voltage). Device is always conducting if V
GS
>
0V.

3)
I
O
D
S




V
GS
= 0V always

Load device is always on, looks like a load
resistor.

Dissipates static power when I = 1
V
OH
= 5V; V
OL
nearly 0V, depending on ratio of R
ON,dep
to R
ON,enh
.

Depletion-mode devices were used before it was economical to put both p-type and n-type
devices on the same die.

4) pMOS device as static load

I
O
D
S





Here also the load device is always on
(conducting).

Dissipates static power when I = 1.


V
OH
= 5V; V
OL
nearly 0V, depending on ratio of R
ON,p
to R
ON,n



Basic MOS Device Equations

Gate
Source
Drain
Bulk (or substrate for nMOS device in n-well technology)


The nMOS device is a four terminal device: Gate, Drain, Source, Bulk.

Bulk (substrate) terminal is normally ignored at schematic level, usually tied to ground for the
nMOS case. In analog applications, however, the bulk terminal may not be ignored.

Gate controls channel formation for conduction between Drain and Source. Drain at higher
potential than Source Source usually tied to GND to act as pull-down (nMOS).

Three regions of operations first-order (ideal) equations:

Cutoff region

I
D
= 0A V
GS
V
Tn
(nMOS threshold voltage)


Linear region

I
D
=

2
V
)V V (V
2
DS
DS T GS n

0 < V
DS
< V
GS
V
Tn


Note: I
D
is linear with respect to (V
GS
V
Tn
) only when ( ) 2 V
2
DS
is small.


Saturation region

I
D
= ( 0 < V )
2
T GS
V V
2

GS
V
Tn
< V
DS



Device parameters:

= transistor gain factor, dependent on process parameters and
device geometry (K
n
)


=

t
ox

W
L
process dependent, constant
under control of the designer


As W/L increases, effective R
ON
of device decreases

= surface mobility of the carriers in the channel

= permittivity of the gate insulator

t
ox
= thickness of the gate insulator

See Figure 2.5, 2.8 concerning , , and t
ox


SPICE represents by a factor given by

K' = C
ox
=

t
ox
= KP


So,
I
D
= (
2
T GS
V V
L
W
2
K'
n
) ; saturation region


VI characteristic

V
DS
V
GS
I
D


V
DS
V
GS1
V
GS2
V
GS3
V
GS4
V
GS5
G
S
|V
GS
- V
T
| = |V
DS
|
boundary between
linear & saturation
regions (dashed line)
SATURATION
LINEAR
CUTOFF

V

D
I


Things to note:
In the "linear" region, I
D
becomes less and less linear with V
GS
as V
DS
becomes large.
This is because the ( ) 2 V
2
DS
term in the linear region grows large.

Higher V
GS
values increase channel conductance allowing for higher values of I
D
for a
given V
DS
.






*MOSFET Characteristics
Vds 1 0 DC 10
Vgs 2 0 DC -.723
Vdummy 3 0 DC 0
M1 1 2 3 3 Mfet
.MODEL Mfet NMOS(KP=3686U VTO=2.30 LAMBDA=0.137)
.DC Vds 0 10 .2 Vgs 2.5 5 .5
.probe
.end





What do W and L physically look like?

nMOSFET layout:

W
L
Drain
n+ diffusion
Source
n+ diffusion
Gate (polysilicon)


In digital logic, typically will draw all transistors with the minimum gate length and vary the
width.

Larger W larger transconductance (more current flow for given gate voltage), higher gate
capacitance

During fabrication process, the actual width and length of the channel can be reduced by
diffusion from the bulk, source, and drain into the device channel.

SPICE has some MOSFET model parameters to account for this effect, LD and WD, where the
actual the actual length and width is calculated as

L
effective
= L
drawn
- 2 LD

W
effective
= W
drawn
- 2 WD

If LD, WD parameters not specified in the model, then SPICE assumes they are 0.


Ideal Inverter
V
out
V
in
V
DD
V
DD
2
switching
point


Actual Inverter Characteristics, some definitions
V
in
(V)
V
OH
V
OL
V
IL
V
IH
V
th
V
out
(V)


V
IL
represents the maximum logic 0 (LOW) input voltage that will guarantee a logic 1
(HIGH) at the output

V
IH
represents the minimum logic 1 (HIGH) input voltage that will guarantee a logic 0
(LOW) at the output

Noise Margin

Illustration of Noise Margin:

NM
L
NM
H
V
in
Input logic 1
Input logic 0
0V
V
IL
V
IH
V
DD
V
out
V
OH
V
DD
0V
V
OL
Output logic 1
Output logic 0


Calculate noise margin using

NM
L
= V
IL
- V
OL
NM
H
= V
OH
- V
IH



How do we determine V
IL
, V
OL
, V
OH
, and V
IH
?

We must exam the inverter's transfer characteristic.
CMOS Inverter Regions of Operation

0
1
2
3
4
5
0 10
0
3 10
-5
6 10
-5
9 10
-5
1.2 10
-4
1.5 10
-4
0 1 2 3 4 5
V
o
u
t

(
V
)I
D
D

(
A
)
V
in
(V)
V
out
I
DD
A
B D E
C



Region A:
0 V
in
<V
Tn
pMOS nonsaturated; nMOS cutoff

nMOS is cutoff because V
in
<V
Tn

Why is the pMOS device in the linear region?

Linear region V
SDp
<V
SGp
- |V
Tp
|

(5 5)V <(5 0)V |0.7|V
[for V
DD
=5V and V
Tp
=0.7V]
0V <4.3V

Note that the pMOS device can be in linear region even if I
Dp
0A!


Region B:

V
Tn
V
in
< V
th
pMOS nonsaturated, nMOS saturated

Why is nMOS saturated? Is V
DSn
> V
GSn
- V
Tn
?

Because (V
DSn
= V
out
) > V
th
and (V
GSn
= V
in
) < V
th
,

then V
DSn
> V
GSn
- V
Tn

V
out
> V
in
- V
Tn
[B-1]

Why is pMOS in linear region?

It started out in linear and will remain in linear as long as
V
SDp
< V
SGp
- |V
Tp
|
(V
DD
- V
out
) < (V
DD
- V
in
) - |V
Tp
|
V
in
< V
out
- |V
Tp
| [B-2]

V
out
in the above expression (Eqn. [B-2]) is decreasing towards V
th
and V
in
is increasing
towards V
th
. When Eqn. [B-2] no longer holds, then the pMOS device will become
saturated.

For the pMOS device, then
regions A B C correspond to
linear linear saturated, respectively.


How can you predict the output voltage for region B?

The nMOS is saturated, so I
Dn
=
2
T in
) V (V
2

n
n
=
2
T GS
) V (V
2

n n
n


The pMOS is linear, so
I
Dp
= ( )
2
SD SD T SG
) (V |)V V | 2(V
2

p p p p
p

I
Dp
= ( )
2
out DD out DD T in DD
) V (V ) V |)(V V | V 2(V
2

p
p


Can solve for V
out
since
I
Dn
= I
Dp


GND
S
D
D
S
I
Dp
I
Dn
V
DD






Equivalent circuit for region B

V
out
I
Dn


Region C:

V
in
= V
th
pMOS saturated, nMOS saturated

In order for nMOS to be saturated, need
V
DSn
> V
GSn
V
Tn

V
out
> V
in
V
Tn


In order for pMOS to be saturated, need
V
SDp
> V
SGp
|V
Tp
|
V
DD
V
out
> V
DD
V
in
|V
Tp
|
V
out
< V
in
+ |V
Tp
|

So V
out
in region C,
V
in
V
Tn
< V
out
< V
in
+ |V
Tp
|

The CMOS inverter has very high gain in region C so small changes in V
in
produce large
changes in V
out
. No closed form equation for V
out
. Somewhere in this region, V
out
= V
in
,
which is the switching point for this gate.

Equivalent circuit for region C:


V
out
I
Dn
I
Dp
V
DD


What is V
in
in region C?

In region C, both devices in saturation so

I
Dp
=
2
T in DD
|) V | V (V
2

p
p


I
Dn
=
2
T in
) V (V
2

n
n


So, using I
Dn
= I
Dp
, V
in
can be solved for (more on this later....)

Region D:

V
th
< V
in
V
DD
|V
Tp
| pMOS saturated, nMOS linear

Hence, I
Dp
=
2
T in DD
|) V | V (V
2

p
p


I
Dn
= ( )
2
out out T in
n
V )V V 2(V
2

n


Again, since I
Dp
= I
Dn
, we can solve for V
out
:

V
out
2
2(V
in
V
Tn
)V
out
+
2
T in DD
|) V | V (V

p
n
p
= 0

using x =
a
ac b b
2
4
2



and, recognizing from above,

a = 1, b = 2(V
in
V
Tn
), c =
2
T in DD
|) V | V (V

p
n
p


we get


V
out
= (V
in
V
Tn
)
2
T DD in
2
T in
|) V | V (V

) V (V
p
n
p
n
.




Equivalent circuit for region D

V
out
I
Dp



Region E:

V
in
> V
DD
|V
Tp
| pMOS is cutoff, nMOS is linear mode

Since V
SGp
= V
DD
V
in
(< |V
Tp
|),

V
out
0V

due to nMOS acting as pull-down while pMOS in cutoff.

CMOS Inverter Transfer Characteristic

0
1
2
3
4
5
0 10
0
3 10
-5
6 10
-5
9 10
-5
1.2 10
-4
1.5 10
-4
0 1 2 3 4 5
V
o
u
t

(
V
)I
D
D

(
A
)
V
in
(V)
V
out
I
DD
A
B D E
C

Analysis:
V
OH
: V
in
< V
Tn
, the nMOS transistor is in cutoff while the pMOS transistor is turned-on
(inversion layer established). The result is

V
OH
V
DD
.

V
OL
: (V
DD
V
in
) < |V
Tp
|, the pMOS is in cutoff while the nMOS is on and providing a
conduction channel to ground. Hence,

V
OL
0V.

V
IL
: Input low voltage, here the nMOS transistor is saturated and the pMOS is nonsaturated.
Equating the currents provides


2
T IL
) V (V
2

n
n
= ( )
2
out DD out DD T IL DD
) V (V ) V |)(V V | V 2(V
2

p
p
.

V
IL
: (continued) Since two unknowns exist, V
in
= V
IL
and V
out
, a second equation is needed.
Use the unity-gain condition to obtain this second equation,

in
out
dV
dV
=
) V / I (
) V / I ( ) V / I (
out D
in D in D


p
p n
= 1,

provides

V
IL

+
p
n

= 2V
out
+

p
n

V
Tn
V
DD
|V
Tp
|.

Now the two equations needed to solve for V
IL
and V
out
exist.

V
IH
: Input high voltage, here the nMOS is nonsaturated and the pMOS is saturated.
Equating the drain currents yields

( )
2
out out T IH
V )V V 2(V
2

n
n
=
2
T IH DD
|) V | V (V
2

p
p
,

the first of two equations needed to solve two unknowns, V
in
= V
IH
and V
out
. Use the
unity-gain condition to get the second,

in
out
dV
dV
=
) V / I (
) V / I ( ) V / I (
out D
in D in D


n
n p
= 1.

This provides

V
IH

+
n
p

= 2V
out
+ V
Tn
+ |) V | (V

T DD p
n
p
,

the second equation needed to solve for the two unknowns.


V
th
: At the CMOS inverter's switching point, or inverter threshold, V
th
= V
in
= V
out
and both
the pMOS and nMOS transistors are saturated. Again, equating the drain currents,

2
T th
) V (V
2

n
n
=
2
T th DD
|) V | V (V
2

p
p


is obtained which can be easily solved to provide V
th
,

V
th
=

+
+
n
p
p
n
p
n

1
|) V | (V

V
T DD T




Note: switching point of gate (V
th
) is
2
V
DD
-if-
p
n

= 1 and V
Tn
= V
Tp
.

So, switching point of inverter is function of the ratio of the nMOS/pMOS gains and the
threshold voltages of the nMOS, pMOS transistors.

n
/
p
Ratio

The
n
(gain of nMOS) /
p
(gain of pMOS) ratio determines the switching point of the CMOS
inverter.

0
1
2
3
4
5
0 1 2 3 4 5
V
out
(V)
V
in
(V)

p
= 10

p
= 1

p
= 0.1
Strong
pull-down
Strong
pull-up
Equal pull-up/pull-down
"strength"
VDD
2
Switching point = V
DD
/2
if
n
/
p
= 1 and V
Tn
= |V
Tp
|

Recall that
=

t
ox

W
L
.

If we assume that the nMOS and pMOS transistors have equal W/L ratios, then

p
=

t
ox

W
n
L
n

t
ox

W
p
L
p

=

p
=
electron mobility
hole mobility
.

In silicon, the ratio
n
/
p
is usually between 2 to 3.

This means, that if L
n
= L
p
,

then W
p
must be 2 to 3 times W
n


in order for
n
=
p
.

0
1
2
3
4
5
0 1 2 3 4 5
V
out
V
in
if
W
p
L
p
=
W
n
L
n
because

p
> 1
V
DD
2


Calculate the switching point of a static load inverter as function of
n
/
p
:

In region C, already know nMOS device is saturated from previous analysis.



V
in
V
out
V
DD






For pMOS to be saturated need:

V
SDp
> V
SGp
|V
Tp
|
V
DD
V
out
> V
DD
0V |V
Tp
|
V
out
< |V
Tp
|
Not true!!!
(If V
out
in region C is about
2
V
DD
and
2
V
DD
>
|V
Tp
|
(typically this is true))

pMOS must be in linear region

Then
2
T GS D
) V (V
2

I
n n
n
n
=
2
T in
) V (V
2

n
n
=

and ( )
2
SD SD T SG D
V |)V V | 2(V
2

I
p p p p
p
p
=
( )
2
out DD out DD T DD D
) V (V ) V |)(V V | 2(V
2

I =
p
p
p


Equate I
Dn
= I
Dp
and solve for V
out
.


2
T in
2
T DD T out
) V (V

|) V | (V | V | V
n
p
n
p p
+ =

Can also solve for
n
/
p
,

2
T in
2
T out
2
T DD
) V (V
|) V | (V |) V | (V

n
p p
p
n

=

Consider again


2
T in
2
T out
2
T DD
) V (V
|) V | (V |) V | (V

n
p p
p
n

=

for the pseudo-nMOS inverter.

Let |V
Tp
| = V
Tn
= 0.2V
DD
and V
in
= V
out
=
2
V
DD
. Then, for V
DD
= 5V,


p
n

6.1 !!!

Note that this is very different result from the CMOS inverter case!

If V
DD
= 3.3V, but the value of V
Tn
= |V
Tp
| is unchanged (i.e., 1V in the above example),
then

p
n

11.5
for a switching point equal to
2
V
DD
.

The
n
/
p
ratio depends on the absolute value of V
DD
! This means that the operation of
the pseudo-nMOS inverter will NOT scale with V
DD
(for a given CMOS technology).

For the CMOS inverter, the
n
/
p
ratio for a switching point of V
DD
/2 is independent of
V
DD
so its operation will scale with supply voltage. This is a another big advantage of
CMOS technology.

Not unusual for static CMOS circuits to operate over a very large range of power supply
voltages, i.e., 2.0V to 6.0V is common.