COE/EE 243 Lect #43

Continued from Jim Frenzel

74x163 counter
Uses 4 D flip flops
Inputs Current State Next State
/CLR /LD ENT ENP Qd Qc Qb Qa Qd* Qc* Qb* Qa*
---------------- ----------- ---------------
0 X X X X X X X 0 0 0 0 Clear
1 0 X X X X X X D C B A Parallel Load
1 1 0 X X X X X Qd Qc Qb Qa No change
1 1 X 0 X X X X Qd Qc Qb Qa No change
1 1 1 1 Count (Count + 1) Mod 16 Increment count
Ripple Carry Out or RCO is carry from the MSB and is 1 only if
Count = 15 and ENT = 1.

CLR, etc are also synchronized with the clock.
Use the inputs and Load Enable to vary the count sequence
^ ^ ^ ^
| | | |
___|_____|_____|_____|___
| Qd Qc Qb Qa |----- P
CLK-------o|> |_____ T
____| 74x163 |
Carry | |o---- Clear
| Dd Dc Db Da |o---- LD
|________________________|
| | | |
| | | |

Two 74x163's can be cascased. This counter can counts from 0 to 255.
(ask if covered).
2^7 2^6 2^5 2^4 2^3 2^2 2^1 2^0
| | | | | | | |
___|____|____|____|____ ___|____|____|____|____
| Qd Qc Qb Qa | | Qd Qc Qb Qa |
| ENP|--1 | ENP|--1
-----|RCO ENT|-------|RC0 ENT|--1
| <|--clk | <|--clk
| LD|o--1 | LD|o--1
| CLR|o--1 | CLR|o--1
|______________________| |______________________|
| | | | | | | |
| | | | | | | |
Dd Dc Db Da Dd Dc Db Da
ENT and ENP are not interchangeable. Only ENT goes to the RCO.
74x161 is binary counter with asynchronous clear.
74x160 and 74x162 are decade counters.
The 74x169 is an up/down binary counter. The state of the
UP/DOWN input line determines if the counter counts up or down.
State Machines Using Counters (such as the 74x163)
A. Use counter for timing
B. Implement state machine using the timer
1. Start from a state table/diagram (after state reduction if any)
2. It is easiest to do a straight binary state assignment
3. Reach the reset (assigned to state 0) when the Clear input
to the counter is asserted.
4. Counting function is used when a transition to the next state
is required (S3-S4)
5. When the next state breaks the normal count sequence (S1-S6)
the next state is loaded by asserting LD
6. When the next state loops back to the present state, disable
the count (but don't assert LD or CLR)
Example:
| | Next State |
| Present | C+B+A+ | CLR | LD | ENT=ENP | Dc Db Da
S | CBA | X=0 X=1 | X=0 X=1 | X=0 X=1 | X=0 X=1 | X=0 X=1
----|---------|------------|---------|---------|----------|----------
S0 | 0 0 0 | 001 001 | 1 1 | 1 1 | 1 1 | XXX XXX
S1 | 0 0 1 | 010 010 | 1 1 | 1 1 | 1 1 | XXX XXX
S2 | 0 1 0 | 000 011 | 0 1 | X 1 | X 1 | XXX XXX
S3 | 0 1 1 | 110 100 | 1 1 | 0 1 | X 1 | 110 XXX
S4 | 1 0 0 | 101 101 | 1 1 | 1 1 | 0 1 | XXX XXX
S5 | 1 0 1 | 110 101 | 1 1 | 1 0 | 1 1 | XXX XXX
S6 | 1 1 0 | 000 000 | 0 0 | X X | X X | XXX XXX
S7 | 1 1 1 | XXX XXX | X X | X X | X X | XXX XXX
Solve expression for CLR, LD, ENT, ENP, Dc, Db, and Da as functions
of C, B, A and X. Set Dd to always be 0.
Section 8.5 Shift Registers
Serial In - data shifted in one bit at a time at first flip-flop
Serial Out - data can only be read out at last flip-flop.
Parallel In - data can be loaded in parallel.
Parallel Out - data can read in parallel.
Shift registers combine these operations. For example, you might
have serial in and parallel out or parallel in and serial out.
SH L | Next State
(shift) (load) | Qa+ Qb+ Qc+ Qd+
-----------------+-------------------
0 0 | Qa Qb Qc Qd (no change)
0 1 | Da Db Dc Dd (parallel load)
1 X | SI Qa Qb Qc (right shift)
Da Db Dc Dd
| | | |
+--+---+---+---+--+
Serial Input SI --| |
Shift Enable SH --| 74x178 |
Load Enable L --| |
Ck -o|> |
+--+---+---+---+--+
| | | |
| | | +------ Serial Out
| | | |
Qa Qb Qc Qd
Consists of 4 SR flip-flops. SI is only input to flip-flop A
Ra = Sa' to avoid S=1, R=1.
We can use a shift register IC like the 74x178 to implement a
state machine. We need to use the SH and L inputs to control
state transitions.
1. If the next state from a present state can be reached by
shifting the present state to the right and adding an appropriate
serial bit (0100 to 1010 for example) we use the shift input
and set SI to 1.
2. If we want to shift to a totally new state, for example
from 0100 to 1001 we load the new state from Da, Db, Dc and Dd.
3. If the state loops back on itself for a given input, set both L=SH=0
As a result, we need to determine logic expressions for:
L, SH, SI, Da, Db, Dc, and Dd as a function of: Qa, Qb, Qc, Qd and
external inputs such as X (or Y etc).