EXPERIMENT # 5

IMPLEMENTATION OF COMBINATIONAL FUNCTIONS

USING VARIOUS LOGIC GATES

1. Objectives
Having completed this experiment you will be able to
• Understand the technical problems in a more logical way.
• Recognize and implement the logic gates in combinational digital
circuit design.
• Understand the relationship between logic circuit, Boolean function
and the Truth table.

2. Introduction:

2.1 Combinational Logic Circuit

A combinational circuit consists of logic gates whose output at any time is determined
directly from the present combination of inputs without regard to previous inputs. A
combinational circuit performs a specific information-processing operation fully
specified logically by a set of Boolean function.

2.2 Combinational Function.

An expression that has only two values, TRUE (1)or FALSE(0), consisting of a logical
variable or of logical variables connected by logical operators. Boolean expressions are
used to implement digital circuits with efficiency. First of all we construct the truth table
and from that we generate the Boolean expression and translate that expression into gates.
In designing digital circuits, the designer often begins with a truth table describing what
the circuit should do. The design task is largely to determine what type of circuit will
perform the function described in the truth table. While some people seem to have a
natural ability to look at a truth table and immediately envision the necessary logic gate
or relay logic circuitry for the task, there are procedural techniques available for the rest
of us. Here, Boolean algebra proves its utility in a most dramatic way.
Example:
To illustrate this procedural method, we should begin with a realistic design
problem. Suppose we were given the task of designing a flame detection circuit for a
toxic waste incinerator. The intense heat of the fire is intended to neutralize the toxicity
of the waste introduced into the incinerator. Such combustion-based techniques are
commonly used to neutralize medical waste, which may be infected with deadly viruses
or bacteria. So long as a flame is maintained in the incinerator, it is safe to inject waste
into it to be neutralized. If the flame were to be extinguished, however, it would be
unsafe to continue to inject waste into the combustion chamber, as it would exit the
exhaust un-neutralized, and pose a health threat to anyone in close proximity to the
exhaust. What we need in this system is a sure way of detecting the presence of a flame,
and permitting waste to be injected only if a flame is "proven" by the flame detection
system.
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Several different flame-detection technologies exist: optical (detection of light), thermal
(detection of high temperature), and electrical conduction (detection of ionized particles
in the flame path), each one with its unique advantages and disadvantages. Suppose that
due to the high degree of hazard involved with potentially passing un-neutralized waste
out the exhaust of this incinerator, it is decided that the flame detection system be made
redundant (multiple sensors), so that failure of a single sensor does not lead to an
emission of toxins out the exhaust. Each sensor comes equipped with a normally-open
contact (open if no flame, closed if flame detected) which we will use to activate the
inputs of a logic system.

Suppose that one of the three sensors were to fail in such a way that it indicated no flame
when there really was a good flame in the incinerator's combustion chamber. That single
failure would shut off the waste valve unnecessarily, resulting in lost production time and
wasted fuel (feeding a fire that wasn't being used to incinerate waste).
It would be nice to have a logic system that allowed for this kind of failure without
shutting the system down unnecessarily, yet still provide sensor redundancy so as to
maintain safety in the event that any single sensor failed "high" (showing flame at all
times, whether or not there was one to detect). A strategy that would meet both needs
would be a "two out of three" sensor logic, whereby the waste valve is opened if at least
two out of the three sensors show good flame.

3. Experimental Work:
In this experiment, you will Implement a combinational logic by applying the
various inputs, according to the table given here under and find out the results with
respect to the Boolean expression..
Input A Input B Input C Input Output F

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 0 0 0 A ′ B′ C′
0 0 1 A ′ B′ C
0 1 0 A′ BC′
0 1 1 A′ BC
1 0 0 AB′ C′
1 0 1 AB′ C
1 1 0 ABC′
1 1 1 ABC
3.1Material Required.
• IC components74ls32,74ls08,74ls04
• Connecting Wires
• Logic Trainer
4.Procedure
• Connect the Logic trainer to 220 volts AC power supply.
• Install the IC,s 74ls32, 74ls08,74Ls04 on trainer,s breadboard.
• Wire the circuit according to the diagram shown as here under..
• Use logic switches to provide inputs at A,B and C as per table provided in step 3..
• Connect the output of the circuit to the LED provided on the breadboard.
• Verify the .truth table with respect to the inputs and outputs to satisfy the system
to be designed.

4.2Experimental results
• FILL IN THE TABLE PROVIDED IN STEP 3 AS AN OUTPUT FOR YOUR
COMBINATIONAL LOGIC CIRCUIT DESIGNED

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5. In case of Trouble.
• Check the power supply.
• Check the Vcc and GND at pin number 14 and 7 of the IC under test.
• Check all the wire connections and remove the breaks.
• Check the IC under test using truth table.
8. Questions.
Communicational circuit has four input and one output the output is equal to 1 when
a) All the input is are equal to “1”.
b) None of the input are equal to one.
c) The odd number of inputs equal to one
• Obtain the truth table ?
• Find the simplified output function in SOP?
• Draw the logic diagram.?

Experiment # 6
IMPLEMENTATION OF HALF ADDER & FULL ADDER

1. Objectives: Having completed this experiment you will be able to

• Understand the use of logic gates in arithmetic operations.
• Understand the addition of two binary digits using. Logic circuit as
a half adder.
• Understand the performance of combinational circuit that performs
the addition of three bits (two significant bit and a previous carry)
called a full-adder.
2. Basic Information:

2.1 Half Adder:

Half Adder is combinational logic circuit that generates the sum of two binary
numbers (each having 1 bit length). The logic circuit has two inputs and two outputs i.e.
Sum & Carry abbreviated as SHA & CHA respectively. First of all, we shall construct Truth
Table of Half Adder

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 x
Now we write Boolean function from above Truth Table as

SHA =x′ y + xy′

CHA = xy

2.2 Full Adder:

Full Adder is combination logic circuit that performs the sum of 3 input binary numbers,
(each having 1 bit length). Two of the binary input variables are x and y represent the two
significant bits to be added the third input z, represents the carry from previous lower
significant position. Outputs of Full Adder are Sum and Carry represented as SFA and CFA
respectively.

x y
SFA = (x y) z

CFA = (x y) z + xy

3. Experimental Work

3.1 Material Used:

• 74ls86,74ls08,74ls32,74ls04
• Connecting wires
• Logic Trainer
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3.2 Procedure:
• Wire the circuit according to the pins supply indicator i.e. +5v to
pin number 7,14 respectively.
• Interconnect the basic logic gates as per logic diagrams given for
half adder and full-adder
• Implement the given Boolean expression by basic logic gates, verify and
write the result in the truth table

Truth Table
i/p’s o/p’s
X Y SHA = x′ y+xy′ CHA = x y
Actual Observed Actual Observed
0 0
0 1
1 0
1 1

Truth Table

i/p’s o/p’s
x y z SFA CFA
Actual Observed Actual Observed
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Sum = x′ y′ z+x′ yz′ +xy′ z′ +xyz
Simplifying by using Boolean Postulates & theorems/k-map, we get
Sum =(x′ y+xy′ ) ′ . z + (x′ y+xy′ ).z′
SFA = (x ⊕ y ) ⊕ z

Carry = x′ yz + xy′ z + xyz′ +xyz

Simplifying by using Boolean Postulates & theorems/k-map, we get
Carry = (x′ y+xy′ ) . z+xy
CFA = (x ⊕ y) z + xy

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 1
1
4.
•
2
In Case of Trouble:
Check the power supply.

2
• Check the Vcc and GND at pin number 14 and 7 of the IC under test.
• Check all the wire connections and remove the breaks.
• Check the IC under test using truth table.

1
3 1
3
4 7432
4
5
5 7

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6
 EXPERIMENT NO. 7:
DESIGN THE BCD-TO-SEVEN-SEGMENT DECODER
CIRCUIT.

1. Objective: Having completed this experiment you will be able to

• Understand the basic concept of BCD to Seven segment decoder.

1. Basic Information
For this laboratory, the combinational logic circuit is used to convert a four-bit
binary coded decimal (BCD) value to the signals required for a seven-segment display.
BCD-to-seven-segment decoder is a combinational circuit that accepts a decimal digit in
BCD (binary-coded decimal) and generates the appropriate output for selection of
segments in a display indicator used for displaying the digit. The seven outputs of the
decoder (a, b, c, d, e, f, g) select the corresponding segment in the display as shown in
figure: a

f b
g

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 Figure 6.1: Seven – Segment display

You are likely familiar with the idea of a seven-segment indicator for representing
a
decimal numbers. Each asegment aof a seven-segment
a a
display is a small light-emitting
diode (LED)f or liquid-crystal
b f b f displayb f(LCD), band
f a decimal
b number is indicated by
g
lighting a particular g
combination ofg the LED's
g or LCD'sg elements is shown below:

e c e c e c e c e c
d d d d d
a a a a a

f b f b f b f b f b
g g g g g

e c e c e c e c e c
d d d d d

Figure: Indication of decimal number on Seven – Segment display

Bindary-coded-decimal (BCD) is a common way of encoding decimal numbers with 4

binary bits as shown below:
BCD Code Decimal Digit
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9

Fill in the truth table for seven segment device whose display elements are active low.
That is, each element will be active when its corresponding input is '0'.

Truth Table:
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 Inputs
A B C D a b c d e f g
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
Truth table for seven – segment display

Rest of bit combinations are used with don’t care condition.

2. Experimental Work
3.1 Material Used:
• Logic trainer
• Connecting wires
• 14 pin ICs
• Seven-Segment Display
• IC7447
• Power supply

1. Procedure
• Wire the IC chip and connect the +5v (Vcc) and ground the pin number 16
and 8 respectively.
• The BCD (8421) code is listed in table given from this table you can
determine the relation between each BCD bit and the decimal digits in
order to analyze the logic.
• For instance, the most significant bit of BCD code, A3 is always a “1” for
decimal digit 8 and 9. An OR expression for bit A3 in terms of a decimal
digits can there for be written is
• A3= 8+9
• Bit A2 is always a one a decimal digit is always “1” for 4,5,6 or 7 and can
be expressed as an OR function as follows.
• A2= 4+5+6+7
• Bit A1 is always a one for decimal digit 2,3, 6 or 7 and cn be expressed as
• A1 =2+3+6+7
• Finally a zero is always a 1 for decimal digit 1,3,5,7, or 9 the expression for
zero is
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 • A0=1+3+5+7+9

5.Questions
5.1 Question:
Modify the BCD to Decimal decoder circuit provided to give output of all 0’s
when any invalid input combination occurs.

EXPERIMENT # 8
INTRODUCTION, IMPLEMENTATION AND WORKING WITH
MULTIPLEXERS,DECODERS AND ENCODERS

1. Objectives: Having completed this experiment you will be able to

• Imply a 74ls151 as a Multiplexer
• Verify the basic operation and principle of Multiplexer , decoder and
encoder.
2. Basic Information.

2.1 A digital Multiplexer is a combinational circuit that selects binary

information from one of many input lines and directs it to a single output
line. The selection of a particular input line is controlled by a set of
selection lines. Normally, there are 2n input lines and “n” selection lines
whose bit combination determine which input is selected.
2.2 A decoder is a combinational circuit that converts binary information from
n input lines to maximum of 2n unique output lines. The decoders are
represented as n-to-m where n is number of inputs and m is number of
outputs. Hence, 2-to-4 decoder means that two inputs are decoded into 4
outputs.
2.3 An encoder is a digital function that produces a reverse operation from that
of a decoder. An encoder has 2n input lines and n output lines. The output
lines generate the binary code for the 2n input variables.

3. Experimental Work.
3.1 Material Used.
• 74ls151, 7432,7408,7404
• Connecting Wires
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 • Logic Trainer
4. Procedure.

We will implement the multiplexer circuit first. It is clear from the logic
diagram that the AND, OR and NOT gate implementation of multiplexer requires
four 3-input AND gates, one 4-input OR gate and two NOT gates. Get the required
number of ICs containing above mentioned gates and other apparatus from the lab
attendant. Install the ICs in the breadboard of the Logic Trainer. All three IC
models used are 16 pin ICs. These are designed in such a way that pin number 8 is
considered as ground and power is given to pin number 16. For other pin
configuration consult the data sheet (we have already used these gates in the first
lab so it should not be a problem). Wire your circuit according to the logic
diagram for multiplexer circuit as given above. Once you have wired the circuit,
check it with your instructor and, if approved, power up your circuit. The outputs
should be connected to the LEDs on the Logic Trainer for monitoring purpose.
Repeat the same procedure for decoder and encoder circuit.

Multiplexer
Multiplexer, simply called Mux, is a data selector and is capable of
“selecting” one of many input lines (usually 2n) and display its input status
on the only output line available.

A Mux has
1. Select lines
2. Data input lines
3. Output line.

Block diagram of 2x1 MUX

I0, I1 are inputs of Mux

S is select line
Y is output

d
The function table of 2x1 Mux is
a t a i / p
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 Select line o/p
S Y
0 Io
1 I1

The Boolean function for 2x1 Mux is

Y = I1 s + I0 s′

Logic Diagram of 2x1 Mux is

I1 s I0

Block diagram of 4x1 MUX

I0, I1,I2 and I3 are inputs of Mux

S1 and S0 are select lines
Y is output

The function table of 4x1 Mux is

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 Select o/p
lines
S1 S0 Y
0 0 Io
0 1 I1
1 0 I2
1 1 I3

.
The Boolean function for 4x1 Mux is
Y = I0 S1′ S0′ + S1′ S0 I1+ S1 S0′ I2+ S1 S0I3
Logic Diagram of 4x1 Mux is

S1

We check this logic circuit by Function Table of 4X1 Mux as drawn above.

Block diagram of 2x 4 Decoder

D0
A
D1
2x4
Decoder
D2
B
D3

D0
A
D1
2x4
Decoder
D2
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The truth table of 2-to-4 line decoder is given below. The output variables of a
decoder are mutually exclusive because only one output can be equal to 1 at any
time.
Inputs Outputs
A B D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

Draw the logic diagram of 2x4 decoder:

The truth table for 4-to-2 encoder is given below

Inputs Outputs
D0 D1 D2 D3 X Y
1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1

1. EXPERIMENTAL RESULT

Fill in the following truth tables while observing the outputs.

Truth table for multiplexer:

Select inputs Output

S1 S0 Y

Truth table for decoder:

Inputs Outputs

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 A B D0 D1 D2 D3

Truth table for encoder:

Inputs Outputs
D0 D1 D2 D3 X Y

2. In the Case of Trouble:

• Check the power supply.
• Check the Vcc and GND at pin number 14 and 7 of the IC under test.
• Check all the wire connections and remove the breaks.

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 EXPERIMENT # 9
IMPLEMENTATION OF FULL ADDER WITH 2, 2X4
DECODERS
Apparatus: 74139, 7400 IC’s and connecting wires
Decoder :
n → 2n .
n = No. of input lines.
2n = No. of outputs of a Decoder.
Decoder is a circuit that convert binary information from n-input lines to
max of 2n output lines e.g. if we have 2 inputs i.e. x, y then there will be 4
outputs of a Decoder and size of Decoder will be 2x4.

Block Diagram of 2X4 Decoder.

data input lines

Truth Table of 2X4 Decoder
x y E d0 d1 d2 d3
x
0 0 1 1 0 0 0
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 1
Boolean Functions for 2 x 4 Decoder

y
do = E x′ y′
d1 = E x′y
d2 = E x y′
d3 = E x y

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Implementation

x
Now we implement Half Adder with 2x4 Decoder.

Truth Table of Half Adder

i/p’s o/p’s
x y SHA CHA
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Truth Table of 2X4 Decoder

i/p’s o/p’s
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 x y d0 d1 d2 d3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

By comparing Truth Tables of half Adder and 2 X 4 Decoder.

We can see that SHA = d1 + d2

CHA= d3

Block Diagram of Half Adder with Truth Table of 2X4 Decoder

Note:

x
By connecting an OR gate with output Pin 1 & 2 of 2X4 Decoder. Half Adder can be
implemented with 2X4 decoder. Similarly by connecting two Half Adders, we can form a
Full Adder by using 2, 2X4 Decoder.

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Truth Table of Full Adder
i/p’s o/p’s
x y z SHA CHA
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Block Diagram of Full Adder with 2, 2X4 Decoders.

Using the concept of implementation of Half Adder with 2X4 Decoder, we can
implement Full Adder with 2, 2 X 4 Decoders.

x
Pin Configuration of 74LS139

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2
 E

Data i/p
lines o
EXPERIMENT # 10
IMPLEMENTATION OF FULL ADDER WITH 8x1 MUX
Apparatus: 74151 MUX, connecting wires.

MUX :
2n → 1.
n = No. of select lines.
2n = No. of inputs of MUX
lines

if n = 3, size of MUX is 8x1 i.e.

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 I0
Function Table
Select lines o/p
I1
x Y z Y

I2
0 0 0 Io
0 0 1 I1
0 1 0 I2
0
1
1
1
0
0
1
0
1
Data input lines
I3
I4
I5
1
1
1
1
0
1
I6
I7
I3
Pin Configuration of 74151 MUX
I4
I5
I6
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 1

Truth Table of Full Adder

x
i/p’s of Full Adder
y z S
o/p’s
C
2
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
Data i/p

0 1 1 0 1
1 0 0 1 0
lines
1 0 1 0 1

3
1 1 0 0 1
1 1 1 1 1

4
Function Table of 8x1 Mux

i/p of Full Adder = Select o/p of o/p of 8x1 o/p of 8x1

lines of MUX 8x1 mux mux mux
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 x y z S=Y C=Y
0 0 0 0 0 I0
0 0 1 1 0 I1
0 1 0 1 0 I2
0 1 1 0 1 I3
1 0 0 1 0 I4
1 0 1 0 1 I5
1 1 0 0 1 I6
1 1 1 1 1 I7

Procedure:

First of all we check/implement Carry of Full Adder (having 3 inputs) using 8X1 Mux,
for this take :
I0 = 0, I1 = 0, I2 = 0, I3 = 1, I4 = 0, I5 = 1, I6 = 1, I7 = 1, from Carry column of Truth table
of Full Adder and then select x,y,z from Function table of 8X1 Mux and then observe
outputs at Y Pin of 74151 IC, that should be equal to Carry of Full Adder for combination
of x,y,z at select lines, which is inserted through data switches, this step is repeated for
all x,y,z combinations, at select lines to observe Carry of Full Adder.

Then we check/implement Sum of Full Adder for 3 input variables, using 8X1 Mux for
this, we take :
I0 = 0, I1 = 1, I2 = 1, I3 = 0, I4 = 1, I5 = 0, I6 = 0, I7 = 1, from Sum column of Truth Table of
Full Adder, as data inputs to 8X1 Mux, and then for each combination of x,y,z at select
lines from Function table,.we see output at Y Pin of 74151 IC, which should be equal to
value of Sum of Full Adder for x,y,z combination at select lines, which is inserted
through data switches, this step is repeated for all x,y,z combinations, at select lines to
observe Sum of Full Adder.

EXPERIMENT # 11

VERIFICATION OF THE TRUTH TABLE OF RS FLIP FLOP

1. Objective: Having completed this experiment you will be able to

• Understand the basic concept of Flip Flops
• Recognize its working according to their truth table.

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 • Working with the IC chip of RS flip flop.
• Design a circuit of RS flip flop using NAND and NOR gates.

1. Basic Information.
Flip-flops (FFs) are devices used in the digital field for a variety of purposes. When
properly connected, flip-flops may be used to store data temporarily. Flip-flops are
bistable multivibrators. The types used in digital equipment are identified by the
inputs. They may have from two up to five inputs depending on the type. They are all
common in one respect. They have two, and only two, distinct output states. The
outputs are normally labeled Q and Q’ and should always be complementary. When
Q = 1, then Q’ = 0 and vice versa.
The R-S FF is used toQtemporarily hold or store information until it is needed. A
S
single R-S FF will store one binary digit, either a 1 or a 0. The standard symbol for
the R-S FF is shown
FF in figure below.

R Q’

2.1: Draw the figure below:

To understand the operation of the RS-flip-flop (or RS-latch) consider the case when S=1
and R=0: The output of the bottom NOR gate is equal to zero, Q'=0. Hence both inputs to
the top NOR gate are equal to one, thus, Q=1. Hence, the input combination S=1 and R=0
leads to the flip-flop being set to Q=1. S=0 and R=1: Similar to the arguments above, the
outputs become Q=0 and Q'=1. We say that the flip-flop is reset. S=0 and R=0: Assume
the flip-flop is set (Q=0 and Q'=1), then the output of the top NOR gate remains at Q=1
and the bottom NOR gate stays at Q'=0. Similarly, when the flip-flop is in a reset state
(Q=1 and Q'=0), it will remain there with this input combination. Therefore, with inputs
S=0 and R=0, the flip-flop remains in its state. S=1 and R=1: This input combination
must be avoided.

Truth Table for RS flip-flop with NOR Gates:

Inputs Outputs Comments

R S Q Q’
0 1 1 0 Set
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 0 0 1 0 Hold
1 0 0 1 Reset
0 0 0 1 Hold
1 1 ? ? Avoid
Truth table RS flip flop

2. Experimental Work:
3.1 Material Used.
• Logic trainer
• Connecting wires
• IC
• Power supply

1. Procedure:
The NOR gate implementation of RS flip-flop requires NOR gates AND gates. Get the
required ICs and other apparatus from the lab attendant. Install the IC 7400 in the
breadboard of the Logic Trainer. Connect 5Vdc power supply and ground on pins 14 and
7 respectively. For other pin configuration consult the data sheet (we have already used
these gates in the first lab so it should not be a problem). Wire your circuit according to
the logic diagram you have drawn. Once you have wired the circuit, check it with your
instructor and, if approved, power up your circuit. The outputs should be connected to the
LEDs on the Logic Trainer for monitoring purpose. Apply different input combinations at
the input and note down the Q and Q’ outputs and fill in the following truth table. This
truth table should conform to the one given in theory. If there are problems, consult the
appendix on troubleshooting given at the end of lab manual. If the problem persists,
request the lab supervisor for help.
2. Experimental Results:
Fill in the following truth table by observing the outputs.

Truth Table for RS flip-flop with NOR Gates:

Inputs Outputs Comments

S R Q Q’
0 0
0 1
1 0
1 1

3. Question:
Draw the circuit of RS Flip flop using NAND gates and also draw its truth table.

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 EXPERIMENT # 12
VERIFICATION OF THE TRUTH TABLE OF JK FLIP FLOP

1. Objectives: Having completed this experiment you will be able to

• Understand the basic concept of Flip Flops
• Recognize its working according to their truth table.
• Working with the IC chip of JK flip flop.
• Design a circuit of RS flip flop using NOR and NAND gates.

1. Basic Information.
A JK flip flop is a refinement of the RS flip-flop int that the indetermined state of the RS type is
defined in the JK type. It has two inputs, traditionally labeled J and K. If J and K are
different then the output Q takes the value of J at the next clock edge. If J and K are both
low then no change occurs.Q If J and
Q’ K are both high at the clock edge then the output will

toggle from one state toJ the other.

K The JK flip-flop is represented by the following
graphic symbol:
CP

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 Graphic symbol for JK flip-flop

In a clocked JK flip-flop, output Q is ANDed with K and CP (clock pulse) inputs so that
the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, output
Q’ is ANDed with J and CP inputs so that flip-flop is set with a clock pulse only if Q’
was previously 1.
Characteristic table for JK flip-flop is given below:
Q J K Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Characteristics table for JK flip - flop

2.1: Draw the logic diagram of a JK flip flop using NOR and AND gates:

Fill the following characteristics table for NAND gate JK flip flop:

Q J K Q(t+1)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Characteristics table NAND gates JK flip - flop

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BSE III
Sept 2009 to Jan 2010
2. Experimental Work:
3.1 Material Used.
• Logic trainer
• Connecting wires
• IC
• Power supply

1. Procedure:
The implementation of JK flip-flop requires two 2-input NOR gates and two 3-input
AND gates. Get the required ICs and other apparatus from the lab attendant. Install the
ICs in the breadboard of the Logic Trainer. Connect 5Vdc power supply and ground on
pins 14 and 7 respectively. For other pin configuration consult the data sheet (we have
already used these gates in the first lab so it should not be a problem). Wire your circuit
according to the logic diagram you have drawn. Once you have wired the circuit, check it
with your instructor and, if approved, power up your circuit. The outputs should be
connected to the LEDs on the Logic Trainer for monitoring purpose. Apply different
input combinations at the input and note down the Q (t+1) outputs and fill in the
following truth table. This truth table should conform to the one given in theory. If there
are problems, consult the appendix on troubleshooting given at the end of lab manual. If
the problem persists, request lab supervisor for help.

Repeat the same procedure for implemention of JK flip-flop with NAND gates.

2. Experimental Results:
Fill in the following truth tables by observing the outputs.
JK with NOR gates:
Q J K Q(t+1)

Observed characteristics table for NOR JK flip - flop

JK with NAND gates:

Q J K Q(t+1)

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BSE III
Sept 2009 to Jan 2010
 Observed characteristics table for NAND gates JK flip - flop

Experiment # 13
SHIFT REGISTER OPERATION (NIGHT RIDER)
RING COUNTER

1. Objectives: Having completed this experiment you will be able to:

• Understand the basic concept of storing binary data (byte)
• Construct the four bit register using IC 74ls74 flip flop.
• Develop a ring counter using basic flip flop 74ls74 to examine
the concept of shifting data around in a circularly shift register.

2. Basic Information:
2.1
A register capable of shifting its binary information either to the right
or left is called a shift register. The logical configuration of a shift register
consists of a chain of flip flop connected in cascade, with a output of one flip
flop connected to the next flip flop. All flip flops receive a common clock
pulse which causes the shift from one stage to the next.
2.2 Ring Counter:
A “K” ring counter circulates a single bit among the flip flop to
provide “K” distinguishable states.

3. Experimental Work:
3.1 Material Used.
• 74ls74 IC (2)
• Wire connecting
• Logic Trainer
4. Procedure:
• Install the two-74ls74 s on the trainer’s breadboard.
• Wire the circuit according to the diagram given.
• Set S1 to low, set S3, S4, S5 and S6 to high

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BSE III
Sept 2009 to Jan 2010
 • Set S2 to low and than back to high, this resets all flip flops. All four
LEDs should be OFF.
• Move S3 to low and than back to high. This has set (preset) the first
flop; its Q output should be high and L1 should be lit.
• Now cycle the data through the ring flip flop by supplying a clock
signal. Move S1 to high and than back to low. Note that the high has
moves to L2.
• Again cycle the S1 high than low. The data again should have shifted
one position.
• Continue to cycle S1, observing that four clock are needed to get the
data completely around the loop.
• Set S1 low. Set S2 low than high.
• Set S5 and S6 both low and than high. Observe that L3 and L4 are lit.
• Cycle S1. Observe that the data recirculates.
• This circuit is also called “ring counter” or “Johnson counter” and
often used to recirculate one bit that is used to turn on one digit in a
strobed display.
• Use CLK signal available on SBB 63 instead S1 and observe that how
the data recirculate.
• Do the same experiment using 7-Segment Decoder/Driver for output
indication.

5. In Case of Trouble
• Check the power supply.
• Check the Vcc and GND at pin number 14 and 7 of the IC under test.
• Check all the wire connections and remove the breaks.
• Check the IC under test using truth table.

6. Question:

6.1
The content of a 4-bit shift register is initially 1101. The register is
shifted six times to the right, with the serial input being 101101. What is the
content of the register after each shift?

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BSE III
Sept 2009 to Jan 2010
 Appendix A: Use good construction practices

• ESD (Electro-Static Discharge) prevention: The failure rate of electronic components

(including IC's) that are produced worldwide is only a few PPM (parts per million). The
failure rate in our labs, where we don't use proper techniques to prevent ESD damage due
to handling seems to be more like 10%. Could it be that we are damaging the parts?!!
Most successful companies will train you in ESD damage prevention, but would then
FIRE you for handling parts the way we do in most KSU labs. Use wrist straps and
understand ESD damage prevention.
• Use ONE common ground point.
• Keep inputs and low-level signal stages away from digital, output, and high power stages.
You may even create an unwanted oscillator if you don't do this.
• For some applications, you need to isolate stages with a transformer or an opto-isolator to
avoid ground problems.
• Be sure that your logic levels are all the same or provide level shifters. Beware of mixing
TTL and CMOS.
• Do not leave inputs of "unused" op amps, comparators, or CMOS logic gates open.
Connect them to an appropriate fixed voltage. DO leave the outputs floating.

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BSE III
Sept 2009 to Jan 2010
 Appendix B: Troubleshooting
○ Turn on the DC power first, and then the signals. (Avoid latch-up)
○ Keep a current copy of your circuit diagram beside the circuit and correct it as
you make changes. Keep a paper trail, or listing, of your lab work.
○ Keep your layout neat and label nodes on bigger circuits.
○ Check your DC power supply currents. If you have current limiting on the
supplies, set it just above what you expect for the total current.
○ Watch for smoke and/or hot parts. (Use saliva on your digit temperature sensor to
avoid burns.)
○ Be sure that the COMmon of the power supply is connected to ground. The
"ground" of many power supplies is isolated from the supply outputs.
○ Check the DC level at the output of each active device. If it's about equal to the
positive or negative supply it's saturated or cut-off. Check all DC bias points.
Vbe's should be about .7V and FET gates should be greater than VT's if they're
supposed to be on.
○ Look for loose wires.
○ Now start checking signals: Use an oscilloscope to monitor signals starting at the
input.
○ Recheck your circuit wiring one more time. This is the most common error and
by now you should have a good idea where the problem is located.
○ If you observe 60Hz where signals should be you probably had an open ground
somewhere.
○ Isolate parts of the circuit if you can and test individual circuits. This will not
always work with feedback circuits, because the feedback may be required to
give a stable operating point.
○ If you suspect a bad part, turn off the signal first, and then the dc power. Finally,
remove and replace the part.
○ Perhaps the most important thing is to understand what each part of the circuit is
supposed to do and then play like a detective.
○ Make measurements as near full scale on the meter as possible.
○ Make a note of measured voltages on the circuit diagram.
○ Think!

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BSE III
Sept 2009 to Jan 2010
 Appendix C: Safety

Freedom from preventable accidents is an important measure of the foresight and capability of
supervision in the engineering industries. The student should give thought to the subject of
accident prevention early in his or her training. He or she should prepare mentally to recognize
and avoid dangerous situations, and to cope with emergencies. A set of rules cannot be made to
apply to all situations. The student should develop the ability to analyze a particular situation. An
engineer's reputation for reliability is seriously injured if his lack of foresight results in injury to
himself, associates, or equipment.
Haste causes many accidents. Work deliberately and carefully. Verify your work as you go along.
Documentation and good planning before coming to the laboratory will promote safety.

• When working on live electrical apparatus, use only one hand as far as practical, keeping
the other hand disengaged from circuitry. All ac power circuits are dangerous.
Adjustment in energized circuits should be made with caution. Do not permit any part of
your body to complete a circuit.
• Close power switches quickly and positively. Hesitant closing may result in an electric
arc. Burns from an electric arc maybe severe and slow-healing. You can depend on the
circuit breakers and fuses in the circuit to prevent over-currents. (Electric arcs and contact
lenses are a bad combination.)
• Be careful to keep watch bands, rings, necklaces, and other metallic objects out of contact
with live parts when working around electrical apparatus. It is a good idea to remove
watches with metal bands while working in the laboratory.
• Long hair should be "up" when working around rotating machinery. Likewise, loose
clothing, neckties, etc., should be avoided around rotating machinery.
• Make sure the banana plugs fit snugly in their sockets. Sometimes they get old and worn
so that they slide out too easily. Never splice two banana cords together so that
electrically "hot" metal is exposed on the bench. There are a number of banana sockets on
the bench which can be used if splicing is necessary.
• If any banana jack connectors are loose on their cords, or if any sockets are loose, report
them immediately to the lab instructor.
• When wiring a circuit, always connect to the source of power as the last step. When
disassembling a circuit, disconnect from the power source as the first step.
• Never work alone in the laboratory. Injury could occur and there would be no one present
to help you.

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BSE III
Sept 2009 to Jan 2010