Project Arbiter

Weighted Priority Arbiter
Global Academy of Technology Page 1

DECLARATION

We hereby declare that the project entitled WEIGHTED PRIORITY ARBITER
submitted in partial fulfillment of the requirements for the award of degree of
Bachelor of Technology in Electronics and Communication Engineering. This
dissertation is our original work and the project has not formed the basis for the
award of any degree, associate ship, fellowship or any other similar titles and no
part of it has been published or sent for the publication at the time of submission.

PARAAG A MEGHARAJ
(1GA11EC054)



ACKNOWLEDGEMENT

We wish to take this opportunity to express our deep gratitude to all those
who helped, encouraged, motivated and have extended their cooperation in
various ways during our project work. It is a pleasure to acknowledgement the
help of all those individuals who were responsible for foreseeing the successful
completion of the project.
We would like to thank Mr. L. VASUDEVA MURTHY (Head, CED) and
express our gratitude with great admiration and respect to our project guide
Mr. SOURABH SHUKLA, Mr. GAUTHAM AND Ms. Y LAKSHMI DEEPTHI for their
valuable advice and help throughout the development of this project by providing
with the required information without whose guidance, cooperation and
encouragement, this project couldnt have been materialized.
Last but not the least; we would like to thank the entire respondents for
extending their help in all circumstances.

PARAAG A MEGHARAJ
(1GA11EC054)



CONTENTS

1. Organization profile 04
2. Verilog .07
3. Abstract ....15
4. Introduction 16
5. Project Definition .........17
6. Project overview .18
7. PIN description ....19
8. Finite state machine .20
9. Functional Description of FSM ..21
10. State diagram 22
11. Working ...23
12. Waveforms .24
13. Features ...28
14. Application ....28
15. Conclusion ..29
16. Bibliography ..29



ORGANISATION PROFILE
ECIL was setup under the department of Atomic Energy in the year 1967 with a view to
generate a strong indigenous capability in the field of professional grade electronic. The initial
accent was on self-reliance and ECIL was engaged in the Design Development Manufacture and
Marketing of several products emphasis on three technology lines viz. Computers, control
systems and communications. ECIL thus evolved as a multi-product company serving multiple
sectors of Indian economy with emphasis on import of country substitution and development
of products and services that are of economic and strategic significance to the country.
Electronics Corporation of India Limited (ECIL) entered into collaboration with OSI
Systems Inc. (www.osi-systems.com) and set up a joint venture "ECIL_RAPSICAN LIMITED". This
Joint Venture manufacture the equipments manufactured by RAPSICAN, U.K, and U.S.A with
the same state of art Technology, Requisite Technology is supplied by RAPSICAN and the final
product is manufactured at ECIL facility.
Recognizing the need for generating quality IT professionals and to meet the growing
demand of IT industry, a separate division namely CED has been established to impart quality
and professional IT training under the brand name of ECIT. ECIT, the prestigious offshoot of ECIL
is an emerging winner and is at the fore front of IT education in the country.

Mission
ECILs mission is to consolidate its status as a valued national asset in the area of
strategic electronics with specific focus on Atomic Energy, Defense, Security and such critical
sectors of strategic national importance.



Objectives
To continue services to the countrys needs for the peaceful uses Atomic Energy. Special
and Strategic requirements of Defence and Space, Electronics Security System and
Support for Civil aviation sector.
To establish newer Technology products such as Container Scanning Systems and
Explosive Detectors.
To re-engineer the company to become nationally and internationally competitive by
paying particular attention to delivery, cost and quality in all its activities.
To explore new avenues of business and work for growth in strategic sectors in addition
to working realizing technological solutions for the benefit of society in areas like
Agriculture, Education, Health, Power, Transportation, Food, Disaster Management etc.

Divisions
The Company is organized into divisions serving various sectors, national and
Commercial Importance. They are Divisions serving nuclear sector like Control & Automation
Division (CAD), Instruments & Systems Division (ISD), Divisions Serving defence sector like
Communications Division (CND), Antenna Products Division (APD), Servo Systems Division (SSD)
etc., Divisions handling Commercial Products are Telecom Division (TCD), Customer Support
Division (CSD), Computer Education Division (CED).

Exports
ECIL is currently operating in major business EXPORT segments like Instruments and
systems design, Industrial/Nuclear, Servo Systems, Antenna Products, Communication, Control
and Automation and several other components.



Services
The company played a very significant role in the training and growth of high calibre
technical and managerial manpower especially in the fields of Computers and Information
Technology. Though the initial thrust was on meeting the Control & Instrumentation
requirements of the Nuclear Power Program, the expanded scope of self-reliance pursued by
ECIL enabled the company to develop various products to cater to the needs of Defense, Civil
Aviation, Information & Broadcasting, Tele communications, etc.



VERILOG
Verilog is a hardware description language (HDL). HDL is used to describe a digital system for example, a
network switch, a microprocessor or a memory or simple flip flop. Verilog is case sensitive. All verilog
keywords are lower case. Identifiers are name used to given an object, such as a register or a function or
a module, a name so that it can reference from other places in a description.
2.1. Design Styles
. Bottom up Design
. Top down Design
2.2. Abstraction Level of Verilog
. Behavioral level
. Register Transfer level
. Gate level
2.2.1. Behavioral level
The level describes a system by concurrent algorithms (Behavioral). Each algorithm itself sequential,
that means it consists of instructions that executed one after the other. Functions, tasks, always blocks
are the main elements.
2.2.2 Register Transfer level
Designs using the register transfer level specify the characteristics of a circuit by operations and
the transfer of data b/w registers. Modern definition of RTL code is any code that is synthesizable is
called RTL code. RTL design contains exact timing possibility, operations are scheduled to occur at
certain times.
2.2.3 Gate level
Within the logic level the characteristics of a system are described by logical links and their timing
properties. All signals are discrete signal. They can only have definite logical values (0,1,X,Z). The
usable operation are predefined logic primitives (AND, OR, NOT). Using gate level modeling might not be
a good idea for any level of logic design. Gate level code is generated by tools like synthesis tools and


this net list is used for gate level simulation and for backend. Verilog has built in primitives like gates,
transmission gates and switches. Gates have one scalar O/P and multiple scalar I/P. The 1 st terminal in
the list of gate terminals is an O/P and other terminals are I/P. transmission gates are bi directional
and can be resistive or non resistive. Transmission gate tran and rtran are permanently on and do not
have a control line. Tran used to interface two wire with separate drives and rtran can be used to
weaken signals. Resistive devices reduce the signal strength which appears on the output by one level.
All the switches only pass signals from source to drain, incorrect wiring of the devices will result in high
impedance output.
2.3. Gate and Switch delays
2.3.1. Rise delays
Rise delay is associated with a gate output transition to 1 from another value (0, X, Z).
2.3.2. Fall delays
The fall delay is associated with a gate O/P transition to 1, X, Z from another value.
2.3.3. Turn off delays
Gate output transition to Z from another value (0, 1, X).
2.3.4. Minimal delays
Minimum delay value that the gate is expected to have.
2.3.5. Typical delays
Typical delay value that the gate is expected to have.
2.3.6. Maximum delays
Maximum delay value that the gate is expected to have.
Verilog has built in primitives like gates, transmission gates and switches. This is rather small number of
primitives, if we need more complex primitives, then verilog provides UDP or simply user defend
primitives. By using UDP we can model Combinational logic and sequential logic.
2.4. Identifiers
Identifiers must start begin with an alphabetic character or the underscore character (_). Identifiers
may contain (a z, A Z, _ , $). Identifier can be long up to 1024 character.
2.5. Data Types
2.5.1. Nets


Represents structural connections between components.

2.5.2. Registers
Represent variable used to store data.
2.5.3. Register data types
Register store the last value assigned to them until another assignment statement changes their value.
Register represent data storage constructs. You can create arrays of register called memories. Register
data types are used as variables in procedural blocks. A register data type is required if a signal is
assigned a value with in a procedural block. Procedural blocks begin with keyword initial and always.
reg: unsigned variable.
integer: signal variable 32 bits.
time: unsigned integer 64 bits.
Real: Double precision floating point variable.
2.5.4. String
A string is a sequence of characters enclosed by double quotes and all contained on signal line. One
eight bit ASCII value representing one character. No extra bits are required to hold a termination
character.
\n New line character.
\t Tab character.
\\ Back slash (\) character.
\ Double quote () character.
\ddd A character specified in 1 3 octal digits.
%% Percent (%) character.
2.5.5. Operators
2.5.5.1. Logical Operators
! (NOT), && (AND), || (OR).
2.5.5.2. Bit wise Operators


~ (Negation), & (AND), | (Inclusive OR), ^ (Exclusive OR), ^~ or ~^ (Exclusive NOR).

2.5.5.3. Reduction Operators
& (AND), ~& (NAND), | (OR), ~| (NOR), ^~ or ~^ (XNOR), ^ (XOR).
2.5.5.4. Shift Operators
<< (Left Shift), >> (Right Shift). The left operand is shifted by the number of bit positions given by the
right operand. The vacated bit positions are filled with zeroes.
2.5.5.5 Concatenation Operators
{}.
2.5.5.6. Replication Operators
{{}}.
2.5.5.7. Conditional Operators
Cond_expr ? True_expr : False_expr.
2.5.6. Procedural Blocks: Two type of procedural blocks in verilog.
2.5.6.1: Initial:
Initial blocks execute only once at time zero.
2.5.6.2: Always:
Always blocks loop to execute over and over again, in other words as name means, it executes always.
Always blocks waits for the event, here positive edge of clock, where as initial block without waiting just
executed all the statements within begin and end statement.
If a procedure block contain more than one statement, those statement must be enclosed within:
a) Sequential begin end Block.
b) Parallel Fork join Block.
2.6. Blocking Assignment:
Blocking assignment are executed in the order they are coded, hence they are sequential. Since they
block the execution of next statement, till current statement is executed, they are called blocking
assignments.


Symbol ( = )

2.7 Non Blocking Assignment:
Non Blocking assignment are executed in parallel. Since the execution of next statement is not blocked
due to execution of current statement, they are called non blocking statement.
Symbol (<=)
2.8. Conditional Statement if else:
When more than one statement needs to be executed for a if conditions, then we need to use begin and
end. We normally do not include reset checking in priority as this does not fall in the combo logic input
to the flip flop. When we need priority logic, we use next if else statements. On other end if we do
not to implement priority logic, knowing that only that only one I/P is active at a time.
2.9. Case Statement: The case statement compares a expression to a series of cases and executes
the statement or statement group associated with the first matching case. Case statement supports
single or multiple statements. Group multiple statements using begin and end keywords.
2.10. Loop Statements:
2.10.1 Forever:
Forever statement executes continually, the loop never ends. Narmally we use forever statement in
initial blocks.
Syntax : forever <Statement>.
If no timing construct is present in the forever statement, simulation could hang.
2.10.2 Repeat:
The repeat loop executes statement fixed <number> of times.
Syntax: repeat <Number> <Statement>.
2.10.3 While:
The while loop executes as long as an evaluates as true.
Syntax : while ().
2.10.4 For:
Syntax: for (initial assignment; expression; step assignment);


Note : i ++ does not have in verilog. i = i + 1 in verilog.

2.11. Continuous Assignment statements:
Continuous assignment statements drive nets. They represent structural connections.
a) They are used for modeling tri state buffers.
b) They can be used for modeling combinational logic.
c) They are outside the procedural blocks.
d) The continuous assign overrides any procedural assignments.
e) The left hand side of a continuous assignment must be net data types.
Syntax: Assign (strength, strength) # (delay) net = expression;
2.11.1 Propagation Delay: Continuous assignments may be have a delay specified, only one delay for
all transitions may be specified.
Syntax: assign #(A minimum : Typical : maximum delay range may be specified)
To model sequential logic, a procedure block must be sensitive to positive edge or negative edge of
clock. Model asynchronous reset, procedure block must be sensitive to both clock and reset. All the
assignments to sequential logic should be made through non blocking assignments. Some time it
tempting to have multiple edge triggering variables in the sensitive list, this is fine for simulation, but for
synthesis this does not make sense. Delays the execution of a procedural statement by specific
simulation time.
Syntax: # <Time> <Statement>.
Delays the execution of the next statement until the specified transition on a signal. {edge sensitive
event controls}
Syntax: @(<Posedge > | <Negedge> signal) <statement>.
Level Sensitive even controls (Wait statements) delay execution of the next statement until the
evaluates as true.
Syntax : Wait().
Intra assignment timing controls evaluate the right side expression right always and assigns the
result after the delay or event control. In non intra assignment controls right side expression
evaluated after delay or event control.


Syntax: a = # 10 2.{intra assignment}.
Modeling combo logic with continuous assignments, whenever any signal changes on the right hand
side, the entire right hand side is re evaluated and the result is assigned to the left hand side.

2.12. Task:
Task are used in all programming languages, generally known as procedures or sub routines. Task are
defined in the module in which they are used. It is possible to define task in separate file and use
compile directive include to include the task in the file which instantiates the task. Task can include
timing delays, like posedge, negedge, #delay and wait. Task can have any number of I/P and output. The
variables declared within the task are local to that task. Task can take, drive and source global variables,
when no local variables are used. Task can call another task or function. Task can be used for modeling
both combinational and sequential logic. Task begin with keyword task and ends with keyword task.
Local variables are declared after I/P and O/P declaration.
2.13 Function
Function is same as task, with very little difference, like function can not drive more then one output,
can not contain delays. Function can not include timing delays, like posedge, negedge, #delay. Function
executed in zero time delay. Function can have any number of I/P but only one output. Function can call
other functions, but can not call task.
2.14.1. $display: Display once every time they are executed.
2.14.2. $monitor: Display every time, one of its parameters changes.
2.14.3. $Strobe: Display the parameters at the very end of the current simulation time unit rather than
exactly where it is executed.
2.14.4. $time: Return the current simulation time as a 64 bit.
2.14.5. $Stime: Return the current simulation time as a 32 bit.
2.14.6. $realtime: Return the current simulation time a real number.
2.14.7. $reset: It resets the simulation back to time 0.
2.14.8. $stop: Halts the simulator and puts it in the interactive mode, where user can enter commands.
2.14.9. $finish: exits the simulator back to the operating system.
2.14.10. $random: it generates a random integer every time it is called.



Note:
%d decimal
%h hexadecimal
%b binary
%c character
%s string
%5d gives exactly 5 spaces for the number.
2.15. Initializing Memories
A memory array may be initialized by reading memory pattern file from disk and storing it on the
memory array by using $ readmemb and $ readmemh.
2.15.1 $redmemb
It is used for binary representations of memory content.
2.15.2 $readmemh
It is used for hex representation of memory content.
Syntax: $readmemh (file name, mem-array, start_adder, stop_addr).



ABSTRACT
This arbiter has a scalable input request. Weight is given to each of the incoming request to the
arbiter. This scheme is used to avoid starvation of requests in a fixed priority arbiter which
continuously gives grant to higher priority requests. Here the requests are serviced in a round
robin manner. Assuming N number of requests, the higher priority request is given the highest
weight. A register should be maintained for each request indicating its priority. Initial value of
weight should be supplied as input for each request. One popular weighted priority arbitration
implementation in the contemporary flow-control SoC design is to allocate a set of credits to
each client then process the requests in a round robin fashion. Credit register associated with
each client are initialized with a value that represents the number of credits. More number of
credits is allocated to higher priority requests. When a client asserts a request to the arbiter, it
can only be issued a grant if it has credits available. After a grant is issued, the credit register of
that client is decremented. If the credit registers of all the clients are zero, then credit registers
are re-initialized with their original values and the arbitration process repeats.



Introduction
An important form of arbiter is used in asynchronous circuits, to select the order of access to a
shared resource among asynchronous requests. Its function is to prevent two operations from
occurring at once when they should not. Given only one request, an arbiter promptly permits
the corresponding action. Delaying any second request until the first action is completed. When
the arbiter gets two requests at once, it must decide which request to be granted first. For
instance, there may be a time multiple PCI agents would like to initiate a data transfer. This is
not possible since all the agents share the same bus and two agents cannot place data on the
same wire at the same time. The PCI arbiter schedules use of the bus, telling the PCI when they
may initiate the data transfer. The arbiter guarantees that there are never two actions
underway at the same time.
So how does the arbiter decide which requestor should be granted first to access the resource?
This task is performed by considering some function units to have higher importance (or
priority) than other units. The request to access the shared resource by the function unit of
higher importance is granted first and subsequently the functions with lesser priorities are
granted access.
However, accesses to the requests from the function unit of higher priority could lead to
starvation of access opportunities to requests from function units with lesser priorities. This
problem is solved by using the concept of request masking and round robin scheduling.
Benefits: protection against heavy users.
Disadvantage: if a connection has a small weight and the number of connections are large, this
may lead to long periods of unfairness.



Project Definition
This project illustrates the design and working of weighted priority arbiter.
In this project, arbiter has its inputs scalable. Weight is assumed to be provided with each
incoming request. The requests are serviced in round robin manner.
Assume there are N requests (req1-reqN), the higher priorities are given higher weights. A
register is maintained for each request indicating its priority. Initial value of weight should be
given as input for each request by the requestor. Weight register associated with each
requestor are initialized with a value that represents the number of weight available to that
particular client. When the requestor asserts a request to the arbiter, it can issue the grant only
if the requestor has available weight. After a grant is issued, the weight register associated with
that request is decremented and the request is masked till the time all other requests are
serviced once. If the weight registers of all the requests are found to be zero, then the weight
registers are re-initialized and the process repeats.
The arbiter begins its operation only if at least one request is asserted. If no requests are
available then the arbiter remains idle.



Project Overview

1: PIN Diagram Weighted priority arbiter

Req 1 Grant 1
Wgt 1
Req 2 Grant 2
Wgt 2
Req 3 Grant 3
Wgt 3

Req N Grant N
Wgt N

Clk Rst

figure 1: PIN diagram

Weighted
Round
Robin
Arbiter

WEIGHTED
PRIORITY
ARBITER


Pin Description

NAME INPUT/OUTPUT DESCRIPTION
Clk Input Operating frequency
Rst Input Resets all request and grant
Req 1 Input This pin represents request 1 to arbiter
Wgt 1 Input This pin represents weight of request 1 to arbiter
Grant 1 Output This pin represents the grant of request 1 to arbiter
Req N Input This pin represents request 1 to arbiter
Wgt N Input This pin represents weight of request 1 to arbiter
Grant N Output This pin represents the grant of request 1 to arbiter



Finite State Machine (FSM)
A finite-state machine (FSM) or finite-state automaton (plural: automata), or simply a state
machine, is a mathematical model of computation used to design both computer programs and
sequential logic circuits. It is conceived as an abstract machine that can be in one of a finite
number of states. The machine is in only one state at a time; the state it is in at any given time
is called the current state. It can change from one state to another when initiated by a
triggering event or condition; this is called a transition. A particular FSM is defined by a list of its
states, and the triggering condition for each transition.
The behavior of state machines can be observed in many devices in modern society which
perform a predetermined sequence of actions depending on a sequence of events with which
they are presented. Simple examples are vending machines which dispense products when the
proper combination of coins is deposited, elevators which drop riders off at upper floors before
going down, traffic lights which change sequence when cars are waiting, and combination locks
which require the input of combination numbers in the proper order.
Finite-state machines can model a large number of problems, among which are electronic
design automation, communication protocol design, language parsing and other engineering
applications. In biology and artificial intelligence research, state machines or hierarchies of
state machines have been used to describe neurological systems and in linguisticsto describe
the grammars of natural languages.
Formally, an FSM is specified by five entities: symbolic states, input signals, output signals, next-
state function and output function

state_next state_reg
Input
clk

Next state
logic
State
register
Moore
output logic
Mealy
output logic


Functional Description of FSM :
Reset: Initially the reset signal is assumed to be high. When the reset signal is high every grant
is made low, weight and request registers and flag registers (flaga, flagb, flagc, flagd) are made
low. State A is set as the present state. As soon as the reset signal is made low, the arbiter is
begins its tasks.
A: This state counts the number of clients requesting for the grant signal and stores it in a
register (count). If no requests are present, the arbiter stays in the same state otherwise moves
to state B.
B: Here the weight register (wt) is initialized with the weight sent by each client. Another
weight register (w) is maintained which is used to store the decremented values of the
requests. These registers are also used to compare the priorities of the requests. Which of the
clients has requested for grant signal is stored in a separate request register (r).
C: Requests with the highest priority is determined by comparing their weights. If two requests
are found to be having same weights, then the request which has been granted least number of
times is chosen for grant. Each time this state is executed, the value of count register is
decremented by one. If a request with weight zero is selected then the control goes back to
state A.
D: The request selected in state C is given the grant and its weight is decremented. The request
after getting the grant once is masked so that the last request that was served, cannot be
served again, forcing the arbiter to grant the next request. If the value of count register is zero
the control is given to state A otherwise the control goes back to state C.
The transfer of control from one state to anther is facilitated with the help of the flag registers.
At any point of time during the operation of the arbiter, if the reset signal is set to high, the
arbiter will immediately go back to state A and wait till the reset signal becomes low again.



FSM of weighted priority arbiter
Flaga=0

Reset

Flagd=0 Flaga=1
Count=0

Flagc=0

Flagd=1
Count!=0 Flagb=1
Flagc=1

Figure 2 FSM

A
D B
C


Working of Weighted priority Arbiter
In this project, we design the arbiter by using FSM technique. The control of the arbiter is
divided into 4 states namely A, B, C, and D. initially the reset is assumed to be high making state
A as the present state. The operation of the arbiter starts as soon as the reset is set low.
1: State A:
This state checks if any requestor is requesting for a grant. If yes, then how many requestors
are present? The number of requestors is stored in a register named count. The flag register
(flaga) is set high for a non-zero value of count. Depending on the value of the flaga the next
state is determined.
flaga=1 => next state=B
flaga=0 => next state=C

2: State B:
The first task is to initial the weight registers (wt) with the input weights (wgt).
wt[0]=wgt1
wt[1]=wgt2
wt[2]=wgt3
wt[3]=wgt4
Another set of weight registers (w) are used to hold the updated value of the weights i.e. the
value after they are decremented. If the value of all the w registers is zero, then their values
are re-initialized from the wt register. Request registers (r) are used to implement the
masking concept. To illustrate the masking process let us consider 4 requests- req1, req2,
req3, req4. Hence the value of request register will be r=1111 where the LSB bit and MSB bit
represent req1 and req4 respectively. If req4 has the highest priority, it will be given the grant
first. After the grant signal is provided, req4 is masked i.e. value of r=0111. This ensures that
the higher priority request will not be given grant continuously.


Flagb is set high signaling that the arbiter can now proceed to state C.

3: State C:
This state determines which of the requests is having the highest weight. If two requests are
found to have the same highest priority, then the request which has been granted least number
of times is given the grant. The weights of masked requests are not compared.
The selected request is stored a register named la.
If a request having weight zero is selected in this state, then the control is immediately
transferred to state A and hence it is not provided with the grant signal.
The value of the count register is decremented by one.
The next state depends on the value of flagc.
Flagc=1 => next state=D
Flagc=0 => next state=A
4: State D:
Grant is provided to the request selected in state C. Weight of that request is decremented
by 1 and the request is masked.
Value of flag register flagd is updated according to the value of the count register. Flagd=1 for a
non-zero value of the count register.
The next state is determined from the value of flagd.
Flagd=1 => next state=C
Flagd=0 => next state=A



Waveform

Reset is set high for 150 nsec. As soon as the reset is set low, requests are asserted by all the
four requestors req1, req2, req3 and req4 with weights 10, 15, 9 and 7 respectively. Since req2
has the highest weight, it is granted first at 180 nsec. At the same time req2 is masked and its
weight is decremented to 14. Subsequently the next requestor with the highest weight is
provided grant, its weight is decremented and the request is masked and so on.
At 240 nsec all the requestors are granted once and hence all the requests are masked. At 260
nsec the requests are again unmasked and the process continues.



At 650 nsec req3 withdraws its request. Hence it is not serviced. The remaining requestors
whose requests are still asserted are serviced in the similar fashion.



At 1150 nsec req3 gets asserted again and the all other requestors withdraw their requests. As
only one request is asserted, it is provided with grant signal continuously. As weight of the
request is decremented each time it is given grant, at 1540 nsec the weight of all the requests is
0. Hence at 1560 nsec, weights of all the requestors are re-initialized.



The purpose of a weighted arbiter is to allow each requestor a share of the common resource
which is relative to his predefined weight. For example, if only two requestors have the weight
of 3 and 4 respectively, then over a long period of time, assuming both requestors always have
their request asserted, the first one will get 3/7 of the grants and the second will get 4/7 of the
total grants.
The weight is therefore a mean for setting specific priorities to the different requestors.
Contrary to the strict priority arbitration, the weighted arbiter maintains the fairness for all
requestors and prevents starvation by serving all requestors according their relative predefined
weight, preventing one requestor from dominating the shared resource indefinitely. Using this
arbiter results in the number of acknowledges for each valid requestor being relative to its
proportional weight with the exception that an inactive requestor is skipped regardless of its
weight.

Weighted Priority Arbiter Features:
1. Ensure fair access to a shared resource in a system e.g. system bus.
2. This arbiter has its input requests scalable.
3. Synchronous reset capability.
4. Weight of each request represents its priority level.
5. Weights set to be initial state value when all N weights become zero.
6. Masking capability to prevent starvation of lower priority requests.

Application
Complex System-on-Chip (SoC) architecture comprises multiple master and slave modules.
Master modules such as processors and hardware accelerators send requests or data to slave
modules like memories or register banks. Efficient communications between master and slave
modules require adequate on-chip interconnected architectures with arbitration that features
content resolution, prioritization, and fairness.



Conclusion
The design of a Weighted Priority round robin arbiter using Finite State Machine (FSM), is both
simple and efficient, making the seemingly complicated features of a round robin arbiter a
straight forward task. The usage of masking concept for blocking the request which has been
given the grant once and unmasking it when all the requests are serviced once is the best way
to implement the round robin functionality.
The overall design is robust, scalable, and easy to extend to any number of requests and simple
for pipeline integration.

Bibliography
www.tkt.cs.tut.fi/kurssit/9636/K05/Chapter18.pdf
www.sciencedirect.com/science/article/pii/0165607482900102
cseweb.ucsd.edu/classes/sp08/cse140L/lab2/starter_files/ch1to12.pdf
www.imit.kth.se/courses/IL2207/0506/Lectures/2B1448_L3_Buses.pdf
www.wolesinski.net/Publications/Papers/10SLJ.pdf
http://en.wikipedia.org/wiki/Finite-state_machine

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