Lecture 3 ECE 425

Lecture 3 -- Static CMOS Gates

Lecture 3 ECE 425
Outline
Static CMOS Logic Gates
Concepts
Formalized design process
Lecture 3 ECE 425
Static CMOS
In steady state, a gate will have either a path from output-
ground through N-FETs or a path from output-power
through P-FETs
Strong drive of gates that use the output
Rail-to-rail signaling, with restoring logic
Low static power consumption
Inputs to logic gates connect to gate terminals of FETs
High input resistance allows large fanout with correct
behavior, although performance will suffer
Lecture 3 ECE 425
Remember the Inverter
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Generalizing to Other Gates
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Computing AND
Connect two transistors in series, and you get an AND
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OR Functions
Transistors in parallel give OR
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CMOS NAND Gate
P-FETs in parallel to V
dd
, N-FETs in series to ground
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CMOS NOR Gate
P-FETs in series to power, N-FETs in parallel to ground
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Generalizing to More Complex Gates
CMOS gate has a p-network that connects to power and
an n-network that connects to ground
Define:
f
p
is a function that is true if and only if the p-network
conducts
f
n
is a function that is true if and only if the n-network
conducts
If the gate implements a function F, then f
p
= F = !f
n
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Other Logic Functions are Combination of AND, OR
Take the function
Find the n-network function !F
Replace AND/OR subexpressions with series/parallel
connections
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p-network is
Again, replace AND/OR subexpressions with
series/parallel transistors
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Combine the p- and n-networks to get the full gate
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Your Turn
Implement
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Our Solution
p-function
n-function
Circuit
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Non Series-Parallel Designs
This technique gives you a correct circuit, which may not
be the best circuit
Finding the best circuit may be non-trivial
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Representing Circuits as Graphs
Draw graph from circuit by
Mapping nodes in the circuit to vertices in the graph
Mapping transistors to edges labeled with the gate
input of the transistor
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Ok, Sure, but Why Would You Do That?
Graph representation of circuit is easier for CAD
programs to manipulate
Generating the dual of a circuit from its graph may be
easier than negating the Boolean expression
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Planar Dual Graphs
If the graph for a circuit is planar, theres a simple process
to generate its dual (the graph of the negation of the
circuits function)
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Creating the Dual of a Planar Graph
1. Add vertical lines from the output and V
dd
/ground nodes
of the original graph out to infinity
2. Create one node in each of the half-planes defined by
the original graph. These will be the output and
V
dd
/ground nodes of the new graph.
3. Place a vertex of the new graph (G) in every finite region
of the plane defined by the original graph G
4. For each edge E in G
1. Find the vertices in G that lie on either side of E
2. Join those vertices with an edge E
3. Label that edge with the negation of the label on E
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Huh?
Time for an example!
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Going the Other Way -- From Circuit to Function
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Example
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Next Time
Overview of fabrication
Reading:
Section 1.5