CHAP.

4]

CHARACTERISTICS OF FIELD-EFFECT TRANSISTORS AND TRIODES

111

are attracted to the region immediately beside the metal oxide lm (this is called enhancement-mode
operation) to induce a conducting channel of low resistivity. If the source-to-drain voltage is increased,
the enhanced channel is depleted of free charge carriers in the area near the drain, and pincho occurs as
in the JFET. Typical drain and transfer characteristics are displayed in Fig. 4-8, where VT 4 V is used
for illustration. Commonly, the manufacturer species VT and a value of pincho current IDon ; the
corresponding value of source-to-gate voltage is VGSon .
iD, mA

iD

LBS = 0

LGS = VGSon

IDon

8V

IDon

7V

6V
5V
LGS = VT = 4 V

10

20

LDS, V

(a)

VT

VGSon

LGS

(b)

Fig. 4-8

The enhancement-mode MOSFET, operating in the pincho region, is described by (4.1) and (4.2) if
Vp0 and IDSS are replaced with VT and IDon , respectively, and if the substrate is shorted to the source,
as in Fig. 4-9(a). Then

2
v
4:6
iD IDon 1 GS
VT
where vGS ! VT .
Although the enhancement-mode MOSFET is the more popular (it is widely used in digital switching circuits), a depletion-mode MOSFET, characterized by a lightly doped channel between heavily
doped source and drain electrode areas, is commercially available that can be operated like the JFET
(see Problem 4.22). However, that device displays a gate-source input impedance several orders of
magnitude smaller than that of the JFET.

4.9.

MOSFET SPICE MODEL

The element specication statement for a MOSFET must explicitly assign a model name (an arbitrary selection of alpha and numeric characters) having the general form
M n1 n2 n3 n4 model name
Nodes n1 ; n2 ; n3 , and n4 belong to the drain, gate, source, and substrate, respectively. Only the nchannel MOSFET is addressed where the device positive voltage and current directions are claried by
Fig. 4-10.

112

CHARACTERISTICS OF FIELD-EFFECT TRANSISTORS AND TRIODES

iD, MA

+ VDD

Drain-feedback
bias line

iL
5

RL
RF
D

ii

DC load line
Problem
4.20

LGS = 8 V

AC load line
Problem 4.21

CC

,V
L gs

[CHAP. 4

Li

_1

5
VT = 4
0

10

15

_ 1.7

(a)

2.5

LDS, V

Lo, V

t
(b)

Fig. 4-9

Fig. 4-10

Format of the .MODEL control statement that must appear in the netlist code for a MOSFET
circuit is as follows:
.MODEL model name NMOS (parameters)
A blank parameter eld results in assignment of default parameter values. Nondefault parameters are
entered in the parameter eld as parameter name value. The specic parameters of concern in this
book are documented by Table 4-3. The SPICE model characterizes the enhancement mode MOSFET
in the pincho region by
iD

IDon
Kp
vGS VT 2
vGS VT 2
2
2
VT

CHAP. 4]

CHARACTERISTICS OF FIELD-EFFECT TRANSISTORS AND TRIODES

113

Table 4-3
Parameter

Description

Default

Units

Vto
Kp
Rd
Rg

Threshold voltage
Transcond. coe.
Drain resistance
Gate resistance

0
2 105
0
0

V
A/V2

Example 4.4. Use SPICE methods to generate (a) the CS drain characteristics and (b) the transfer characteristic
for an n-channel MOSFET that has the parameter values Vto 4 V; Kp 0:0008 A=V2 ; Rd 1
, and Rg 1 k
.
(a) Figure 4-11(a) shows the chosen connection method for measurement of both the drain characteristics and the
transfer characteristic. The netlist code below generates the drain characteristic that has been plotted using the
Probe feature of PSpice as Fig. 4-11(b).

(b)

(c)

Fig. 4-11

114

CHARACTERISTICS OF FIELD-EFFECT TRANSISTORS AND TRIODES

[CHAP. 4

Ex4_4a.CIR - MOSFET drain characteristics

vGS 1 0 0V
vDS 2 0 0V
M 2 1 0 0 NMOSG
.MODEL NMOSG NMOS (Vto=4V Kp=0.0008ApVsq
+ Rd=1ohm Rg=1kohm)
.DC vDS 0V 25V 0.5V vGS 0V 8V 1V
.PROBE
.END

(b) The following netlist code maintains vDS constant to determine the transfer characteristic that is plotted by use
of Probe as Fig. 4-11(c).
Ex4_4b.CIR - MOSFET transfer characteristic
vGS 1 0 0V
vDS 2 0 15V
M 2 1 0 0 NMOSG
.MODEL NMOSG NMOS (Vto=4V Kp=0.0008ApVsq
+ Rd=1ohm Rg=1kohm)
.DC vGS 0V 8V 0.1V
.PROBE
.END

4.10.

MOSFET BIAS AND LOAD LINES

Although the transfer characteristic of the MOSFET diers from that of the JFET [compare Fig. 42(b)] with Figs. 4-8(b) and 4-27], simultaneous solution with the transfer bias line (4.4) allows determination of the gate-source bias VGSQ . Further, graphical procedures in which dc and ac load lines are
constructed on drain characteristics can be utilized with both enhancement-mode and depletion-mode
MOSFETS.
The voltage-divider bias arrangement (Fig. 4-5) is readily applicable to the enhancement-mode
MOSFET; however, since VGSQ and VDSQ are of the same polarity, drain-feedback bias, illustrated in
Fig. 4-9(a), can be utilized to compensate partially for variations in MOSFET characteristics.
Example 4.5. In the amplier of Fig. 4-9(a), VDD 15 V; RL 3 k
, and RF 50 M
. If the MOSFET drain
characteristics are given by Fig. 4-9(b), determine the values of the quiescent quantities.
The dc load line is constructed on Fig. 4-9(b) with vDS intercept of VDD 15 V and iD intercept of
VDD =RL 5 mA.
With gate current negligible (see Section 4.3), no voltage appears across RF , and so
VGS VDS .
The drain-feedback bias line of Fig. 4-9(b) is the locus of all points for which VGS VDS . Since
the Q point must lie on both the dc load line and the drain-feedback bias line, their intersection is the Q point. From
Fig. 4-9(b), IDQ % 2:65 mA and VDSQ VGSQ % 6:90 V.
Example 4.6. The drain-feedback biased amplier of Fig. 4-9(a) has the circuit element values of Example 4.5
except that the MOSFET is characterized by the parameter values of Example 4.4. Apply SPICE methods to
determine the quiescent values.
The netlist code below describes the circuit.