CLA: Carry Look Ahead Adders

Problem: 1) Speed up the process of Addition in Multi-bit Arithmetic Circuits

2) Traditional Methods such as Parallel Adders take a long time in the Propagation of Carry
Bit
Total propagation delay is proportional to the length of the circuit. We Reduce the propagation
delay by reducing the path-Length , that the signals have to travel. E.g. In the case of Full adder , carry
has to be carried out to the next level .By predicting or Pre-computing the carry bit, we can reduce the
propagation delay.
First ,we predict, what would be the carry at each stage and then feeding them to the circuit at the same
time, rather than calculating it at one stage then feeding it into next stage and so on. For that we need
extra hardware, extra piece of logic. One of many techniques to achieve this , is using CLA ( Carry Look
Ahead Adders).
Now lets study the Carry Logic , only then well be able to predict or pre-Compute the carry values at
respective stages:
1) There is a Carry out generated only in four cases, we divide the four cases into 2 parts:
a) Blue : only one of inputs A,B should be 1 provided carry in bit be 1: Logic: (A XOR B)C(in) or;
b) Black : both a and b inputs are 1 irrespective of carry in bit. : Logic: (A AND B)
So C(out) logic is: C(out) = AB + (A XOR B )C(in);

In the C(out) Logic,
1) The term AB is called Carry Generate(g) because , a carry is generated irrespective of C(in), carry of
the previous state. So let g = AB;
2) The term (A Xor B)Cin is called Carry propagate(p) because, a carry of the previous state is
propagated (transmitted )to next stage. And p=A XOR B

Fig. Parallel Adders
Assuming inputs: ai and bi for each step are already known , we can calculate gi and pi at respective
steps;
gi = ai * bi
pi = ai XOR bi
so, the carry out at any stage can be written as : Cin(i) = gi +pi*Cin(i-1) ;
and now we can write:
1) c0 = g0 + p0*c(-1)
2) c1 = g1 + p1*c(0) = g1 + p1g0 + p1 p0 c(-1) .and so on;
now to demonstrate , we feed our pi and gi are fed into the logic circuit whose logic is given above in
1) and 2) and get c0, c1,c2 as an output;

g(n-1) g1 p1 g0 p0 c(-1)
..






P(n-1) C(n-1) . P1 c1 p0 c0


S(n-1) S1 S0
C
CLA: Carry Look Ahead Logic
of c0,c1,c2.and so on.
C(-1)
XOR XOR XOR
So, in the above method , we did not let carry bits to propagate to each level one by one , instead pre-
computed carry at each stage , with the help of CLA, and calculated the sum.
Two disadvantages of this Logic Circuit:
1) No modularity in CLA , that was there in Parallel Adders.
2)Limitations on number of bits ,we can give as an input to CLA ie. And gates used in CLA have limited
Fan out.
Solution: To overcome the problem , we can use more than one CLAs , and the carry outputs from one
CLA will trigger the different CLA to work. i.e take only 4-bit carry look ahead circuits and use them carry
propagation modes.
References :
[1] NPTELHRD : IIT online Lectures
[2] Wikipedia for Figures.
Submitted By:-
Amit Gupta
Btech. (IT)
Bharti Vidyapeeths College of Engg.
Roll_no.: 06011503112