BIOSCIENCE

COURSES AND CERTIFICATE

VLSI
Engineering
ENGINEERING AND TECHNOLOGY
KNOWLEDGE YOU PUT TO WORK
Benets of Studying at UCSC Extension
Learn from experts in the VLSI engineering feld
Practice with real EDA tools used by professionals in the feld
Access labs integrated with lectures
Learn from real-world test cases
Keep up-to-date with the trends in the chip industry
Program Summary
UCSC Extension Silicon Valley
offers the VLSI (Very Large Scale
Integration) Engineering Certicate
Program for professionals working
in the integrated circuit, ASIC,
semiconductor, EDA, device and
system industries. With more than
20 cutting-edge courses, our VLSI
program is the most complete
integrated circuit curriculum available
in Silicon Valley. Students gain
practical experience using the
latest EDA tools on Linux in our
fully upgraded state-of-the-art
VLSI Lab. Our expert faculty teaches
hardware specication, logic
design, verication, synthesis,
physical implementation, circuit
design, testing and manufacturing
integrated circuit products.
ucsc-extension.edu/engineering
Join us for a
FREE Open House
to learn more.
Details inside
Curriculum
Units Course
Design Methodology
Developing the Nanometer ASIC
from Spec to Silicon ....................................2.0 ........3497
Designing Xilinx CPLDs and FPGAs,
Introduction ................................................3.0 ........6346
Logic and Functional Design
Digital Logic Design Using Verilog ..............3.0 ........0764
Logic Synthesis, Introduction ......................3.0 ........4377
Practical DFT Concepts for ASIC:
With Nanometer Test Enhancements ..........3.0 ........5373
IO Concepts and Protocols: PCI Express,
Ethernet, and Fibre Channel........................3.0 ......22177
Digital Design with FPGA ...........................3.0 ......30207
SystemVerilog and Verifcation
Design Simulation with Verilog
and SystemVerilog ......................................3.0 ........6932
SystemVerilog for ASIC & FPGA Design ......3.0 ......20095
SystemVerilog Assertions
and Design Verication ...............................3.0 ......20062
Advanced Verication with
SystemVerilog OOP Testbench ....................3.0 ......18966
Structured Verication Using UVM
(Universal Verication Methodology).......... 2.0 ........0027
Physical Design and Timing Closure
Physical Design Flow from
Netlist to GDS II ............................................3.0 ........4436
ASIC Physical Design, Advanced .................3.0 ........0634
Timing Closure in IC Design ........................3.0 ........4775
Circuit Design
Low-Power Design of Nano-Scale
Digital Circuits ............................................3.0 ......21941
Analog IC Design, Introduction ...................3.0 ........3799
Mixed-Signal IC Design ...............................3.0 ........1999
IO Design Fundamentals .............................3.0 ......30170
PLL and Clock/Data Recovery Circuits .........3.0 ........2283
Designing CMOS Radio Frequency
Integrated Circuits (RFIC) ............................3.0 ......22866
Wireless and Mobile Communications,
Introduction ................................................3.0 ........5455
Jitter Essentials ...........................................1.5 ......21321
Comprehensive Signal
and Power Integrity for
High-Speed Digital Systems ........................3.0 ......22874
Certicate Requirements
To obtain the Certicate in VLSI Engineering,
you must successfully complete a total of 14 units.
Prerequisites
You will need a degree in a technical eld or
equivalent knowledge acquired through training and
experience in hardware design and development.
Experience with UNIX and/or Linux is required for the
lab sessions. Knowledge of a programming language
(e.g., C, Perl or Bash Shell) may be helpful.
Recommended Course Sequence
It is recommended that you take at least one course
from the Design Methodology category. Other
courses can be taken based on your interests and
professional level. For beginners, take Introduction
courses before Advanced.
Note: Some courses may be listed in more than one
program, however, only one course may be shared
between two Engineering and Technology certicate
programs unless otherwise noted.
Program Contact
Engineering and Technology Department,
(408) 861-3860 or e-mail
extensionprogram@ucsc.edu
Advanced Verication with
SystemVerilog OOP Testbench
This course focuses on the use of advanced verication
features in SystemVerilog. You will gain experience
developing an industrial-strength object-oriented
programming (OOP) testbench. The course starts
with building exible testbench components, and
continues with functional coverage to round up
the development of a complete Verication
Environment. The objective is to become familiar
with the exibility of an OOP-centric technique,
the power of constrained random verication
and the use of functional coverage tools to ensure
the success of a verication project. Concepts
introduced in class are reinforced in the lab.
Course 18966
Analog IC Design, Introduction
This course introduces analog IC design fundamentals
including single/multiple-transistor ampliers, current
mirrors, current/voltage reference, output stages,
frequency response, feedback, stability, noise, non-
linearity, and mismatches. Transistor models and
CAD tools for analog design will also be covered.
You will gain a basic understanding of analog IC
design and become familiar with circuit analysis and
simulation tool ow. The fundamentals presented in
the course will prepare you to tackle advanced analog
IC topics such as Op-amp, PLL, ADC and DAC.
Course 3799
ASIC Physical Design, Advanced
This lab-based course covers advanced topics of
ASIC front-to-back design automation. It provides
a 28nm library for you to practice techniques
learned in class. The instructor covers UPF-based
synthesis and placement, and gives an example of
congestion analysis and reduction. You will learn
the CTS and how to optimize timing sign-off.
The course also introduces hierarchical design ow,
power mesh synthesis, and IR drop analysis. The
course further develops your advanced ASIC design
skills with state-of-the-art EDA back-end design
tools and methodology.
Course 0634
Comprehensive Signal and Power Integrity
for High-Speed Digital Systems
This course covers signal and power integrity analysis
of high-speed digital systems, and the modeling and
design techniques used in high-speed links (in board,
package, and connector). The instructor introduces IO
modeling including IBIS, behavioral, functional, and
ESD. Also explained are signaling techniques such as
VLSI Engineering Certicate
Copyright 2013 The Regents of the University of California. All rights reserved.
Enrollment Information
Visit ucsc-extension.edu/engineering for
the most up-to-date information about our
courses and programs, including textbooks,
instructors, schedules and locations.
Enroll online at ucsc-extension.edu.
differential, NRZ, pulse, and multi-level, as well as
simulation methods. You will learn the fundamental
concepts in equalization design. At the system level,
topics include clocking schemes such as PLL, DLL and
CDR; timing jitter analysis; and power analysis topics
such as IR drop, AC noise, simultaneous switching
noise and decoupling capacitor.
Course 22874
Design Simulation with Verilog
and SystemVerilog
This course covers basic Verilog language.
It introduces the digital simulation process with
hands-on exercises using the simulation tool
in the lab. Discussions cover simulation techniques
such as coding style, event ordering, delta cycle
debugging, zero width glitch, race conditions,
time slices, conditional compilation, simulation
performance and code coverage. The second half
of the course introduces the System-Verilog
language including syntax and semantics.
Course 6932
Designing CMOS Radio Frequency
Integrated Circuits (RFIC)
This course addresses both the theoretical and
practical aspects of CMOS RFIC circuit design.
The course begins with a review of the CMOS
transistor model and RLC network. It introduces
the concepts of impedance matching, two-port
noise, and linearity. The instructor provides in-depth
explanations of the design and analysis of low-noise
ampliers, mixers, voltage-controlled oscillators,
synthesizers, and power ampliers. To reinforce
the skills learned in the course, you will develop
your own design for major wireless transceiver
blocks. The course also includes discussion of the
design trade-offs in various radio architectures.
Course 22866
Designing Xilinx CPLDs and FPGAs,
Introduction
This course is a practical introduction to programmable
logic design with Xilinx FPGAs and CPLDs. Using several
examples and design techniques, you will be taken
through a complete PLD design. Upon completion
of the course, you will be able to complete a design
with Xilinx CPLDs and FPGAs, and understand the
design and timing reports. The course will include two
student projects. Topics include a logic design process
review, design software, Xilinx CPLDs and FPGAs
architecture, design techniques and optimizing, JTAG,
power optimization and large design techniques.
Course 6346
Developing the Nanometer ASIC:
From Spec to Silicon
This course covers each step in developing an ASIC,
explaining in an intuitive and visual manner such
key concepts as transistor action, standard cells, RTL
synthesis, meeting timing, functional coverage, formal
equivalence, physical design, signal integrity, DFT and
BIST, tape-out, IC fabrication, and emerging packaging
trends. The course includes hands-on quick tour labs
to familiarize you with the use of EDA tools. The focus
is on mostly-digital ASICs with multiple IP cores, low-
power goals, and on-chip RF-CMOS/analog blocks.
Course 3497
Digital Design with FPGA
This course provides the knowledge and hands-on
experience needed to design digital logic blocks in
FPGA. The course introduces how to build designs
in FPGA and covers specic designs of various digital
blocks. Starting from combinational logic, look-up
tables, carry chains, and multiplexers, you will learn
to design arithmetic and comparator functions using
FPGA and then you will test them. The instructor then
explains various sequential ops, fast counters and
shift register look-up. The course also explores the
embedded RAM, ROM and nite state machine
designs using Xilinx architecture.
Course 30207
Digital Logic Design Using Verilog
This course will prepare you to implement Verilog
modeling of digital logic. You will learn Verilog
constructs and hardware modeling techniques. The
course covers Verilog language elements and data
types. You will tackle key challenges and learn
structural, dataow and behavioral modeling in
Verilog, including common constructs and coding
considerations. Instruction in the coding and testing
of digital logic includes examples of combinational
circuits (gates, mux/demux, encoders/decoders, and
Boolean expression), sequential circuits (latches,
ip-ops, shift registers, counters, RAMs and ROMs),
and complex logic (avors of ALU and FSM).
Course 0764
IO Concepts and Protocols:
PCI Express, Ethernet, and Fibre Channel
This course focuses on IO technologies and walks
students through the complexities of IO subsystems
in modern computers, and the networking and
storage subsystems to which they are attached.
After an introduction to the basic concepts of IO,
the course covers PCI Express, Ethernet and
Fibre Channel. Discussion will include operation
and protocols and an exploration of how these
technologies work. You will follow an applications
IO request all the way from the system call, to
when the data actually makes it out of the wire.
Course 22177
IO Design Fundamentals
This course is an introduction to IO interfacing at chip
and board levels. It covers the advantages and disad-
vantages of TTL, CMOS, low-voltage CMOS, LVDS and
optical interfaces. The course emphasizes fundamental
concepts such as transmission line analysis, slew rate
and termination. It introduces basic IO logic, timing
analysis and package models. You will learn about
bit error rate, bi-directional IO and decision feedback
lters. Because most solutions are silicon-based, ESD
concepts and techniques will also be discussed.
Course 30170
Jitter Essentials
Learn the denitions of various types of jitter
(including phase noise), understand which type
of jitter is important to your application and why,
plus learn how to propagate jitter through a system,
create jitter budgets, measure and minimize jitter,
and more. Emphasis will be placed on developing
a working knowledge of jitter, such as establishing
a common language, understanding jitter beyond
the denitions, gaining insight by making simplifying
assumptions, and visualizing relationships between
different types of jitter.
Course 21321
Embedded Systems and VLSI Open House
Join us for a FREE Open House to learn about two of our most popular certicate programs. The VLSI Engineering Certicate Program is for
professionals working in the integrated circuit, ASIC, semiconductor, EDA, device and system industries in Silicon Valley. The Embedded Systems
Certicate Program is for professionals working in the hardware and system design elds, with courses in system design, embedded programming,
real-time systems, and DSP/DV. Presenters will discuss new developments in both elds and how these courses can help you break into new elds
and advance your career.
Course 20544 and 22403
For information and to register, visit ucsc-extension.edu/events.
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Logic Synthesis, Introduction
This course outlines various concepts of logic
synthesis. Starting with the basics of synthesis,
the course explains the Synopsys tools and their
use in synthesizing high-level language into gates.
It also covers various options such as partitioning,
design, gate-level optimization, time/area constraints
and library management. The course is intended for
design engineers with some knowledge of hardware
description languages such as Verilog HDL or VHDL.
It is a lab-based course with hands-on exercises.
Course 4377
Low-Power Design of
Nano-Scale Digital Circuits
This course introduces advanced topics in nano-scale
(below 90nm) VLSI device and circuit design. High-
performance and low-power design issues in modern
and future nano-scale CMOS technologies are
discussed in detail. You will learn low-power
design approaches and techniques at different
levels of abstraction. New design techniques will be
introduced to deal with nano circuit designs under
excessive leakage and process variations. Several
non-classical CMOS devices for circuit design in such
technologies will be explored. Prospects of future
non-silicon nanotechnologies will be reviewed.
Course 21941
Mixed-Signal IC Design
This course will help you understand basic analog
circuits and systems, and problems encountered
when analog circuits share substrate with digital
circuits. You will also learn precautionary measures
and techniques used to circumvent these problems.
Topics include MOS transistors, basic analog building
blocks, phase-locked-loop circuits, sample and hold
circuits, comparator design, A/D and D/A converters,
and layout considerations in mixed-signal circuits.
The course is intended for practicing engineers and
design managers who want to understand analog
circuit and layout techniques in mixed-signal IC design.
Course 1999
Physical Design Flow from Netlist to GDS-II
This course is an introduction to ASIC physical design
ow and tools from netlist to GDS-II. The course
starts with oor planning and block pin assignment.
The instructor then addresses placement and clock-
tree synthesis, followed by routing, and post-route
optimization. You will learn RC extraction, static timing
analysis, and physical verication. Upon completion
of the course, you will possess the essential knowledge
and hands-on experience with the back-end physical
design ows, from a synthesized netlist all the way
to layout completion for ASIC chip tapeout.
Course 4436
PLL and Clock/Data Recovery Circuits
Phase-locked-loop (PLL) circuits are used extensively in
system and chip designs for frequency multiplication,
data extraction, and re-timing purposes. This course
provides the knowledge required for analysis and
design of PLL circuits and their applications in clock
and data-recovery circuits. The instructor will discuss
various components involved in the design of a PLL
circuit. Topics include transceiver design, high-speed
I/O, ring and LC oscillators, charge-pump PLL, practical
issues at transistor-level design, noise and jitter in PLL,
delay-locked loop, frequency multiplier, and clock
and data recovery circuits.
Course 2283
Practical DFT Concepts for ASICs:
With Nanometer Test Enhancements
This hands-on course is ideal for IC designers seeking
a deeper understanding of test issues and test
engineers wanting to stay current with emerging
trends and tools. You will gain hands-on experience
building scan chains and generating test patterns
using Synopsys DFT Compiler (DFTC) and TetraMAX
ATPG. Advanced topics include building multiple
scan-chain insertion, employing sequential ATPG,
optimizing DFT logic, and understanding LBIST and
MBIST. By the end of the course, you will be able
to hand off a full-scan design and generate a high-
coverage test program for nanometer ASIC.
Course 5373
Structured Verication Using UVM
(Universal Verication Methodology)
This ve-week course covers structured verication
development using the Universal Verication
Methodology (UVM) environment. It begins with an
overview of UVMs basic building blocks, followed
by an examination of the components and trans-
actions they use to communicate. Test and component
creation and sequence generation will be discussed
and reviewed. You will learn the effectiveness of
modular and encapsulated, ready-to-use and
congurable verication environments. Concepts
introduced in class are reinforced in the lab with
a real-world design project.
Course 0027
SystemVerilog Assertions
and Formal Verication
This course rst introduces SystemVerilog Assertion
(SVA) concepts and syntax, using both small examples
and a realistic design. It covers the OVL checker library,
writing and debugging assertions. The second part
of the course introduces formal verication theory
and tool. The course covers FV application in
several design stages and in different functional
areas such as SoC connectivity, coverage closure,
and x-propagation checks. The course addresses
key topics in detail, from language constructs to
assertion coding guidelines with practical examples
of how to use assertions in verication.
Course 20062
SystemVerilog for ASIC and FPGA Design
This course prepares hardware engineers, ASIC
and FPGA designers, and design-support staff to
use the high-level syntax of SystemVerilog to design,
debug, and synthesize digital logic for ASICs, FPGAs,
and IP cores. You will learn SystemVerilogs basic
building blocks and language constructs, including
synthesizable data types and operators, structures
and unions, 2-D arrays and loops, and the bus
interface unit. In lab sessions, you will write code
and synthesize it into digital logic and bus fabric,
using both ASIC and FPGA tools.
Course 20095
Timing Closure in IC Design
This lab course begins with basic timing concepts
and STA methodology. You will learn what needs to
be timed and how to setup a run for STA. The course
exposes students to constraints, exceptions and
what if analysis. It also explains how to address
timing violations in ECO mode. Nanotechnology
topics including noise analysis, prevention and
on-chip variations are covered. The instructor shares
practical experiences meeting timing closure, budget-
ing and debugging. The course uses primetime tools
and test cases for hands-on practical experience.
Course 4775
Wireless and Mobile Communications,
Introduction
This course builds an understanding of the various
wireless standards and techniques in use today. The
course begins with a review of traditional amplitude
modulation (AM), frequency modulation (FM), and
single sideband (SSB). After covering the foundation
technologies, present day digital modulation schemes
are analyzed, including OFDM, TDMA and CDMA.
The course covers the current wireless standards,
including, but not limited to, IS-136, IS-95, Bluetooth,
3G, 4G, 802.11, and LTE. Additional discussions
address antenna and transceiver design principles
and implementation in todays mobile devices.
Course 5455
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