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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011

Highly Integrated and Tunable RF Front Ends for

Reconfigurable Multiband Transceivers: A Tutorial
Hooman Darabi, Ahmad Mirzaei, and Mohyee Mikhemar

AbstractArchitectural and circuit techniques to integrate the

RF front end passive components, namely the SAW filters and duplexers that are traditionally implemented off chip, are presented.
Intended for software-defined and cognitive radio platforms,
tunable high-Q filters realized by CMOS switches and linear or
MOS capacitors allow the integration of highly reconfigurable
transceiver front ends that are robust to in-band and out-of-band
blockers. Furthermore, duplexer techniques based on electrical
balance concepts are introduced to enable highly integrated and
programmable radios for full-duplex applications such as 3/4G
transceivers. Several case studies are presented that offer highly
linear and low-noise transceiver front ends that satisfy the challenging requirements of cellular standards, yet offer considerably
lower cost and size compared to the state-of-the-art transceivers
available today.

Fig. 1. (a) Ideal SDR. (b) A more practical architecture.

Index TermsCellular, duplexers, EDGE, electrical balance, filters, frequency division duplexing, frequency selectivity, front end,
GSM, passive, quality factor, SAW filters, software-defined radios,
WCDMA.

I. INTRODUCTION

HE RECENT demand on instant and wideband access

to information and communication requires a mobile
terminal that is capable of delivering the ultimate user experience. One realization is a software-defined radio (SDR)
[1][3], [47], which is a highly programmable device that is
reconfigured through software to operate over a wide range
of carrier frequencies and channel bandwidths. If designed
properly, the SDR is capable of transforming itself, satisfying
the requirements of any specified standard at competitive power
consumption, size, and flexibility. One common example
of the SDR is 3G cell phones, which allow as many as 17
bands in three modes of operation, that is, GSM, EDGE, and
WCDMA/HSPA.
The first SDR architecture was proposed by Mitola [1], in
which the RF and analog processing are reduced to only a pair
of data converters, as shown in Fig. 1(a), thus providing the
maximum flexibility and programmability through the digital
processing block. This idealistic approach however, suffers
from a fundamental limitation; that is, the poor tolerance of
such a radio to the interferers. Shown in Fig. 2, in many wireless
applications, a small desired signal could be accompanied by
Manuscript received March 01, 2011; revised April 22, 2011; accepted June
30, 2011. Date of current version September 14, 2011. This paper was recommended by Associate Editor H. Luong.
The authors are with the Broadcom Corporation, Irvine CA 92617 USA
(e-mail: hdarabi@broadcom.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2011.2162460

Fig. 2. Blockers in wireless environments.

several large in-band (created due to nearby transmitters of

the same communication standard), or out-of-band blockers
(caused by any transmitter). At times, these blockers could be
as much as about 100 dB larger than the desirable received
signal, which, due to the lack of any filtering in the SDR of
Fig. 1(a), would demand an impractical dynamic range of about
100 dB on the ADC. According to the survey published in [4],
this demand leads to an unacceptable power dissipation of 2
kW estimated for the ADC! That is three orders of magnitudes
higher than what a cellular power amplifier (PA) could consume. Thus, a more practical receiver architecture shown in
Fig. 1(b) is adopted in most SDRs today [3], [47], where, by
means of downconversion, a considerable portion of analog
and digital signal processing is performed at a conveniently
lower intermediate frequency (IF). The difference from the
other traditional radios is the added programmability in almost
everything, including channel-select filter bandwidth or ADC
sample rate to allow several modes of operation, as well as
extended RF bandwidth of the transceiver front end and PLL
range to support multiple bands.
Even though the architecture of Fig. 1(b) solves the in-band
blocker problem through programmable IF filtering, the out-ofband blockers remain a challenge. In the case of GSM for example, a 0 dBm out-of-band blocker can heavily compress the
receiver front end (explained more in Section II and Fig. 3), and
thus desensitize it. Therefore, an additional front-end filter is
needed to suppress the blocker adequately [Fig. 1(b)] before

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DARABI et al.: HIGHLY INTEGRATED AND TUNABLE RF FRONT ENDS

the large gain of the low noise amplifier (LNA) occurs. The
filter typically requires a narrow bandwidth set by a given application and a very sharp stop-band. Consequently, due to its
very high-quality nature, it is typically implemented externally,
which adds considerably to the cost and size of the reference
design.
Moreover, because the filter bandwidth and center frequency
are inevitably not programmable, for every band or mode of operation, a dedicated input and its corresponding filter are needed.
These items further add to the cost, and more importantly, oppose the promise of maximum hardware sharing offered by the
SDR architecture shown in Fig. 1(b). This circumstance continues to be one of the greatest obstacles to realizing true software-defined radios.
In this paper, we introduce several circuit techniques to address this great challenge, enabling highly programmable and
tunable front-end filters and duplexers integrated along with the
rest of the CMOS RF IC. The paper is organized as follows:
Section II provides more details of system level requirements of
the radio front end. The main focus is on cellular applications,
which are the most challenging realization of SDR. Sections III
and IV are dedicated to 2G and 3G receivers, followed by a
discussion of transmitters in Section V. Duplexer techniques
are described in Section VI, and conclusions are presented in
Section VII.
II. FRONT-END INTEGRATION CHALLENGES AND SYSTEM
REQUIREMENTS
In this section, we discuss the challenges and high-level requirements of the integration of the SAW filters for 2/3G transceivers. Because cellular is the most demanding wireless standard with regard to filtering, we mostly focus on that.
As shown in Fig. 3, in a GSM receiver, a weak desirable signal
dBm or 2.5 V) and
3 dB above the reference sensitivity (
as close as 20/80 MHz to the desirable signal at the edge of the
band is specified for low/high band cases, to be accompanied by
very large in-band and out-of-band blockers (as large as 0 dBm).
Thus, for the case of a GSM/EDGE receiver, the main requirement arises from the radio tolerance to the 0 dBm blocker. The
blocker is a static sine wave and imposes only compression issues.
Knowing that the in-band blockers (subject to almost no RF
dBm at 3 MHz away (Fig. 3), the
filtering) are as large as
RF filter needs to provide at least 23 dB (approximately) of attenuation on the out-of-band blocker to reduce it to the level that
the RX front end can handle. If realized by inductors and capacitors, the corresponding quality factor (Q) would be greater than
100, thus making it impractical to be realized on-chip, and especially in a regular bulk CMOS process.
dBm is speciNote that even though a sensitivity of
fied in the standard, most advanced handsets today target for
dBm sensitivity or better, which translates to a total noise
figure of 5 dB for the entire system (assuming 200 kHz bandwidth and 5 dB signal-to-noise ratio or SNR). With a 1 dB loss
budget for the switch and 1.5 dB for the SAW filter, the receiver noise figure must be about 2.5 dB. On the other hand,
a SAW-less receiver can enjoy a higher noise figure of 4 dB to

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Fig. 3. GSM out-of-band blocker profile.

Fig. 4. GSM Noise requirement in RX band.

Fig. 5. Direct-conversion TX versus translational loop.

achieve the same sensitivity as the 1.5 dB loss of the filter is

eliminated.
dBm
For a GSM transmitter, an output noise of less than
(measured at a 100 kHz resolution bandwidth at the corresponding receive-band) is needed to ensure that the nearby
receiver is not desensitized by the other handset transmitting at
full power (Fig. 4). Given that the edge of the RX band starts at
20 MHz away for low bands, the required system phase noise
dBm output power is
at
dBm

kHz

dBm

Excluding the PA noise (which is typically

dBm and
dBm worst case), the radio contribution must
better than
be less than
dBc Hz at 20 MHz. To meet this challenging
requirement without any external filtering, the GSM transmitters traditionally have been using translational loops [5], [7] or
direct modulated PLLs [6], [8], [9], [36], which could be extended to a polar scheme in the case of EDGE [7][12], [36],
[41][44] that supports 8PSK modulation (see Fig. 5). The advantage of these architectures is that the noise of the IQ modulator [39] (a substantial noise contributor) is eliminated. In the
case of a translational loop for instance, the PLL forces the VCO
output to be a replica of the modulated input spectrum fed to
the phase frequency detector (PFD), thus translating the intermediate frequency (IF) spectrum to radio frequency (RF). Here,
unlike the direct-conversion case, only the VCO and LO chain
contribute to the far-out noise (the PLL bandwidth is usually
narrow enough to suppress the noise of the rest of the loop).
Moreover, because the VCO and PA output have exactly the
same phase content, this type of transmitter is more immune to
pulling.

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Fig. 7. Examples of (a) current and (b) future 3G radios.

Fig. 6. 3G Full-duplex issue.

For the case of 3G radios, the problem arises from the full-duplex nature of the system, that is, the simultaneous operation of
the RX and TX (Fig. 6). Ideally, an external duplexer realized
by two highly selective filters separates the receive and transmit
signals, but in practice, due to the finite isolation of the duplexer,
some of the strong TX signals leak to the RX input, causing two
issues: First, the TX noise falling in the RX band effectively degrades the receive noise figure. Second, when mixed by a large
out-of-band blocker (for example the blocker at half-duplex frequency) due to the front-end third-order nonlinearity the RX is
desensitized. To overcome these issues, external filters are traditionally placed at the TX and RX ports to suppress the TX
noise and leakage, thus relaxing the phase noise and linearity
requirements of the transceiver. In the case of the transmitter
output, the SAW filter relaxes the noise requirement of the TX
chain by providing some filtering, whereas the receiver SAW
filter attenuates the TX residual leakage and any other blocker,
thereby relaxing the linearity requirements of the RX chain.
Similar concerns exist in the case of the long term evolution (LTE) standard. For the LTE standard, the out-of-band filtering requirements are the same as those required for 2G and
dBm, which is the worst case for LTE, is still the
3G (
dominant requirement for GSM). Due to the wider bandwidth,
however, the in-band blocking requirement for LTE is more
stringent. This requirement, however, mainly imposes greater
challenges on the integrated channel-select filter design, not the
RF front end. Note that similar to 3G, LTE must support the
FDD option as well. For other shorter-range standards [wireless
personal area network (WPAN) or wireless local area network
(WLAN)] the blocking requirements are far less stringent. For
example, in Bluetooth applications, the out-of-band blockers are
dBm (from 02 GHz, and
GHz), as opspecified to be
posed to 0 dBm in the case of GSM. The recent demand for
integrating WPAN and WLAN devices with cell phones does
impose more challenging blocking requirements, however, because of the large TX signal of the cellular device coupling with
the other embedded devices (although the cellular device still
has the most stringent in-band/out-of-band blocking requirements).
For these reasons, current cellular platforms use several external filters and duplexers to alleviate noise, compression, and
linearity issues imposed by either the blockers or the TX leakage

from the cellular radio itself. An example of a quad-band GSM/

EDGE tri-band WCDMA radio is shown in Fig. 7(a), where as
many as 10 SAW filters, three duplexers, and several matching
components are needed.
Besides the obvious size and substantial cost implications,
this front-end partitioning is contrary to the hardware sharing
concept provided in SDRs. The goal of this paper is to introduce
techniques to eliminate these external passives, introducing a
single-input 3G SDR with all external components integrated
[Fig. 7(b)].
III. 2G RECEIVER SAW ELIMINATION
As previously stated, the GSM receive filter needs to suppress the out-of-band blocker at 80 MHz away by about 23 dB
or more, with a 60 MHz passband for the PCS band (see Fig. 3).
The low band has a bandwidth of 35 MHz, but a more stringent stop band of 20 MHz away. If such a filter is to be realized by an LC structure, the very high Q of the inductor needed
will inevitably require Q enhancement techniques, which have
proven to be insufficient to meet the stringent GSM noise and
linearity requirements [13][15]. Moreover, the high Q nature
of the filter inevitably makes it very sensitive to small variations in the values of the capacitors and inductors if implemented on-chip. In this section, we discuss several other ideas
proposed recently to eliminate the front-end SAW filters and
provide several case studies. Of the few techniques described,
the N-path filtering (Section III-C) followed by linear-LNA receivers (Section III-F) seem to be the most promising in the realization of true SAW-less GSM receivers while the feedforward
(Section III-B) and mixer-first (Section III-A) may not be as attractive for the cellular applications.
A. Mixer-First Receivers
As shown in Fig. 8, one simple and basic way of enhancing
the receiver linearity is to eliminate the low noise amplifier,
thus reducing the gain in front of the downconversion mixers
that are typically the bottleneck. Recently, mixer-first (also
known as LNA-less) receivers proposed in [16], [17] have
shown promising linearity due to the lack of the high gain of the
LNA upfront, but as expected, still somewhat short on the noise
figure (NF). Note that a SAW-less GSM receiver can tolerate a
more relaxed NF of about 4 dB, as derived in Section II. Still,
removing the LNA will inevitably degrade the noise figure,
unless much higher current is burned in the mixer buffer and the
LO chain. In addition to that, using large switches (as required

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Fig. 8. Mixer-first receiver front end.

Fig. 10. Actual realization of feedforward filter.

Fig. 9. Feedforward blocker cancellation concept.

Fig. 11. FF filter response compared to EPCOS SAW.

to improve noise figure) directly connected to the receiver input

causes a potentially large LO-to-RF feed-through.
Moreover, the harmonic mixing remains a challenge, as the
LNA-less receiver is quite wideband and provides little filtering
at LO harmonics, although the 8-phase mixing scheme in [17]
substantially helps at the expense of increasing the LO chain
power consumption. Fig. 8 shows an example of a single-ended
8-phase design that inherently removes the
and
blockers, although in practice is limited by the mismatches in
the LO phase-generation path.
B. Feedforward Blocker Cancellation
Another approach proposed in [18] keeps the LNA so as not
to compromise the NF at the sensitivity level and relies on feedforward (FF) cancellation of the blocker at the LNA output, as
illustrated in Fig. 9. A similar approach is also demonstrated in
[51] and [52], while we focus on the architecture proposed in
[18] to provide a case study. The features and properties of the
two feedforward examples ([18], [51], and [54]) are very similar.
To distinguish the blocker from the desirable signal, a sharp
notch filter in the feedforward path is required. This is realized
by a frequency translational loop where the low-Q high-pass
filter (HPF) response appears at RF through subsequent down
and up conversion by the same receive LO signal. This leads
to a very sharp RF filter whose center frequency is precisely
controlled by the LO and whose bandwidth is conveniently set
by the low-Q low-frequency HPF (Fig. 9).

Since IQ LO signals are available, the actual filter realization

is shown in Fig. 10 where the feedforward path resembles a
linear time-invariant system whose impulse response is:
, where h(t) is the original HPF response (the
).
BB response translated to
The feed-through of the LO signals to the receiver input is a
potential concern similar to mixer-first approach. In this case
however, due to much better isolation between the LO ports
and the input, the measured LO feed-through is well below the
dBm requirement.
Despite a better NF of 4.2 dB achieved here [18] compared
to the LNA-less approach, this scheme suffers from two issues:
1. The lack of any input filtering imposes relatively challenging linearity on the LNA input devices, thus compromising the NF, limiting it to 4 dB.
2. The inevitable phase and gain mismatch between the main
and FF paths limit the amount of filtering to about low
20 dB as shown in Fig. 11 (black curve). Although this
value is marginally adequate and comparable to a commercial external filters worst case, a higher rejection is helpful.
The latter issue can be alleviated by using adaptation techniques to improve matching at the expense of complexity.
C. N-Path Filtering
Inspired by N-path filtering concept introduced in 1960 [19]
and subsequently used in switched capacitor (SC) filters in early

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Fig. 12. N-path filtering concept.

Fig. 14. Realization of M-path filtering.

Fig. 15. SAW-less SoC die photo.

Fig. 13. Implementation of 4-path filter.

1980s [20], we realized the following alternative approach. Consider the low-pass SC filter of Fig. 12, where a sampling freis applied. Due to the Nyquist limit (NY), the maxquency of
, leaving only one replica of
imum allowable frequency is
the low-pass response. Now assume we have N replicas of the
th of a period rotating clocksame filter, each turning on at
wise. It can be shown [20] that now the Nyquist limit is extended
by N times, allowing other replicas of the filter response, particularly the one at , to be extracted.
An example of a 4-path realization is shown in Fig. 13. It
can be shown [21] that, as expected, base-band impedance of
is translated to
, in series with the switch resistance,
, where
is the 4-phase clock frequency applied to the
switches as illustrated in Fig. 13.
To extend the flat region and improve the stop-band rejection,
it is crucial to minimize the switch resistance with respect to the
parasitic impedance at the input of the filter. For typical values
of switch sizes and RF parasitics, a stop-band rejection of up to
20 dB is feasible with one stage of filtering.
Shown in Fig. 14 is the actual circuit implementation of the
4-phase filter, where to minimize noise and linearity, the baseis simply reduced to a capacitor
.
band impedance
For applications with wider channel bandwidth, the baseband
impedance may be replaced by a parallel RC.
The BPF is implemented differentially to make it robust
to common-mode noise. In GSM low bands, the out-of-band
blockers can be as close as 20 MHz to the desired signal. Thus,
,
to determine the minimum size of the baseband capacitor

the impedance must be low enough to adequately attenuate

the blocker without causing any gain compression. It must be
emphasized that the switches of the BPF carry no dc current,
and thus their noise contribution is minimal. Additionally, a
good linearity of the proposed high-Q BPF is guaranteed, due
to the low-resistance switches offered in submicron CMOS
technologies.
For the proof of concept, a quad-band GSM/GPRS/EDGE
receiver (as part of a 2.5G SoC) with integrated front-end SAW
filters is fabricated [22], [48]. The SoC die photo is shown in
Fig. 15 (the radio is at the upper-left corner). The radio core
occupies about 5 mm in 65 nm CMOS.
Illustrated in Fig. 16 is the SAW-less receiver front-end
circuitry. An on-chip balun converts the single-ended receiver
input from the antenna switch to a differential signal to drive the
inputs of a differential LNA. The secondary of the transformer
of
is tuned to the desired band, and it ensures a measured
dB seen from the input of the RF IC across a
less than
wide range of 1.72 GHz for high bands and 0.81 GHz for low
bands. This single-ended-to-differential conversion provides a
voltage gain of close to 9 dB as well, resulting in a simulated
receiver noise figure of 2.8 dB. The LNA is a common-source
cascode amplifier, loaded by a differential tuned inductor. To
prevent the saturation of the LNA input devices by the 0 dBm
blocker, an on-chip differential high-Q BPF (the same as the
one shown in Fig. 14) is placed at the inputs. This BPF provides
low-input impedance to far-out blockers without impacting the
desired signal, causing the blockers to be attenuated at this
stage before hitting the LNA.
At this point, the attenuation that the blockers have experienced is not enough to cause any significant gain compression

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2043

Fig. 17. The impact of phase noise.

Fig. 16. Front-end circuit with high-Q filters.

or intermodulation at the input devices of the LNA. This attenuation, however, is not sufficient for 0 dBm blockers at a
20 MHz offset, which is required for low band. Therefore, a
second high-Q BPF is used at the inputs of the cascode devices.
This additional filtering guarantees that the attenuated blockers
do not cause large swings at the LNA output, although the desired signal experiences the intended amplification by the LNA.
Furthermore, the downconversion current-driven passive mixer,
along with the low-pass response of the transimpedance amplifier, is used as the third high-Q BPF. For this purpose, the
switches of the passive mixer must be driven by the same 25%
duty-cycle signal that clock the two other high-Q BPFs. Before
we present the measured results, we briefly discuss some of nonideal effects associated with the proposed filtering technique.
D. N-Path Filtering Nonideal Effects
Despite the simplicity of the filter, there are several factors
that must be carefully considered because they can potentially
impact the RX performance. As shown in Fig. 17, a noisy
LO signal driving the switches reciprocally downconverts
the blocker on the top of the desirable signal. Depending
on whether the phase-noise components between four LO
are common-mode or differential,
clocks
the downconverted noise components can have various phase
relationships among themselves. To summarize, each capacitor
holds three types of voltages: 1) the downconverted desired
signal at around dc; 2) the downconverted and attenuated
; and 3) the reciprocally downconverted
blocker at
blocker by the LO phase-noise, which is at dc as well. Looking
back from the RF, the first two types are upconverted to the RF
and eventually create RF voltages at the desired and blocker
frequencies, respectively. The third type of capacitor voltages,
however, which are emerged from the LO phase-noise, appear
as an RF noise voltage at around LO, which degrade the receiver
noise figure.
The exact phase noise analysis of the filter is quite cumbersome and beyond the scope of this paper. Due to its importance, however, we summarize the final outcome as follows:
For a 0 dBm blocker at a 20 MHz offset, a phase noise of
dBc Hz is shown to create an input-referred noise floor of
dBm Hz, assuming everything else is ideal. This noise

floor corresponds to a blocker NF of 6.5 dB, which is adequately

below the 15 dB target needed to meet 3GPP [36]. This condition is clearly more stringent than the phase-noise requiredBc at 3 MHz and
ment of a conventional GSM receiver (
above), and thus the VCO and RX-LO chain are designed properly to achieve this target.
Another concern arises from the second-order nonlinearity of
the switches. As shown in Fig. 18, assume the switch voltage
has a second-order relation with respect to its current, which is
. It can be shown that with
given as
the switches matched, an amplitude-modulated blocker current
fed to the filter input only creates
of
, which subsequently
a voltage component proportional to
at baseband, causing no issue. A
downconverts to around
mismatch of
among the switches, however, creates an RF
, where S(t) is 1 when LO is high,
voltage of
and is 0 when LO is low. This component can now downconvert
on the top of the desirable signal, and hence the switches mismatches must be reduced by proper layout techniques. Moreover, the switch 2nd order nonlinearity must be lowered by applying a sharp LO voltage [53]. It can be shown that by exploiting common good design and layout techniques, the 2nd
order nonlinearity should not be a major issue for most cases,
including GSM.
The impact of quadrature errors in LO signals driving the
creates a proswitches is shown in Fig. 19. A mismatch of
portional image component on the opposite side of the desirable
RF voltage, as expected. This component is downconverted,
along with the RF signal, falling on top of each other at baseband, and naturally degrading the SNR. In the case of GSM/
EDGE, a relatively low SNR is needed (about 20 dB for MCS9
EDGE mode which is the most stringent case), thus making the
filter immune to IQ mismatches. Nonetheless, common design
and layout techniques must be used to minimize that.
Similar to LNA-less receivers, the LO harmonic mixing is a
potential issue here, although the relatively narrow bandwidth
of the tuned loads at the LNA input/outputs helps considerably.
dB is achieved at
,
In this prototype, a rejection of
which requires only an additional 20 dB of filtering upfront. This
blocker revalue can be easily achieved, given that the
sides at a far frequency of 6 GHz. Alternatively, at the expense of
extra power consumption on VCO and the LO path, an M-phase

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Fig. 20. M-phase filter to suppress harmonic mixing issue.

Fig. 18. Second-order nonlinearity in the 4-phase filter.

Fig. 21. (a) Measured noise figure at the LNA input. (b) Measured PCS band
sensitivity at the antenna.

Fig. 19. Impact of IQ mismatch.

structure (Fig. 20) (M equal to 8, for instance), may be adopted,

(14 GHz in
which puts the closest harmonic at
). This would be desirable for the SDRs using
the case of
wide-band LNAs.
E. Prototype RX Measured Results
The prototype receiver is fabricated in the 65 nm CMOS
process, as a part of a GSM/GPRS/EDGE SoC [22]. The RF
front end provides 78 dB of gain, and the receiver noise figure
measured across all received channels and bands is shown in
Fig. 21(a), which is 3.1 dB. This value is about 0.5 dB higher
than the noise figure for a typical cellular receiver [7][9], [11],
however. Because the SAW filters add an additional loss of
1.52 dB, the overall noise figure of the system is 1 dB better,
as also discussed in Section II. The corresponding measured
voice sensitivity is close to
dBm [Fig. 21(b)], which as expected, is 1 dB better than similar radios with an external SAW
filter. Note that the filters are nominally disabled and need to
turn on only for the infrequent event of receiving a large out-ofband blocker, which is detected through a wideband RSSI.

Fig. 22. Receiver measure blocker noise figure and compression.

The NF performance of the receiver versus the blocker power

MHz and
MHz offsets for the PCS band is shown in
at
MHz compresses the receiver
Fig. 22. A 0 dBm blocker at
gain by 0.8 dB, and the measured blocker NF is 11.4 dB, which
is well below the 15 dB requirement of 3GPP. For a blocker at
MHz, a
dBm blocker compresses the RX
an offset of
gain by 0.3 dB and results in a measured NF of 10.9 dB, which
again, is well below the target value. All other bands satisfy the
requirements as well, and only the more challenging PCS band
is shown here as an example. The platform BER measurements
with baseband running further indicate that the receiver meets
the requirements with a 0 dBm blocker present at the input,
which agrees with the device measurements shown in Fig. 22.
F. SAW-Less Receivers With Linear LNA
A variation of the N-path filtering receiver described in
Section III-C has been recently introduced as an alternative

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TABLE I
SUMMARY OF SAW-LESS RECEIVER APPROACHES

[49], [50] to the multi-stage filtering scheme shown in Fig. 16.

The design features a highly linear LNA, with high supply
voltage to improve the blocker handling, followed by either a
voltage-mode [49] or current-mode passive mixer that provide
the high-Q filtering. The linear LNA enables elimination of the
first two stages of high filters as shown in Fig. 16, but comes at
the expense of somewhat higher power dissipation.
In summary, all three N-path based topologies [48][50]
achieve similar noise figure and blocking performance, though
[48] seems to be somewhat lower power as expected. Note
that only [48] features integrated Baluns. Of all the options
presented, the high-Q filtering is the most promising one
(compared to feedforward or mixer-first) as the noise figure at
sensitivity is compromised the least. Moreover, feedforward
techniques unless compensated by some LMS routine, seem to
provide limited filtering. Table I summarizes the main features
of each architecture.
As for a comparison to the receivers with external SAW filters, There is typically some power penalty, for instance about
5 mA from battery in the case SAW-less RX in [48]. Also the
NF is usually higher, how the overall system NF is less due to
the SAW elimination.
IV. 3G RECEIVER SAW ELIMINATION
In a SAW-less 3G receiver, assuming 45 dB of duplexer isolation and 3 dB of TX insertion loss, the TX leakage at the LNA
dBm, assuming
input is calculated to be
full power transmission of 24 dBm at the antenna. This value is
substantially lower than the 0 dBm blocker present in the GSM
case, and also at a further offset frequency of 45 MHz in low
bands, or at least 80 MHz in high bands (as opposed to 20 MHz
in GSM). Depending on duplexer rejection at half-duplex freof about
to 0 dBm is
quency (Fig. 6), an out-of-band
needed. For instance, for a blocker at half-duplexer frequency
), assuming 25 dB of duplexer
(that is at
can be calculated as follows:
filtering, the

where
is the blocker power specified to be
dBm,
less the 25 dB rejection, the sensitivity for the blocking is
dBm
MHz
dB, and the SNR is
dB, assuming a processing gain of 21 dB (or 128). This calculation
of
dBm. This result is obviously a function
leads to an
of the duplexer isolation and filtering and can vary based on the
platform but is certainly very challenging given that the blocker
can be as close as 22.5 MHz, subject to little filtering in the relatively wideband LNA. Similar to the third-order nonlinearity,

Fig. 23. SAW-less 3G RX front-end tolerant to TX leakage.

the receiver second-order nonlinearity amplitude demodulates

the TX leakage and raises the RX noise floor. If no filtering
of better than
dBm
achieved at the TX frequency,
is typically desirable so as not to affect the receiver sensitivity
considerably. This along with the TX noise (Section V) will
effectively determine the receiver noise figure and adds to
the thermal noise of the receive path alone. Most receivers
today target for 2.53 dB of noise figure with additional 0.51
dB degradation due to the second-order nonlinearity and the
transmitter noise in the RX band.
and
can be substantially relaxed if
The receiver
any of the filtering techniques presented in the previous section
are adopted. Alternatively, because the TX leakage is relatively
dBm versus 0 dBm in
weak compared to GSM receivers (
GSM), a simplified front end, such as the one shown in Fig. 23,
can be used where only one stage of filtering at LNA output
is used [23], [25], [26]. The main advantage here is less power
consumption owing to the fact that the 3G blocker does not impose any compression issue at the LNA input.
Moreover, to save power, the receiver can use 50% of the LO
signals, as opposed to the 25% used in the GSM front end of
Fig. 16 [23]. In the case of 50% LO signal use, however, the
image current circulating between the I and Q branches is troublesome and must be minimized based on the techniques offered
in [23] and [24], which mainly involves the proper choice of capacitance C and the resonance mode of the LNA RLC load.
V. TRANSMITTER SAW ELIMINATION
As mentioned in Section II, PLL-based TX architectures are
dBc Hz
proven to achieve the required phase noise of
at a reasonable power consumption. Thus, as also shown in
Fig. 7(a), all the current GSM/EDGE transmitters are SAW-less
[6][12]. In the case of EDGE modulation, because the output
power is 6 dB less (that is, 27 dBm for the low band), the phase
dBc Hz or better
noise accordingly is relaxed to about
at a 20 MHz offset. The EDGE transmitter may be built as an
extension of the GSM direct-modulated PLL through a polar
scheme [40]. Alternatively, at the expense of more power consumption, a linear transmitter may be used. Given the 6 dB more
relaxed noise requirement, a direct-IQ (or linear) transmitter
would work reasonably well, although it would be more power
consuming than what can be achieved in the polar scheme.

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Fig. 24. Current 3G transmitters.

On the other hand, due to architectural challenges of polar

transmitters [7][12], [40] for wide-band modulation transmitters such as 3G, a more straightforward direct-IQ scheme is
adopted [27][30], [45], [46], which is noisier due the contribution of the modulator. This scheme is shown in Fig. 24, where
typically, the GSM path is using PLL-based architecture to meet
the tight noise requirements, but to overcome the challenges of
the polar scheme, the 3G transmitter is linear [40]. The EDGE
can be either an extension of the PLL-based TX or be run on the
linear 3G portion, as discussed earlier.
To derive the noise requirements of the 3G TX, let us assume a duplexer isolation of 45 dB with 3 dB of insertion loss,
which is common for most of current front ends. A phase noise
dBc Hz at the transmitter output (excluding the PA)
of
dBm Hz.
leads to a noise floor of
If the RX has a thermal noise figure of 2.5 dB, this condition
effectively degrades the sensitivity by about 0.5 dB, which is
acceptable in most designs. The power amplifier noise will add
to this further. Meeting this phase noise target is practical, although not easy, as demonstrated in [27][29], provided that the
phase noise of the VCO, the LO chain, and the TX IQ modulator
is properly optimized. A notch filter in the TX path can lower
the power consumption further (if one chooses to use one) [30],
although the transmitters presented in [28] and [29] seem to be
adequately low-power. Also, there recently have been alternative approaches to realize true multimode 3G transmitters using
wideband polar architectures [37], [38]. An example of a multimode GSM/EDGE/WCDMA wideband polar transmitter based
on an analog two-point modulation PLL [37] is shown in Fig. 25.
As the VCO linearity and gain accuracy are crucial to achieve a
wideband all-pass response, an embedded feedback-frequency
locked loop is employed to stabilize the VCO gain and to ensure
robust performance.
VI. DUPLEXER TECHNIQUES
So far we have established several techniques to eliminate the
external SAW filters in both RX and TX in 2G and 3G modes of
operation. The duplexer, which is unique only to 3G radios, is
discussed in this section. As 3G systems are full-duplex (that is,
the TX and RX operate concurrently), a duplexer is needed at the
antenna to isolate (or more importantly, protect) the LNA from
the high-power PA output going to the antenna (Fig. 26). Typically, an isolation of 4550 dB in the RX band and 45 dB in the

Fig. 25. Wideband polar multimode 3G transmitter.

Fig. 26. Basic duplexer operation.

TX band is common in current platforms. Because modern RF

duplexers rely on frequency-selective filters for isolation, these
stringent requirements prohibit their integration on silicon, particularly in CMOS. An alternative implementation is based on
the electrical balance [33] of a hybrid transformer rather than
frequency selectivity, which unfavorably requires high-Q elements. This concept, along with a prototype duplexer, is discussed next in more detail.
A. Electrical Balance Concept
An integrated duplexer should perform two functions: first,
it must provide concurrent matching for the antenna, the transmitter, and the receiver, and second, it should attenuate the transmitted signal at the RX input to avoid saturation or desensitization. The solution to this challenge was introduced some 90
years ago for old telephony systems, relying on a class of networks called maximum output networks [31].
In a telephone handset, the weak received signal from the
switching office should be isolated from the strong locally generated microphone signal; otherwise, listeners will be deafened
by their own voices. The isolation was implemented using
the hybrid transformer shown in Fig. 27. When the balancing
is identical to the switching office line resistance
resistor
, the microphone current experiences identical loads (the
same inductors and resistors are used). Therefore, identical
voltage waveforms are formed on the line and the balancing
resistor. Thus, the microphone voltage shown in black appears
as common-mode and does not create a voltage across L2.
On the other hand, the PSTN current (in grey), experiences a
single-ended circuit and couples to the speaker with the voltage
gain of the hybrid transformer.
A well-known embodiment of the hybrid transformer (HT) as
an RF duplexer is shown in Fig. 28 [32], [33]. The HT has sev-

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2047

Fig. 27. Electrical balance in a telephone handset.

Fig. 29. Prototype 3G duplexer.

Fig. 28. Electrical balance in modern 3G transceivers.

Fig. 30. Reciprocity in electrical balance duplexers.

eral peculiar characteristics: First, all HT ports can be simultaneously matched; second, HT ports are bi-conjugate (TX and RX
are electrically isolated from each other, as are the antenna and
); and third, the incoming power from
balancing resistor
one port can be split in any ratio between the two receiving ports.
The HT shown in Fig. 28 is a balun with three ports connected
and matched to the RX, TX, and antenna. The fourth port, which
.
is the center tap, is connected to the balancing resistor
For the ideal balun to operate as a HT, the values of the port resistance should satisfy the following requirements:

than 250 MHz, limited only by pad, bondwire, and other parasitics.
As for the performance of the ideal balun, the insertion loss
(IL) is 3 dB for both the TX and the RX. As shown in Fig. 30,
this loss is the result of the reciprocity, which is a characteristic of any passive network. In other words, if the antenna is
pledged to deliver 100% power to the receiver for zero receiver
insertion loss, so would be the receiver to the antenna. This condition works against delivering the full power from the antenna
to the TX. Theoretically, half of the power would be wasted,
and in the case of the hybrid transformer, the power would be
dissipated in the fourth terminal (the balancing resistor). Thus,
the electrical balance duplexer suffers from a fundamental 3 dB
loss. A practical balun suffers an additional Ohmic loss, as it is
formed by coupling two separate inductors. Thus, in a monolithic balun, the loss and the coupling trade off with each other.
To reduce the Ohmic loss of the HT, an autotransformer (implemented as a differential inductor) may be used alternatively
[33]. The simplicity of the implementation yields lower loss for
the same coupling, which is about 0.5 dB here.
The transformer could be skewed in favor of the transmitter
or the receiver at the expense of degrading one loss for the other.
The transmitter insertion loss versus that of the receiver is shown
in Fig. 31. At the midpoint, both the RX and TX experience an
ideal loss of 3 dB. The transformer, however, can be skewed to
have fewer turns on the transmitter side (with a ratio of 0.63,
as shown in the example in Fig. 31) to reduce the loss to about
2 dB. This will increase the RX loss, however, to about 4 dB
when matched to 50 . This IL tradeoff potentially present in
the duplexer can be circumvented when we note that the absolute power level at the LNA input is irrelevant to the RX operationall that matters is signal-to-noise ratio. In other words,
the RX IL and the effective NF of the duplexer are not necessarily identical, which is not the case for an external SAW duplexer whose two ports must terminate in 50 . Therefore, in

Once all ports are matched, the balance is achieved, and the TX
and the RX are perfectly isolated. The isolation is merely a function of the matching between the antenna and the balancing resistor, and thus, ideally, is frequency-independent. This condition, which is unlike the external duplexers that rely on selectivity, can be implemented on-chip, where good resolution and
matching can be achieved.
B. Prototype Implementation
For proof of concept, a prototype duplexer for 3/4G applications based on the HT in Fig. 28 is implemented (Fig. 29) [34].
At balance, there is no net differential voltage across the balun,
and so zero self-inductance current flows. The duplexer is balanced when the voltage at the antenna port is equal to that at
the balancing network. Consequently, the TX signal appears as
common-mode and does not create a voltage across the LNA
input inductor. This scheme yields an isolation bandwidth (the
bandwidth where isolation remains better than 50 dB) of better

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Fig. 31. TX-RX insertion loss trade-off.

Fig. 34. Addressing the antenna mismatch issue.

the common mode at its two input terminals, without the benefit
of the third winding.
D. Antenna Mismatch
Fig. 32. LNA circuit.

Fig. 33. High-power duplexer.

this prototype, the LNA, shown in Fig. 32, is noise-matched by

maximizing the voltage gain that the signal experiences from
the antenna to the LNA input (about 6 dB). Referred to the antenna, the equivalent input voltage noise of the LNA is divided
by this gain. The noise-matched LNA reduces the NF to less
than 1 dB, compared to 3 dB for the LNA in [33]. The achieved
antenna return loss is better than 8 dB, as expected.
C. Full Power Challenges
In 3G TX, the PA should deliver a maximum power of 24
dBm to the antenna. For a typical peak-to-average ratio of 3.2
dB, the antenna peak-to-peak voltage swing is about 15 V. The
CMOS resistors, capacitors, and inductors can tolerate the 15 V
swing without breakdown or reliability problems, especially as
no dc current flows in the duplexer. A 65 nm thin-oxide NMOS
switch, however, cannot tolerate this voltage. Instead, a switch
based on stacked FETs with floating well structure [35] may be
used, as shown in Fig. 33.
The full-power duplexer should be codesigned with the PA
to benefit from the inherent 1:2 impedance transformation of
the autotransformer. In this work, we have realized a duplexer
to validate the wideband isolation and the low loss at moderate
signal voltages. To simplify autotransformer design, the LNA
was directly connected across the autotransformer and rejected

Another concern arises from the antenna mismatch, which

could adversely affect the duplexer isolation. As mentioned
earlier, the isolation is achieved when the balancing network
impedance tracks the antenna impedance, but, as the near-field
of the antenna is perturbed, the antenna impedance slowly
changes. The industry specification for acceptable antenna
impedance variation is a voltage standing wave ratio (VSWR)
of 3:1. Therefore, the antenna impedance can lie anywhere
inside the grey circle shown in Fig. 34. The balancing network
impedance can track some variations around the center of the
Smith chart with fine resolution, which is the shaded area in
grey. Note that the antenna impedance variation is very slow
(on the orders of tens of milliseconds or more). The duplexer
isolation can simply monitored at the LNA input and the
balancing network impedance can be corrected accordingly.
The antenna tuning unit provides a coarse tuning across the
area. The most common implementation for
whole
the antenna tuning unit is a pi network, with an off-chip inductor
and two on-chip capacitor banks (Fig. 34). The main motivation
behind the ATU is to improve the PA efficiency under antenna
mismatch conditions, but we use it here for the duplexer as well.
Note that the duplexer loss is little affected by the antenna
mismatch, and mostly, it is the isolation that will be compromised. This behavior is certainly the opposite of the external
duplexers, which are based on high-Q filtering. Moreover, it is
noteworthy to mention that, in most cases, the transceiver key
requirements (sensitivity being one) are allowed to be relaxed
some in the presence of the antenna mismatch.
E. Prototype Measurement Results
The prototype duplexer is implemented in a 65 nm CMOS
technology, with an active area of less than 0.1 mm and a total
area of 0.2 mm , including the LNA, as shown in Fig. 35[34].
The LNA draws 10 mA from 1.2 V. The balancing network
is designed as an array of switched resistors and capacitors.
The array covers the tuning range over process corners and the
temperature range with a 25% margin. Simulation results indicate that the autotransformer can provide isolation over the
range from 0.53 GHz. In this prototype, however, the LNA
covers only the high band from 1.82.2 GHz, limited by the
load, which, if needed, can easily be extended. The simulated

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2049

Although techniques proposed here are generic and not frequency- or application-dependent, examples demonstrated here
cover cellular design, which is the most challenging from a
filtering perspective. Both the filtering and electrical balance
schemes work well over a wide range of frequency and could
be used in generic SDRs, up to 6 GHz and beyond.
With the circuit and architectural techniques proposed here,
realization of SAW-less radios with integrated duplexers is imminent and inevitable.
Fig. 35. Prototype duplexer die photo.

Fig. 36. (a) LNA/duplexer cascaded NF. (b) Duplexer isolation.

Fig. 37. TX measured insertion loss.

and measured cascaded NF is 5 dB with a gain of more than 27

dB [Fig. 36(a)]. The simulation and measurement results of the
TX-RX isolation are illustrated in Fig. 36(b), where better than
55 dB of isolation in the TX band and better than 45 dB of isolation in the RX band are achieved.
The measured IL on TX port is better about 2.2 dB and is
shown in Fig. 37.
VII. CONCLUSIONS AND DISCUSSION
Software-defined radios cover several bands and modes of operation through maximum hardware sharing and a wide tuning
range. In all solutions presented so far, however, the lack of integrated and tunable RF filtering opposes this flexibility. Moreover, there are obvious cost implications due to the external filtering needed. Several circuit-level and architectural techniques
to solve this challenge were presented in this paper. We proposed highly integrated and tunable RF filters for 2G and 3G
receivers, along with architectural schemes to eliminate the intermediate SAW filters in 3G transmitters. Tunable integrated
duplexers based on electrical balance prove to be a competitive replacement for the current frequency-selective designs, allowing ultralow cost solutions, with maximum hardware sharing
and programmability.

REFERENCES
[1] J. Mitola, Cognitive radio architecture evolution, Proc. IEEE, vol. 97,
no. 4, pp. 626641, Apr. 2009.
[2] J. Mitola, The software radio architecture, IEEE Commun. Mag., vol.
33, no. 5, pp. 2638, May 1995.
[3] R. Bagheri et al., An 800-MHz-6 GHz software-defined wireless receiver in 90-nm CMOS, IEEE J. Solid-State Circuits, vol. 41, pp.
28602876, Dec. 2006.
[4] B. Murmann, ADC Performance Survey 19972008 [Online]. Available: http://www.stanford.edu/murmann/adcsurvey.html
[5] O. E. Erdogan et al., A single-chip quad-band GSM/GPRS transceiver
in 0.18  m standard CMOS, ISSCC Dig. Tech. Papers, pp. 318319,
Feb. 2005.
[6] O. Bonnaud et al., A fully integrated SoC for GSM/GPRS in 0.13  m
CMOS, ISSCC Dig. Tech. Papers, pp. 482483, Feb. 2006.
[7] R. Pullela et al., An integrated closed-loop polar transmitter with saturation prevention and low-IF receiver for quad-band GPRS/EDGE,
ISSCC Dig. Tech. Papers, pp. 112113.
[8] H. Darabi et al., A quad-band GSM/GPRS/EDGE SoC in 65 nm
CMOS, in VLSI Symp., Jun. 2010, pp. 8990.
[9] H. Darabi et al., A fully integrated quad-band GPRS/EDGE radio in
0.13  m CMOS, ISSCC Dig. Tech. Papers, pp. 206207, Feb. 2008.
[10] J. Mehta et al., A 0.8 mm all-digital SAW-less polar transmitter in
65 nm EDGE SoC, ISSCC Dig. Tech. Papers, pp. 5859, Feb. 2010.
[11] G. Puma et al., Integration of a SiP for GSM/EDGE in CMOS technology, ISSCC Dig. Tech. Papers, pp. 210211, Feb. 2008.
[12] M. Elliott et al., A polar modulator transmitter for EDGE, ISSCC
Dig. Tech. Papers, pp. 188189, Feb. 2004.
[13] S. Pipilos et al., A Si 1.8 GHz RLC filter with tunable center frequency
and quality factor, IEEE J. Solid-State Circuits, vol. 31, no. 10, pp.
15171525, 1996.
[14] X. He and W. Kuhn, A 2.5-GHz low-power, high dynamic range, selftuned Q-enhanced LC filter in SOI, IEEE J. Solid-State Circuits, vol.
40, no. 8, pp. 16181628, 2005.
[15] W. Kuhn et al., Dynamic range performance of on-chip RF bandpass
filters, IEEE Trans Circuits Syst. II, Exp. Briefs, vol. 50, no. 10, pp.
685694, 2003.
[16] M. C. M. Soer et al., A 0.2-to-2.0 GHz 65 nm CMOS receiver without
LNA achieving > 11 dBm IIP3 and < 6:5 dB NF, ISSCC Dig. Tech.
Papers, pp. 222223, Feb. 2009.
[17] C. Andrews et al., A passive-mixer-first receiver with baseband-controlled RF impedance matching, < 6 dB NF, and > 27 dBm wideband
IIP3, ISSCC Dig. Tech. Papers, pp. 4647, Feb. 2010.
[18] H. Darabi, A blocker filtering technique for SAW-less wireless receivers, IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 27662773,
Dec. 2007.
[19] L. Franks and I. Sandberg, An alternative approach to the realizations
of network functions: N-path filter, Bell Syst. Tech. J., pp. 13211350,
1960.
[20] D. V. Grunigen et al., An integrated CMOS switched-capacitor bandpass filter based on N-path and frequency-sampling principles, IEEE
J. Solid-State Circuits, vol. SC-18, no. 6, pp. 753761, 1983.
[21] A. Mirzaei et al., Analysis and optimization of direct-conversion
receivers with 25% duty-cycle current-driven passive mixers, IEEE
Trans Circuits Syst. I, Reg. Papers, vol. 47, no. 9, pp. 23532366,
2010.
[22] A. Mirzaei et al., A 65 nm CMOS quad-band SAW-less receiver for
GSM/GPRS/EDGE, in Proc. VLSI Symp., Jun. 2010, pp. 179180.
[23] A. Mirzaei, J. Leete, X. Chen, and H. Darabi, A frequency translation
technique for SAW-less 3G receivers, in Proc. VLSI Symp., Jun. 2009,
pp. 280281.
[24] A. Mirzaei et al., Analysis and optimization of current-driven passive
mixers in narrowband direct-conversion receivers, IEEE J. Solid-State
Circuit, vol. 44, no. 10, pp. 26782688, Oct. 2009.

2050

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011

[25] D. Kaczman et al., A single-chip 10-band WCDMA/HSDPA 4-band

GSM/EDGE SAW-less CMOS receiver with DigRF 3G interface and
90 dBm IIP3, IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 718739,
2009.
[26] B. Tenbroek et al., Single-chip tri-band WCDMA/HSDPA transceiver
without external SAW filters and with integrated TX power control,
ISSCC Dig. Tech. Papers, pp. 202203, Feb. 2008.
[27] C. Jones et al., Direct-conversion WCDMA transmitter with
163 dBc=Hz noise at 190 MHz offset, ISSCC Dig. Tech. Papers,
pp. 336337, Feb. 2007.
[28] Q. Huang et al., A tri-band SAW-less WCDMA/HSPA RF CMOS
transceiver with on-chip DC-DC converter connectable to battery, in
ISSCC Dig. Tech. Papers, Feb. 2010, pp. 6061.
[29] X. He et al., A 45 nm WCDMA transmitter using direct quadrature
voltage modulator with high oversampling digital front-end, in ISSCC
Dig. Tech. Papers, Feb. 2010, pp. 6263.
[30] A. Mirzaei and H. Darabi, A low-power WCDMA transmitter with
an integrated notch, IEEE J. Solid-State Circuits, vol. 43, no. 12, pp.
28682888, 2008.
[31] G. A. Campbell et al., Maximum output networks for telephone substation and repeater circuits, Trans. AIEE, vol. 39, 1920.
[32] E. Sartori, Hybrid transformers, IEEE Trans. Parts, Mater., Packag.,
vol. PMP-4, no. 8, pp. 5966, Sep. 1968.
[33] M. Mikhemar et al., A tunable integrated duplexer with 50 dB isolation in 40 nm CMOS, in ISSCC Dig. Tech. Papers, Feb. 2009, pp.
386387.
[34] M. Mikhemar et al., An on-chip wideband and low-loss duplexer for
3G/4G CMOS radios, in VLSI Symp., Jun. 2010, pp. 129130.
[35] M. Ahn et al., A 1.8-GHz 33-dBm P0.1-dB CMOS T/R switch using
stacked FETs with feed-forward capacitors in a floated well structure,
IEEE Trans. Microw. Theory Tech., vol. 57, no. 11, pp. 26612670,
2009.
[36] H. Darabi et al., A quad-band GSM/GPRS/EDGE SoC in 65 nm
CMOS, IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 870872,
Apr. 2011.
[37] M. Youssef, A. Zolfaghari, H. Darabi, and A. Abidi, A low-power
wideband polar transmitter for 3G applications, ISSCC Dig. Tech. Papers, Feb. 2011.
[38] Z. Boos et al., A fully digital multi-mode polar transmitter employing
17b RF DAC in 3G mode, ISSCC Dig. Tech. Papers, Feb. 2011.
[39] H. Darabi and A. A. Abidi, Noise in RF-CMOS mixers: A simple
physical model, IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 1525,
2000.
[40] H. Darabi, H. Jensen, and A. Zolfaghari, Analysis and design of small
signal polar transmitters for cellular applications, IEEE J. Solid-State
Circuits, vol. 46, no. 6, pp. 12371249, 2011.
[41] Y. Akamine et al., A polar loop transmitter with digital interface including a loop-bandwidth calibration system, in ISSCC Dig. Tech. Papers, Feb. 2007, pp. 348349.
[42] R. B. Staszewski et al., A 24 mm quad-band single-chip GSM radio
with transmitter calibration in 90 nm digital CMOS, in ISSCC Dig.
Tech. Papers, Feb. 2008, pp. 208209.
[43] A. Hietala, A quad-band 8PSK/GMSK polar transceiver, IEEE J.
Solid-State Circuits, vol. 41, no. 5, pp. 11311141, 2006.
[44] T. Sowlati et al., Quad-band GSM/GPRS/EDGE polar loop transmitter, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 21792189,
2004.
[45] M. Cassia et al., A low-power CMOS SAW-less quad band
WCDMA=HSPA=HSPA + =1X=EGPRS transmitter, IEEE J.
Solid-State Circuits, vol. 44, no. 7, pp. 18971906, Jul. 2009.
[46] T. Sowlati et al., Single-chip multi-band WCDMA/HSDPA/HSUPA/
EGPRS transceiver with diversity receiver and 3G DigRF interface
without SAW filters in transmitter/3G receiver, in ISSCC Dig. Tech.
Papers, Feb. 2009, pp. 116117.

[47] M. Ingels et al., A 5 mm 40 nm LP CMOS transceiver for a softwaredefined radio platform, IEEE J. Solid-State Circuits, vol. 45, no. 12,
pp. 27942806, 2010.
[48] A. Mirzaei et al., A 65 nm CMOS quad-band SAW-less receiver for
GSM/GPRS/EDGE, IEEE J. Solid-State Circuits, vol. 46, no. 4, pp.
950964, Apr. 2011.
[49] J. Borremans et al., A 40 nm CMOS highly linear 0.4-to-6 GHz receiver resilient to 0 dBm out-of-band blockers, in ISSCC Dig. Tech.
Papers, Feb. 2011, pp. 6264.
[50] I. Lu et al., A SAW-less GSM/GPRS/EDGE receiver embedded in a
65 nm SoC, in ISSCC Dig. Tech. Papers, Feb. 2011, pp. 364365.
[51] S. Ayazian and R. Gharpurey, Feedforward interference cancellation
in radio receiver front-ends, IEEE Trans. Circuits Syst. II, Exp. Briefs,
vol. 54, no. 10, pp. 902906, Oct. 2007.
[52] R. Gharpurey and S. Ayazian, Feedforward interference cancellation
in narrow-band receivers, in Proc. IEEE Dallas/CAS Workshop Design, Appl., Integr. Software, 2006, pp. 6770.
[53] H. Khatri et al., Distortion in current commutating passive CMOS
downconversion mixers, IEEE Trans. Microw. Theory Tech., vol. 57,
no. 11, pp. 26712681, Nov. 2009.
[54] A. Safarian et al., Integrated blocker filtering RF front-ends, in Proc.
2007 Radio Freq. Integr. Circuits (RFIC) Symp., 2007, pp. 1316.

Hooman Darabi received the Ph.D. degree in electrical engineering from the University of California,
Los Angeles in 1999.
He is currently a Senior Technical Director with
Broadcom Corporation, Irvine, CA. His interests include analog and RF IC design for wireless communications, including Bluetooth, WLAN, and cellular
applications.

Ahmad Mirzaei received the Ph.D. degree in electrical engineering from the University of California,
Los Angeles, in 2006.
He is currently a Principal Scientist with
Broadcom Corporation, Irvine, CA. His interests
include analog and RF IC design for wireless communications.

Mohyee Mikhemar received the B.S. and M.S. degrees with honors in electrical engineering from Ain
Shams University, Egypt, in 2000 and 2004, respectively, and the Ph.D. degree from the University of
California, Los Angeles, in 2009.
Currently, he is a Senior Staff Scientist at the
advanced RF research and development department with Broadcom Corporation, Irvine, CA. His
research interests include low power multiband
and multimode radio design in CMOS, multiband
duplexers, and RF filters on silicon and digitally
assisted RF circuits.