LFS & Sleep Stack with Keeper : Two New Low-
Power leakage reduction Techniques
Pankaj Kr. Pal*, Ashwani K. Rana**
Abstract- For the most recent CMOS feature sizes (e.g., 90nm
and 65nm), leakage power dissipation has become an overriding
concern for VLSI circuit designers. ITRS reports that leakage
power dissipation may come to dominate total power
consumption [1]. We are doing comparable analysis of different
low power, leakage current reduction techniques like SLEEP
approach, STACK, ZIGZAG & some new techniques like ,
SLEEPY–STACK, LEAKAGE FEEDBACK approach and
SLEEPY KEEPER techniques. And , after That to combine the
advantages of above written techniques, we propose two novel
approaches, named “Leakage Feedback with Stack (LFS)” &
“Sleep Stack With Keeper (SSK)” which reduces leakage
current while saving exact logic state. But Based on simulations
result with a full adder circuit, “Sleep-Stack with keeper
approach” achieves up to 76% less power consumption.
Keywords—low power design, leakage reduction,
sleep, stack, sleepy-stack, keeper.
I. INTRODUCTION
Power consumption is one of the top concerns of Very
Large Scale Integration (VLSI) circuit design, for which
Complementary Metal Oxide Semiconductor (CMOS) is the
primary technology. Today’s focus on low power is not only
because of the recent growing demands of mobile
applications. Even before the mobile era, power consumption
has been a fundamental problem. To solve the power
dissipation problem, many researchers have proposed
different ideas from the device level to the architectural level
and above. However, there is no universal way to avoid
tradeoffs between power, delay and area, and thus designers
are required to choose appropriate techniques that satisfy
application and product needs.
* Pankaj Kr. Pal, M.Tech. Scholar, “VLSI Design Automation &
Techniques”, E&CED, National Institute of Technology, Hamirpur,
Himanchal Pradesh; E-mail: pankajpal86@ gmail.com .
** Ashwani K. Rana, Sr. Lecturer & Ph.d Research Scholar, E&CED,
National Institute of Technology, Hamirpur, Himanchal Pradesh; E-mail:
ashwani@nitham.ac.in.
Power consumption of CMOS consists of dynamic and
static components. Dynamic power is consumed when
transistors are switching, and static power is consumed
regardless of transistor switching. Dynamic power
consumption was previously (at 0.18μ technology and above)
the single largest concern for low-power chip designers since
dynamic power accounted for 90% or more of the total chip
power. Therefore, many previously proposed techniques, such
as voltage and frequency scaling, focused on dynamic power
reduction. However, as the feature size shrinks, e.g., to 0.09μ
and 0.065μ, static power has become a great challenge for
current and future technologies. Based on the International
Technology Roadmap for Semiconductors (ITRS) [1], Kim et
al. report that sub-threshold leakage power dissipation of a
chip may exceed dynamic power dissipation at the 65nm
feature size [11].
One of the main reasons causing the leakage power increase
is increase of sub-threshold leakage power. When technology
feature size scales down, supply voltage and threshold voltage
also scale down. Sub-threshold leakage power increases
exponentially as threshold voltage decreases. Furthermore, the
structure of the short channel device lowers the threshold
voltage even lower. In addition to sub-threshold leakage,
another contributor to leakage power is gate-oxide leakage
power due to the tunneling current through the gate-oxide
insulator. Since gate-oxide thickness will be reduced as the
technology decreases, in nano-scale technology, gate-oxide
leakage power may be comparable to sub-threshold leakage
power if not handled properly. However, we assume other
techniques will address gate-oxide leakage; for example, high-
k dielectric gate insulators may provide a solution to reduce
gate-leakage [11]. Therefore, this project work focuses on
reducing sub-threshold leakage power consumption.
II. PREVIOUS WORK
We here review previously proposed circuit level
approaches for sub-threshold leakage power reduction. The
most well-known traditional approach is the sleep approach
[2][3]. In the sleep approach, both (i) an additional "sleep"
PMOS transistor is placed between VDD and the pull-up The sleepy stack approach combines the sleep and stack
network of a circuit and (ii) an additional "sleep" NMOS approaches [6][7]. The sleepy stack technique divides existing
transistor is placed between the pull-down network and GND. transistors into two half size transistors like the stack
These sleep transistors turn off the circuit by cutting off the approach.
power rails. Figure 1 shows its structure. The sleep transistors
are turned on when the circuit is active and turned off when
the circuit is idle. By cutting off the power source, this
technique can reduce leakage power effectively. However,
output will be floating after sleep mode, so the technique
results in destruction of state plus a floating output voltage.

A variation of the sleep approach, the zigzag approach,

reduces wake-up overhead caused by sleep transistors by
placement of alternating sleep transistors assuming a
particular pre-selected input vector [4]. In Figure 2, we
assume that, in sleep mode, the input of the logic is ‘0’ and
each logic stage reverses its input signal, i.e., the output is ‘1’
if the input is ‘0,’ and the output is ‘0’ is the input is ‘1.’ If the
output is ‘1,’ then a sleep transistor is added to the pull-down
Fig. 3 Stack Approach Fig. 4 Sleepy Stack Approach
network; if the output is ‘0’, then a sleep transistor is added to
the pull-up network. Thus, the zigzag approach uses fewer
sleep transistors than the original sleep approach.
Then sleep transistors are added in parallel to one of the
Furthermore, this approach still results in destruction of state
divided transistors. Figure 4 shows its structure. During sleep
(i.e., state is set to the particular pre-selected input vector),
mode, sleep transistors are turned off and stacked transistors
although the problem of floating output voltage is eliminated.
suppress leakage current while saving state. Each sleep
transistor, placed in parallel to the one of the stacked
transistors, reduces resistance of the path, so delay is
decreased during active mode. However, area penalty is a
significant matter for this approach since every transistor is
replaced by three transistors and since additional wires are
added for S and S’, which are sleep signals.

Fig. 1 Sleep approach Fig. 2 Zigzag Approach

Another technique for leakage power reduction is the stack

approach, which forces a stack effect by breaking down an
existing transistor into two half size transistors [5]. Figure 3
shows its structure. When the two transistors are turned off
together, induced reverse bias between the two transistors
results in sub-threshold leakage current reduction.
Fig. 5 Leakage feedback approach Fig. 6 Sleepy Keeper approach
 The leakage feedback approach is based on the sleep
approach. However, the leakage feedback approach uses two
additional transistors to maintain logic state during sleep
mode, and the two transistors are driven by the output of an
inverter which is driven by output of the circuit implemented
utilizing leakage feedback [14]. As shown in Figure 5, a
PMOS transistor is placed in parallel to the sleep transistor (S)
and a NMOS transistor is placed in parallel to the sleep
transistor (S'). The two transistors are driven by the output of
the inverter which is driven by the output of the circuit.
During sleep mode, sleep transistors are turned off and one of
the transistors in parallel to the sleep transistors keep the
connection with the appropriate power rail.
The basic problem with traditional CMOS is that the
transistors are used only in their most efficient, and naturally
inverting, way: namely, PMOS transistors connect to VDD
and NMOS transistors connect to GND. It is well known that
PMOS transistors are not efficient at passing GND; similarly,
it is well known that NMOS transistors are not efficient at
passing VDD. However, to maintain a value of ‘1’ in sleep
mode, given that the ‘1’ value has already been calculated, the
sleepy keeper approach uses this output value of ‘1’ and an
NMOS transistor connected to VDD to maintain output value
equal to ‘1’ when in sleep mode. As shown in Figure 6, an
additional single NMOS transistor placed in parallel to the
pull-up sleep transistor connects VDD to the pull-up network.
When in sleep mode, this NMOS transistor is the only source
of VDD to the pull-up network since the sleep transistor is off.
Similarly, to maintain a value of ‘0’ in sleep mode, given that
the ‘0’ value has already been calculated, the sleepy keeper
approach uses this output value of ‘0’ and a PMOS transistor
connected to GND to maintain output value equal to ‘0’ when
in sleep mode. As shown in Figure 6, an additional single
PMOS transistor placed in parallel to the pull-down sleep
transistor is the only source of GND to the pull-down network
which is the dual case of the output ‘1’ case explained above.
For this approach to work, all that is needed is for the NMOS
connected to VDD and the PMOS connected to GND to be
able to maintain proper logic state. This seems likely to be
possible as other researchers have described ways to use far
lower VDD values to maintain logic state. For example,
Flautner et al. propose some significantly reduced VDD
values sufficient to maintain state [10].
For the sleep, zigzag, sleepy stack and leakage feedback
approaches, sleepy keeper approach, dual Vth technology can
be applied to obtain greater leakage power reduction. Since
high-Vth results in less leakage but lowers performance, high-
Vth is applied only to leakage reduction transistors, which are
sleep transistors, and any transistors in parallel to the sleep
transistors; on the other hand, low-Vth is applied to the
remaining transistors to maintain logic performance [2]-[7].
III. MOTIVATION
Currently, sub-threshold leakage seems to be the dominant
contributor to overall leakage power [8]. Another possible
contributor to leakage power is gate-oxide leakage. A possible
solution widely reported is the potential use of high-k (high
dielectric constant) gate insulators [9]. In any case, this papers
targets reduction of the sub-threshold leakage component of
static power consumption; other approaches should be
considered for reduction of gate oxide leakage. Do please
note, however, that all results reported in this paper include all
sources of leakage power. With application of dual threshold
voltage (Vth) techniques, the sleep, zigzag and sleepy stack
approaches result in orders of magnitude sub threshold
leakage power reduction [7] but in this papers we are not
using dual Vth approach. The major advantage of the sleepy
stack approach over the sleep and zigzag approaches is that
the sleepy stack approach saves exact logic state. However,
the sleepy stack approach carries a nontrivial penalty: each
transistor in the original, base case, traditional CMOS design
results in three transistors in the sleepy stack equivalent. The
goal of our new approach is to achieve the benefit of all above
written techniques, and now we propose two novel
approaches, named “Leakage Feedback with Stack” & “Sleep
Stack With Keeper” which reduces leakage current while
saving exact logic state.
IV. LFS & SLEEP STACK WITH KEEPER
In this section, we describe our new leakage reduction
techniques ,in which we call the first one “Leakage feedback
with stack (LFS) ” approach and other is “Sleep-stack with
Keeper” . This section explains the structure of the Leakage
feedback with stack approach and Sleep-stack with Keeper.
In First technique i.e. Leakage feedback with stack (LFS, we
are combining the two low power techniques or taking
advantage of two techniques i.e. Leakage feedback approach
due to less transistor than sleepy-stack in which we replaces
each transistor in base case into three transistors, and ultra low
power technique i.e. Stack approach. This is shown in fig. 7
In second approach i.e. Sleep-stack with Keeper, we are
combining the three different low power leakage reduction
techniques i.e sleep transistors, stack approach with keeper as
shown in fig 8.
 process as well as the Berkeley Predictive Technology Model
(BPTM) [12][13] approach for 0.18, 0.13, 0.10, and 0.07μm
processes. We use Tanner-SPICE ie T-SPICE simulation to
estimate only Average power consumption. The supply
voltages used by the technologies are tabulated in Table 1.

Technology 0.07 μ 0.1 μ 0.13 μ 0.18 μ

Vdd 1.0 V 1.3 V 1.6 V 2.0 V

Table 1. Supply voltages for different technologies

VI. SIMULATION RESULTS

Fig. 7 Leakage feedback with Stack
We measure only the average power consumption for nine
design approaches, which are the base case, sleep, zigzag,
stack, sleepy stack , leakage feedback and sleepy keeper
approaches with newly proposed approaches named “Leakage
Feedback with Stack” & “Sleep Stack With Keeper”. The
static power measurement for the leakage feedback approach
by using same method for all other approaches resulted in 10X
greater than the result of the base case. For this reason, we do
not show results for the leakage feedback approach.
.
A 1-bit Full-adder (mirror design) is chosen to compare our
Leakage Feedback with Stack & Sleep Stack approach to the
other considered approaches for four different technologies.
The simulations table for 1-bit Full-adder is shown below in
table 2.
Fig. 8 Sleep Stack with Keeper approach
For For For For
Techniques (70 nm) (100 nm) (130 nm) (180 nm)
V. EXPERIMENTAL METHODOLOGY Base Case 3.86E- 8.90E- 2.29E- 6.35E-
08 08 07 07
In order to compare the results of our new approach with Sleep 1.20E- 3.87E- 8.85E- 2.27E-
prior leakage reduction approaches, experiments include all 08 08 08 07
the techniques discussed in Section 2, namely, stack, sleep, Zigzag 1.46E- 4.47E- 9.89E- 2.55E-
zigzag, sleepy stack and leakage feedback & sleepy-Keeper 08 08 08 07
approaches. In addition, we consider a base case and the Stack 1.49E- 4.24E- 9.74E- 3.08E-
newly proposed novel approaches, named “Leakage Feedback 08 08 08 07
with Stack” & “Sleep Stack With Keeper”. Sleepy-stack 1.79E- 1.34E- 1.34E- 3.75E-
08 07 07 07
Schematics are designed for all considered techniques using Sleepy- 1.64E- 5.45E- 1.27E- 3.63E-
Schematics Editor i.e S-EDIT in T-SPICE targeting TSMC keeper 08 08 07 07
0.18μm technology . Schematics are used to obtain netlists of Sleepy- 7.91E- 2.79E- 6.39E- 1.57E-
test circuits, and the netlists are used to simulate and test stack-keeper 09 08 08 07
performance. LF with 1.69E- 5.21E- 1.29E- 3.32E-
Stack 08 08 07 07
Schematics are created based on TSMC 0.18um process
Table 2. Avg. Power consumed in watts
parameters. Netlists of test circuits for different techniques are
extracted from the schematics. The netlists are modified to fit
Now we are showing the simulations results of 1-bit Full
into all silicon technologies targeted using the TSMC 0.18μm
adder circuit with four different technology generations for all
above discussed eight techniques ie. base case, sleep, zigzag,
stack, sleepy stack , leakage feedback and sleepy keeper
approaches with newly proposed approaches named “Leakage
Feedback with Stack” & “Sleep Stack With Keeper”. in
forms of graphs by which we can easily see the average power
consumed.
Fig. 9 Average power consumed chart for 70 nm
Fig. 9 Average power consumed chart for rest technologies
VII.CONCLUSION
From the analytical model of the sleepy stack inverter [ ],
we observe that the sleepy stack inverter can reduce delay by
25%, which alternatively can be used to increase Vth by 69%.
Using this increased threshold voltage, the sleepy stack
inverter can potentially achieve a large (e.g., 10X) leakage
power reduction compared to the forced stack inverter. Other
proposed technique is LEAKAGE FEEDBACK WITH
STACK EFFECT, it reduces power comparable to SLEEPY
STACK and it is also better area as well as delay. We are find
that the proposed technique i.e. SLEEPY- STACK with
KEEPER is the best technique for leakage power reduction.
But little bit Area and delay overhead but compared with
other power reduction techniques Like sleepy stack, it takes
less no. Of transistor, so because of this techniques has less
area than sleepy stack approach. It reduces almost 80% of
static or leakage power. For our future work, we plan to
investigate about the exact delay and area in these proposed
techniques.
REFERENCES
[1] International Technology Roadmap for Semiconductors by
Semiconductor Industry Association, http://public.itrs.net, 2007.
[2] S. Mutoh et al., “1-V Power Supply High-speed Digital Circuit
Technology with Multi-threshold-Voltage CMOS,” IEEE Journal of
Solis-State Circuits, Vol. 30, No. 8, pp. 847-854, August 1995.
[3] M. Powell, S.-H. Yang, B. Falsafi, K. Roy and T. N. Vijay kumar,
“Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep
submicron Cache Memories,” International Symposium on Low Power
Electronics and Design, pp. 90-95, July 2000.
[4] K.-S. Min, H. Kawaguchi and T. Sakurai, “Zigzag Super Cut-off
CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage
Level Controller: An Alternative to Clock-gating Scheme in Leakage
Dominant Era,” IEEE International Solid-State Circuits Conference,
pp. 400-401, February 2003.
[5] Z. Chen, M. Johnson, L. Wei and K. Roy, “Estimation of Standby
Leakage Power in CMOS Circuits Considering Accurate Modeling of
Transistor Stacks,” International Symposium on Low Power
Electronics and Design, pp. 239-244, August 1998.
[6] J.C. Park, V. J. Mooney III and P. Pfeiffenberger, “Sleepy Stack
Reduction of Leakage Power,” Proceeding of the International
Workshop on Power and Timing Modeling, Optimization and
Simulation, pp. 148-158, September 2004.
[7] J. Park, “Sleepy Stack: a New Approach to Low Power VLSI and
Memory,” Ph.D. Dissertation, School of Electrical and Computer
Engineering, Georgia Institute of Technology, 2005. [Online].
Available http://etd.gatech.edu/theses
[8] A. Kahng, S. Muddu, P. Sharma, “Defocus-aware leakage estimation
and control,” International Symposium on Low Power Electronics and
Design, pp. 263-268, Aug. 2005.
[9] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C.
Parthasarathy, E. Vincent, and G. Ghibaudo, “Review on high-k
dielectrics reliability issues,” IEEE Transactions on Device and
materials Reliability, Vol. 5, Issue 1, pp. 5-19, March 2005.
[10] K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge, “Drowsy
Caches: Simple Techniques for Reducing Leakage Power,”
Proceedings of the International Symposium on Computer
Architecture, pp. 148-157, May 2002
[11] KIM, N., AUSTIN, T., BAAUW, D., MUDGE, T., FLAUTNER, K.,
HU, J., IRWIN, M., KANDEMIR, M., and NARAYANAN, V.,
“Leakage Current: Moore’s Law Meets Static Power,” IEEE Computer,
vol. 36, pp. 68–75, December 2003.
[12] Berkeley Predictive Technology Model, http://www.eas.asu.edu/~ptm/.
[13] Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu., “New
paradigm of predictive MOSFET and interconnect modeling for early
circuit design,” Proceeding of IEEE Custom Integrated Circuits
Conference, pp. 201-204, June 2000.
[14] J. Kao and A. Chandrakasan, "MTCMOS sequential circuits,"
Proceedings of European Solid-State Circuits Conference, pp 332-
335, September 2001.