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Abstract- For the most recent CMOS feature sizes (e.g., 90nm Power consumption of CMOS consists of dynamic and
and 65nm), leakage power dissipation has become an overriding static components. Dynamic power is consumed when
concern for VLSI circuit designers. ITRS reports that leakage transistors are switching, and static power is consumed
power dissipation may come to dominate total power regardless of transistor switching. Dynamic power
consumption [1]. We are doing comparable analysis of different consumption was previously (at 0.18μ technology and above)
low power, leakage current reduction techniques like SLEEP
the single largest concern for low-power chip designers since
approach, STACK, ZIGZAG & some new techniques like ,
dynamic power accounted for 90% or more of the total chip
SLEEPY–STACK, LEAKAGE FEEDBACK approach and
SLEEPY KEEPER techniques. And , after That to combine the power. Therefore, many previously proposed techniques, such
advantages of above written techniques, we propose two novel as voltage and frequency scaling, focused on dynamic power
approaches, named “Leakage Feedback with Stack (LFS)” & reduction. However, as the feature size shrinks, e.g., to 0.09μ
“Sleep Stack With Keeper (SSK)” which reduces leakage and 0.065μ, static power has become a great challenge for
current while saving exact logic state. But Based on simulations current and future technologies. Based on the International
result with a full adder circuit, “Sleep-Stack with keeper Technology Roadmap for Semiconductors (ITRS) [1], Kim et
approach” achieves up to 76% less power consumption.
al. report that sub-threshold leakage power dissipation of a
chip may exceed dynamic power dissipation at the 65nm
Keywords—low power design, leakage reduction,
feature size [11].
sleep, stack, sleepy-stack, keeper.
One of the main reasons causing the leakage power increase
I. INTRODUCTION is increase of sub-threshold leakage power. When technology
feature size scales down, supply voltage and threshold voltage
Power consumption is one of the top concerns of Very also scale down. Sub-threshold leakage power increases
Large Scale Integration (VLSI) circuit design, for which exponentially as threshold voltage decreases. Furthermore, the
Complementary Metal Oxide Semiconductor (CMOS) is the structure of the short channel device lowers the threshold
primary technology. Today’s focus on low power is not only voltage even lower. In addition to sub-threshold leakage,
because of the recent growing demands of mobile another contributor to leakage power is gate-oxide leakage
applications. Even before the mobile era, power consumption power due to the tunneling current through the gate-oxide
has been a fundamental problem. To solve the power insulator. Since gate-oxide thickness will be reduced as the
dissipation problem, many researchers have proposed technology decreases, in nano-scale technology, gate-oxide
different ideas from the device level to the architectural level leakage power may be comparable to sub-threshold leakage
and above. However, there is no universal way to avoid power if not handled properly. However, we assume other
tradeoffs between power, delay and area, and thus designers techniques will address gate-oxide leakage; for example, high-
are required to choose appropriate techniques that satisfy k dielectric gate insulators may provide a solution to reduce
application and product needs. gate-leakage [11]. Therefore, this project work focuses on
reducing sub-threshold leakage power consumption.
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