PROBLEM STATEMENT: Write VHDL code and test bench, synthesis, simulate and

down load in to PLD to design programmable timer/counter.

OBJECTIVE:
1. To understand the concept of programmable timer/counter

THEORY:
The programmable timer/counter is designed as an UP/DOWN counter to the
maximum determined value. When counter reaches to the maximum value, it has to
reload from 0 again and then again counting processes. This UP/DOWN counting is
to be displayed on 7-segment display.

BLOCK DIAGRAM:

Clock

Reset

Fig.: 41 Programmable Timer/Counter
In this simple circuit, each LED segment of the common cathode display has its own
anode terminal connected directly to the 4511 driver with its cathodes connected to
ground. The current from each output passes through a 220 resistor that limits it to a
safe amount. The binary input to the 4511 is via the four switches. Then we can see that
using a BCD to 7-segment display driver such as the CMOS 4511, we can control the
LED display using just four switches .
ASSIGNMENT NO.4
TITLE: Synthesis, simulate and down load in to PLD to design
programmable timer/counter.
Programmable
Timer/Counter
Seven segment
decoder
Seven segment
display

Fig 4.2: BCD to seven segment display
Most digital equipment use 7-segment Displays for converting digital signals into a
form that can be displayed and understood by the user. This information is often
numerical data in the form of numbers, characters and symbols. Common anode and
common cathode seven-segment displays produce the required number by illuminating
the individual segments in various combinations. LED based 7-segment displays are
very popular amongst Electronics hobbyists as they are easy to use and easy to
understand. In most practical applications, 7-segment displays are driven by a suitable
decoder/driver IC such as the CMOS 4511 or TTL 7447 from a 4-bit BCD input. Today,
LED based 7-segment displays have been largely replaced by liquid crystal displays
(LCDs) which consume less current.
ALGORITHM:
SCHEMATIC DIAGRAM:
RTL SCHEMATIC:
I/O PORTS DETAILS:
SYNTHESIS REPORT:
TEST BENCH WAVEFORMS:

FAQ:
1. Write short notes on simulation and synthesis.
2. What is test bench? Describe synthesizable test bench and non synthesizable test
bench

CONCLUSION:









PROBLEM STATEMENT: To design CMOS inverter, calculate W/L ratios, prepare
layout in multi metal layers and simulate it. Assume suitable technology, load
capacitance, free running frequency, switching timings etc.

OBJECTIVE:
1.To understand the functional verification of the CMOS Inverter through
schematic entry.
2.To understand the pMos and nMOS characteristics
THEORY:

CMOS Inverter:
CMOS is also sometimes referred to as complementary-symmetry metaloxide
semiconductor. The words "complementary-symmetry" refer with CMOS uses
complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor
field effect transistors (MOSFETs) for logic functions. Two important characteristics of
CMOS devices are high noise immunity and low static power consumption. Significant
power is only drawn while the transistors in the CMOS device are switching between
on and off states. Consequently, CMOS devices do not produce as much waste heat as
other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which
uses all n-channel devices without p-channel devices
Inverter consists of nMOS and pMOS transistor in series connected between
VDD and GND. The gate of the two transistors are shorted and connected to the input.
When the input to the inverter A = 0, Nmos transistor is OFF and pMOS transistor is
ON. The output is pull-up to VDD. When the input A = 1, nMOS transistor is ON and
pMOS transistor is OFF. The Output is Pull-down to GND.

Fig.5.1: Inverter logic symbol and gate level model
ASSIGNMENT NO.5
TITLE: Prepare layout in multi metal layers for CMOS inverter,
calculate W/L ratios, and simulate it.
Inverter Static Characteristics (VTC):
Digital inverter quality is often measured using the Voltage Transfer Curve (VTC),
which is a plot of input vs. output voltage. From such a graph, device parameters
including noise tolerance, gain, and operating logic-levels can be obtained.

Fig.5.2: Voltage Transfer Curve for a typical 20 m Inverter
Ideally, the voltage transfer curve (VTC) appears as an inverted step-function - this
would indicate precise switching between on and off - but in real devices, a gradual
transition region exists. The VTC indicates that for low input voltage, the circuit outputs
high voltage; for high input, the output tapers off towards 0 volts. The slope of this
transition region is a measure of quality - steep (close to -Infinity) slopes yield precise
switching. The tolerance to noise can be measured by comparing the minimum input to
the maximum output for each region of operation (on / off).
Inverter Dynamic Characteristics:
The dynamic characteristics of a CMOS inverter. The following are some formal
definitions of temporal parameters of digital circuits. All percentages are of the steady
state values.

Fig.5.3: Dynamic characteristics of CMOS Inverter
ALGORITHM:

SCHEMATIC DIAGRAM:

STICK DIAGRAM:

SIMULATION RESULT:

TEST BENCH WAVEFORMS:


FAQ:
1. Define following term related to CMOS, FAN IN FAN OUT power dissipation
figure of merit
2. Draw block diagram and explain architecture of FPGA.


CONCLUSION:

























PROBLEM STATEMENT: To design CMOS NAND, NOR calculate W/L ratios,
prepare layout in multi metal layers and simulate it.

OBJECTIVE:
1. To understand the concept of CMOS NAND characteristics.
2. To understand the concept of CMOS NOR characteristics.
3. To perform the functional verification of the universal gate through schematic
entry.

THEORY:
NAND GATE DESIGN:



Fig.6.1: 2 input NAND gate schematic and truth table

In CMOS design, the NAND gate consists of two nMOS in series connected to two
pMOS in parallel. The schematic diagram of the NAND cell is reported below. The
nMOS in series tie the output to the ground for one single combination A=1, B=1. For
the three other combinations, the nMOS path is cut, but atleast one pMOS ties the
output to the supply VDD. Notice that both nMOS and pMOS devices are used in their
best regime: the nMOS devices pass 0, the pMOS pass 1.

NOR GATE DESIGN:
ASSIGNMENT NO.6
TITLE: Prepare layout in multi metal layers for CMOS NAND,NOR
calculate W/L ratios, and simulate it.



Fig.6.2: 2 input NOR gate schematic and truth table

In CMOS NOR gate circuit uses four MOSFETs just like the NAND gate, except that its
transistors are differently arranged. Instead of two paralleled sourcing (upper)
transistors connected to Vdd and two series-connected sinking (lower) transistors
connected to ground, the NOR gate uses two series-connected sourcing transistors and
two parallel-connected sinking transistors like given above. Each pair is controlled by a
single input signal. If either input A or input B are "high" (1), at least one of the lower
transistors (T3 or T4) will be saturated, thus making the output "low" (0). Only in the
event of both inputs being "low" (0) will both lower transistors be in cutoff mode and
both upper transistors be saturated, the conditions necessary for the output to go "high"
(1). This behavior defines the NOR logic function.

ALGORITHM:

SCHEMATIC DIAGRAM:

STICK DIAGRAM:

SIMULATION RESULT:

TEST BENCH WAVEFORMS:

FAQ
1. Write a short note on layout rules.
CONCLUSION: