SV8860 Datasheet

Copyright 2010 Skyviia Confidential PAGE.
1
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical,
including photocopying and recording, for any purpose, without the express written permission of Skyviia.

SV8860
FullHD Multimedia Processor

Preliminary Datasheet
Version 0.4
J une 29, 2010

Copyright 2010 Skyviia Confidential PAGE.2
Revision History

Version Date Description
Ver. 0.1 2009/3/14 Preliminary datasheet 1st Release
Ver. 0.2 2010/5/18 Add the electrical characteristics
Ver. 0.3
2010/6/24 Add more detailed description on each
block.
Ver. 0.4
2010/6/29 Modify and add feature descriptions
on GMAC , TSDMX, USB and audio
interfaces (I2S, AC97, SPDIF)
Ver 0.5
2010/7/22 Add 4KB boundary limitation for
DMA engine

Disclaimer
No part of this document may be reproduced or transmitted in any form or by any means,
electronic or mechanical, including photocopying and recording, for any purpose, without the
express written permission of Skyviia. Skyviia retains the right to make changes to this document
at any time, without notice. Skyviia makes no warranty of any kind, expressed or implied, with
regard to any information contained in this document, including, but not limited to, the implied
warranties of merchantability or fitness for any particular purpose. Further, Skyviia does not

Table of Contents
1. Description....................................................................................................................................... 7
2. Features ............................................................................................................................................ 8
2.1 CPU........................................................................................................................................ 8
2.2 Video ...................................................................................................................................... 8
2.3 Image...................................................................................................................................... 8
2.4 Audio Decode......................................................................................................................... 8
2.5 Storage/Memory Interface ..................................................................................................... 9
2.6 Display Controller.................................................................................................................. 9
2.7 LCD Interface ........................................................................................................................ 9
2.8 HDMI Output ......................................................................................................................... 9
2.9 Video Input/Output................................................................................................................. 9
2.10 Audio Output...................................................................................................................... 10
2.11 IR Input .............................................................................................................................. 10
2.12 2D Graphic Engine & Scalar ............................................................................................. 10
2.13 Gigabit Ethernet MAC....................................................................................................... 10
2.14 Transport Stream Demuxer ................................................................................................ 10
2.15 Others ................................................................................................................................. 10
3. Architecture.................................................................................................................................... 11
3.1 Central Processor ................................................................................................................. 11
3.2 PLLs ..................................................................................................................................... 11
3.3 Block Diagram & System Application Diagram.................................................................. 12
4. Multi-Format Video Decoder......................................................................................................... 14
5. Video Post Processing subsystem.................................................................................................. 17
5.1 Features ................................................................................................................................ 17
5.2 2D Graphics Engine............................................................................................................. 19
5.3 Scalar Engine & image enhancement .................................................................................. 20
5.3.1 Scalar Engine ............................................................................................................ 20
5.3.2 Color enhancement ................................................................................................... 21
5.3.3 Six-axis hue adjust .................................................................................................... 22
5.4 Video DAC........................................................................................................................... 22
6. DMA Controller ............................................................................................................................. 22
General Description ........................................................................................................... 22
Register Definition............................................................................................................. 23
7. Storage Controller .......................................................................................................................... 23
7.1 SATA II Controller ............................................................................................................... 23
7.2 SD/MMC Card Reader......................................................................................................... 25
7.3 MS-Pro/MS-Pro HG Card Reader ....................................................................................... 25
8. DDR2 SDRAM Controller............................................................................................................. 26
9. Flash Controller.............................................................................................................................. 26
9.1 NOR Flash............................................................................................................................ 26
9.2 NAND Flash ........................................................................................................................ 26

10. USB Controller ............................................................................................................................ 27
10.1 USB 2.0 Host/Device Controller ....................................................................................... 27
10.2 USB 2.0 Host Controller.................................................................................................... 27
11. Transport Stream Demuxer .......................................................................................................... 29
11.1 Features : ............................................................................................................................ 29
11.2 System Block Diagram : .................................................................................................... 29
12. 8051 Subsystem........................................................................................................................... 30
13. External Interface......................................................................................................................... 31
13.1 I
2
S Interface........................................................................................................................ 31
13.2 General Purpose Input/Outputs (GPIO)............................................................................. 35
13.3 IR Decoder ......................................................................................................................... 35
13.4 I
2
C Interface ....................................................................................................................... 35
Feature................................................................................................................................ 35
13.5 JTAG.................................................................................................................................. 35
13.6 UART................................................................................................................................. 35
13.7 SAR-ADC.......................................................................................................................... 35
13.8 RTC.................................................................................................................................... 35
14. Gigabit Ethernet MAC................................................................................................................. 36
15. Video Output Interface................................................................................................................. 37
15.1 Analog Video Output ......................................................................................................... 37
15.1.1 TV Encoder ............................................................................................................. 37
15.1.2 YPbPr ...................................................................................................................... 37
15.2 Digital Video Output .......................................................................................................... 37
15.2.1 CCIR-601................................................................................................................ 38
15.2.2 CCIR-656................................................................................................................ 38
15.2.3 24-bit RGB with TCON.......................................................................................... 38
15.2.4 HDMI with HDCP.................................................................................................. 38
15.3 Digital Video Input............................................................................................................. 40
16. Timing Controller......................................................................................................................... 40
17. Pin Information ............................................................................................................................ 42
17.1 Pin Layout .......................................................................................................................... 42
17.1.1 Left .......................................................................................................................... 43
17.1.2 Right........................................................................................................................ 44
17.2 Pin Listing by Ball Id......................................................................................................... 45
17.3 Shared Pin for Card Readers.............................................................................................. 56
17.4 LCD/Digital RGB/CCIR656 Input Mux Pins.................................................................... 57
17.5 GPIO Pin List and Address Define .................................................................................... 58
17.5.1 GPIO Pin Group List............................................................................................... 58
17.5.2 GPIO Pin Group Address Define............................................................................ 59
17.5.3 GPIOH Pin Group Pin List ..................................................................................... 60
17.5.4 GPIOH Pin Group Address Define ......................................................................... 61
17.5.5 GPIO2 Pin Group List............................................................................................. 62
17.5.6 GPIO2 Pin Group Address Define.......................................................................... 63


17.5.7 GPIO3 Pin Group List............................................................................................. 64
17.5.8 GPIO3 Pin Group Address Define.......................................................................... 65
17.5.9 EGPIO Pin Group List ............................................................................................ 66
17.5.10 EGPIO Pin Group Address Define........................................................................ 66
17.5.11 MGPIO Pin Group List ......................................................................................... 66
17.5.12 MGPIO Pin Group Address Define ...................................................................... 66
18. System Specifications .................................................................................................................. 67
18.1 DC Characteristics ............................................................................................................. 67
18.1.1 Power Supply.......................................................................................................... 67
18.1.2 Recommended I/O Pad Operating Conditions........................................................ 67
18.1.3 I/O Pad Capacitance................................................................................................ 67
18.2 AC Characteristics.............................................................................................................. 67
18.2.1 Power On Sequence ................................................................................................ 67
18.2.2 Reset and System Clock Timing............................................................................. 68
18.3 Power consumption............................................................................................................ 69
18.3.1 Standby mode.......................................................................................................... 69
18.3.2 Normal mode........................................................................................................... 69
19. Package Information .................................................................................................................... 70

List of Figures

Fig. 1 Block Diagram of ARM926EJ-S.......................................................................................... 11
Fig. 2 SV8860 Functional Block Diagram...................................................................................... 13
Fig. 3 Typical System Application Diagram .................................................................................. 13
Fig. 4 Block Diagram of Video Decoder & video post processor .................................................. 14
Fig. 6 Functional Block Diagram of USB 2.0 Host Controller....................................................... 28
Fig. 8 Functional Block Diagram of HDMI with HDCP................................................................ 39
Fig. 9 Reset and System Timing Diagram...................................................................................... 68
Fig. 10 432-pin TFBGA (19m x 19mm x 1.6mm) Package Outline Diagram............................... 70
Fig. 11 432-pin TFBGA (19mm x 19mm x 1.6mm) Package Mechanical Information ................ 71
Fig. 12 432-pin TFBGA (19mm x 19mm x 1.6mm) Ball Map ...................................................... 72

List of Tables

Tab. 1 SV8860 Video Decoder supported bit rate and size............................................................... 17
Tab. 2 SV8860 YPbPr Output Format ............................................................................................... 37
Tab. 3 SV8860 integrated timing controller support resolution ........................................................ 41
Tab. 4 SV8860 Pin Assignment list ................................................................................................... 55
Tab. 5 SV8860 Shared Pin for Card Readers..................................................................................... 56
Tab. 6 SV8860 LCD/Digital RGB/CCIR656 Input Mux Pins........................................................... 57

1. Description

The SV8860 is a highly integrated single chip multimedia processor targeting at high-end system
solution. It is capable of decoding multi video format up to 1920x1080p@30fps such as H.264,
VC-1, RealVideo, VP6, MPEG-1/2/4, DivX4/5/6, Sorenson, and MJPEG etc. Its image decoding
capability can decode various formats as JPEG, BMP, GIF, TIFF, PNG, and RAW without file
sizes limitation. The SV8860 also supports audio processing on MP3, WMA, WAV, AMR, AAC,
OGG-Vorbis, PCM/ADPCM, AC-3, DTS, RealAudio, and DD+ formats with sound output
including SPDIF, I2S or AC97 interface. The supporting file formats can be played-back without
transcoding the contents. Product designed around the SV8860 will provide high-quality video,
image, and audio decoding capability while maintaining high flexibility for upgrading to the latest
codec standards.

SV8860 is implemented based on a 32-bit RISC CPU (ARM926EJ-S) with programmable parallel
processing architecture to optimize performance, power and area. In addition to the supreme CPU
core which is the central part for all decoding algorithms and providing maximum flexibility,
SV8860 also offers easy-to-use peripheral interfaces, such as USB 2.0 host and device controller,
memory card interfaces (SD3.0/MMC4.3, MS/MS-Pro/MS-Pro HG, ...etc.).
Integrated HDMI Tx(v1.3a) provides a full HD(1920x1080p) video/audio TV output and SV8860
also supports digital video interface such as CCIR656/601, RGB888. With multi-layer true color
On-Screen-Display (OSD) controller, users can change and activate features/functions by using
set-up menu easily.
2D (Texture) graphic engine of SV8860 can provide various fancy UI(user interface) for customers.
The SV8860 is available in 432-pin TFBGA industry standard package.

l 1.2V internal , 1.8V memory, 3.3V external I/O
l DDR II DRAM controller and chip select logic
l LCD controller with resolution up to 1920 x 1080
l HDMI (v1.3a) / Component / Composite TV out
l 7-ch DMA
l 2-ch UART
l 1-ch SPI
l 2-port USB Host / 1-port USB Host/Device
l 4-ch PWM
l Watch Dog Timer
l 10-ch 10-bit SAR ADC for Touch Panel/Touch Pad
l RTC with Calendar function
l On-chip clock generator PLL

2. Features
2.1 CPU
q ARM926EJ-S 16Kbytes I-Cache/16Kbytes D-Cache running up to 400MHz
q MMU to support virtual memory and various OS platform
q Support Linux2.6 and Android

2.2 Video
q M-JPEG, up to 1920x1080p resolution, 30fps, BP
q MPEG-1 compliant ISO/IEC 11172-2 criteria
q MPEG-2, up to 1920x1080p resolution, 30fps, MP(HL)
q MPEG-4, up to 1920x1080p resolution, 30fps, SP/ASP L5.0
q H.263, up to 720x576p resolution, 30fps, Profile 0, Level 10~70
q H.264, up to 1920x1080p resolution, 30fps, BP(L4.1)/MP(L4.1)/HP(L4.1)
q VC-1, up to 1920x1080p resolution, 30fps, SP(L3.0)/MP(L3.0)/AP(L3.0)
q DivX, up to 1920x1080p resolution, 30fps, Ver. 4.x/5.x/6.x
q Xvid, up to 1920x1080p resolution, 30fps
q RealVideo, up to 1920x1080p resolution, 30fps, Ver. 8/9/10
q VP6, up to 1920x1080P resolution, 30fps, Simple and Advance Profile.
q Sorenson Spark, up to 1920x1080P resolution, 30fps
q Area based Deinterlacer

2.3 Image
q JPEG
l Maximum JPEG decode capability 48x48 up to 8176x8176, 67Mpixel
l Fast JPEG hardware decode capability 40Mpixel<1sec
l Support baseline and 420 422 444 format decode
q BMP
q GIF
q TIFF
q PNG
q RAW (Adobe DNG is default format)
q Special Features
l Zoom in / out
l Picture Slide Show ! Sequential / Random
l Thumbnail Modes (thumbnail images displayed at the same time)
l Hardware Rotation 90" / 180"/ 270" , Mirror/Flip
l Photo show with user-defined background music

2.4 Audio Decode
q MP3, all formats
q HEAAC/HEAAC v2/AAC-LC (MPEG-4, Part-3)
q OGG Vorbis
q PCM / ADPCM
q AMR
q Real Audio
q Dolby Digital (AC-3)
q DTS 5.1
q WMA
q WMA Pro

2.5 Storage/Memory Interface
q USB
l Two USB 2.0 Host
l One USB 2.0 Host/Device (could be configured as Host or Device by hardwire)
q SATA-II Interface
l SATA-II: 1.5 Gbps/3.0 Gbps compliant with revision 2.5 specification
q Memory Card
l Two SD 3.0 card supported (backward compatible to SD 2.0, SD 1.1)
l MMC 4.2 card (backward compatible to MMC 3.x)
l MS-Pro (v1.03) / MS-Pro HG(v1.01) card
q DDR2 DRAM
l Support 2 channels 16-bit DDR2-800 DRAM
l Each channel can support 128Mb/256Mb/512Mb/1Gb/2Gb DRAM type
q NAND Flash
l Support 2 CE
l Support x 8 / x16 data width
l Support all kinds of NAND vendors (SLC/MLC) : Samsung, Hynix, Micron, Intel and STM
l Support program boot-up from NAND
q NOR Flash
l Support SPI bus compatible serial interface NOR type Flash

2.6 Display Controller
n Primary and secondary video/image sources
n 5 Color-indexed non-overlapping OSD blocks, ARGB1232 format.
n YCbCr 422/420, RGB888, RGB565, ARGB8888 Video/Image format
n Support per-pixel alpha blending
n Image/Video Scaling up/down
n Contrast/Brightness/Sharpness adjustment
n Hue/Saturation adjustment
n Gamma correction with per channel gamma table
n Hardware cursor up to 32x32 pixels
n Ordered Dither
n 6-axis color adjustment
n Anti-flicker

2.7 LCD Interface
q Support LCD with parallel digital RGB888 interface (up to 24-bit)
q CCIR 601/656 digital output
q Built-in digital T-con up to WUXGA(1920x1080) LCD panel
q Up to 2 PWM outputs for backlight control circuit

2.8 HDMI Output
q Support HDMI v1.3a Tx
q Support HDCP
q Support CEC(Consumer Electronics Control) bus

2.9 Video Input/Output
q Analog
l Composite (CVBS) output for NTSC / PAL
l S-Video output for NTSC / PAL

l YPbPr component output for SDTV / HDTV, up to 720p and 1080i /1080P
l Analog RGB D-SUB output
q Digital
l CCIR-601/656 digital output
l CCIR656 digital input
l D-sub output

2.10 Audio Output
q I2S/AC97/SPDIF interface to external audio codec

2.11 IR Input
q The infrared input allows interfacing to an external IR receiver

2.12 2D Graphic Engine & Scalar
q Bitblt, ROP256, pattern fill, line draw, parallelogram, transparent/color-key, alpha blending
q Support multilayer true color OSD
q 2D engine
q Scalar Horizontal/Vertical up to 4x with edge enhancement
q Scalar down 6 taps programmable FIR
q Scalar engine

2.13 Gigabit Ethernet MAC
r Support big/little endian data bus type
r Large embedded SRAM for packet buffers
l 32K bytes for receive buffer
l 8K bytes for transmit buffer
r Support IP/TCP/UCP checksum offloads
r Support interrupt with high or low active trigger mode
r Compatible with IEEE802.3, 802.3u, and 802.3ab standards
r Support 10/100/1000Mbps data rate
r Support full and half duplex operations with 10/100Mbps data rate
r Support 10/100/1000Mbps N-way Auto-negotiation operation
r Support IEEE802.3x flow control for full-duplex operation
r Support 10/100/1000Mbps data rate with RGMII or MII in 10/100Mbps data rate
r Support back-pressure flow control for half-duplex operation
r Support 4K bytes JUMBO packet

2.14 Transport Stream Demuxer
q Compliant DTV standards
l ISO/IEC 13818-1:2000
l DVB: ETS 300 428 v.1.4.1
l ARIB: STD-B32 Part 3
q Transport stream input interface
l Configurable 8-bit parallel or serial input interfaces
l Mulit2 descramble for ISDB
l CSA descramble for DVB

2.15 Others
q AP/SW/FW upgradeable via USB port or SD card host
q Embedded 8051 enabled by main CPU for power management and IR control

q RTC (Real Time Clock)
q Supply power: 1.2V for core, 1.8V for RAM I/O and 3.3V for other I/O ports
q Package : 432-pin EBGA lead-free Package

3. Architecture

3.1 Central Processor
SV8860 utilizes a high performance 32-bit RISC CPU engine ! ARM926EJ-S with 16KB I-cache
and 16KB D-cache memory. ARM926EJ-S#s patented configurable architecture results in higher
performance and lower power consumption.

Please refer to the implementation diagram of ARM926EJ-S as below:

Fig. 1 Block Diagram of ARM926EJ-S

3.2 PLLs
The SV8860 has 6 sets of built-in PLLs to provide the required working frequency for each block. It
has clock multiplier to drive internal logic with desired frequency. As to the function of each PLL,
it is described as following:
q PLL0 ! generate CPU master clock and bus clocks
The PLL0 takes 27MHz input and generates 10 to 15 times of frequency for ARM926EJ-S. This
PLL output clock will be used to generate AHB and APB clocks as well. The default frequencies
for ARM926EJ-S and buses are
ARM926EJ-S = 405 MHZ
AHB1 Bus = 202.5 MHZ
AHB2 Bus = 101.25 MHZ
APB Bus = 50.625 MHZ

However, the clock frequencies of ARM926EJ-S and buses could be adjustable through the proper
register setting.

q PLL1 ! generates video output clock
The PLL1 generates video output clock. With 27MHz input, it can generate clocks for various video
standard output. For example, 27MHz video clock is used for NTSC TV 480i output, 74.25MHZ
video clock is used for 720p/1080i HD output and 148.5MHz video clock is used for 1080p Full
HD output.

q PLL2 ! generates audio clock
The PLL2 generates audio output clock. It can generate various audio output frequencies from
32KHZ, 44.1KHZ, to 48KHZ, 96KHZ and so on.

q PLL3 ! generates video decoder clock
The PLL3 generates the clock for the hardware video decoder engine. It can generate various output
frequencies to support different video streams with different frame rates and resolutions to save the
system power consumption.

q PLL4 ! generates DDR-2 clock
The PLL4 generates the clocks for AXI bus, DDR2 controller and DDR2 PHY. The default
frequencies are
AXI Bus = 195.75 MHZ
DDR2 Controller = 195.75 and 391.5 MHZ
DDR2 PHY = 391.5 and 783 MHZ

q PLL5 ! generates USB clock
The PLL5 generates 48MHZ for USB PHY from the input 27MHZ crystal. Then USB PHY will
generate 60MHZ clock for USB Host/Device controllers.

3.3 Block Diagram & System Application Diagram
Fig.1 shows the functional block diagram for SV8860 and Fig.2 depicts a simple system connection
diagram for customer to have a quick reference.


Fig. 2 SV8860 Functional Block Diagram

(a) HD Media Player (b) IPTV

Fig. 3 Typical System Application Diagram

4. Multi-Format Video Decoder
SV8860 implements a hardware multi-format video decoder and its decoding capability up to Full
HD (1920x1080p@30fps). While for internet access, SV8860 also support all the Adobe Flash
Video codecs : Sorenson Spark, H.264 and ON2 VP6, which enable watching hundreds of video
web sites, such as YouTube, Google Video and Yahoo! Video.

Fig. 1 Block Diagram of Video Decoder & video post processor




Video Decoder Maximum bit rate Supported Video Size
H.264 57.2 Mbps 48x48 to 1920x1080
Real Video 38.4 Mbps 48x48 to 1920x1080
MPEG 4 38.4 Mbps 48x48 to 1920x1080
H.263 38.4 Mbps 48x48 to 720x576
Sorenson Spark 38.4 Mbps 48x48 to 1920x1080
DivX 38.4 Mbps 48x48 to 1920x1080
MPEG-2/MPEG-1 80 Mbps 48x48 to 1920x1080
VC1 45 Mbps 48x48 to 1920x1080
VP6 57 Mbps 48x48 to 1920x1080
Tab. 1 SV8860 Video Decoder supported bit rate and size

5. Video Post Processing subsystem

5.1 Features
The post-processor (PP) features are described in the following Table. It is possible to run the
post-processor combined with the decoder, or as a stand-alone IP block, when it can process image
data from any external source. Using combined mode reduces bus bandwidth, as PP can read its
input data directly from the decoder output without accessing external memory. The
post-processor output image can be alpha blended with two rectangular areas. If alpha blending is
used in combined mode, the currently decoded image will be set as the background image. Alpha
blending can be used for creating transparent menus, subtitles and logos on top of the video
playback. These overlay regions must be in the same color space, YCbCr or RGB, as the target
format of the post-processor output image. If the two areas for alpha blending overlap, the second
area overrides the first (the first area content is discarded). Alpha blending increases the bus load.

Note: In addition to the features listed next, the post-processor also takes care of the VC-1 features
range mapping and multi-resolution coding.

Post Processor Features :



5.2 2D Graphics Engine

2D engine supports the following features up to 2048 X 2048 resolution:
q Linear addressing
q Support YCbCr to RGB color space converter
q Support command queue mode to program graphics 2D engine
q BitBLT
n Bit block transfer(BitBLT)
n BitBLT direction: Right left, bottom top
n Rectangle Fill

n Pattern Fill (8x8)
n Color Key, Chroma Key, Transparent, alpha-blending
n 256 3-operand ROPs
n Bresenham Line Drawing
n Shearing
q Alpha Blending
q Rotation function
n rotation(90, 180, 270)
n mirror, flip

Formats for three associated data for 2D :
n Source, Destination
u Input image
l Source1/source2 image
n YCbCr420
n 32bpp: ARGB8888
n RGB565
l Destination image
n 32bpp: ARGB8888
n RGB565
u Output image
l Destination image
n 32bpp: ARGB8888
n RGB565
n Pattern
u 8x8 bitmap in any color depth

5.3 Scalar Engine & image enhancement
5.3.1 Scalar Engine
There are two scalars in SV8860. One is in video post processor engine. This scalar is mainly
used to scale down MegaPixel JPEG image or HD video to a smaller output resolution to save the
system memory bandwidth. It supports up to three times enlargement with good image quality.
Scalar engine is up to 3X, and downsizing is unlimited, etc. There is another scalar engine in the
display controller which is mainly used to scale up the input image/video to full HD resolution for
component or HDMI output. Besides, this scale will be used for TV overscan adjustment as well.
It could scale up the input image/video up to 4X and scale down to 1/2.

The scalar up algorithm can scale up a source image from one time to four times size of source
image. If the ratios of scaling up in vertical and horizontal direction are both more than two, we
adapt median algorithm to scalar up image size to (source image width *2 !1 ) * (source image
height*2 !1) and then perform bilinear algorithm. Otherwise, we only adapt the bilinear algorithm.
The following shows that overall algorithm of scaling up in luma and chroma path. In luma path,
we will do sharpness algorithm first. If the ratio is more than two, we will adapt median algorithm.
Finally, we perform bilinear algorithm. In chroma path, we only perform bilinear algorithm.


As to the scaling down engine, here is the supported feature list:
q Support image scale down with adjustable filter coefficient.
q Horizontal 6-tap FIR filter and vertical 2-tap FIR filter.
q Support maximum input image dimension: 1920x1080
q Support up to 31x scale down.

5.3.2 Color enhancement
Enhance image color in 1-D pixel operation. This image enhancement includes color hue,
chrominance saturation, contrast and brightness change

q Hue, Saturation

[ ] [ ]

=
) cos( ) sin(
) sin( ) cos(
128
_

Value Saturation
Cr Cb r C b C

[ ] [ ] [ ] ( ) [ ] 128 128
) cos( ) sin(
) sin( ) cos(
128
_
128 128 +

=

Value Saturation
Cr Cb r C b C
Where
256
360 _
=
Value Hue

Brightness

128 _ ' " + = Value Brightness Y Y

Contrast
When contrast_value < 128
( )
256
128 _
' "
+
+ =
Value Contrast
Y Y

When contrast_value > 128
128
_
' "
Value Contrast
Y Y + =

q Gamma correction
Gamma correction is a non-linear adjustment to the value to match the output more closely to the
original image. SV8860 uses RAM based look-up table for gamma correction for each R/G/B
channel independently.

5.3.3 Six-axis hue adjust
SV8860 offers a function for user to adjust the output color hue in Red / Green / Blue / Yellow /
Magenta / Cyan domain independently.

5.4 Video DAC
SV8860 embeds a high performance 10-bit Video DAC. Its working frequency is up to 220MHz for
Video and Graph applications. There are 3-channels 10-bits DAC with embedded band gap
reference block. Each of them receives 10 bits digital input then converts to the corresponding
output current to the load. The main features of this block are listed as follows:
q Dual power supply : Digital: 1.2V; Analog: 3.3V
q 10-bit input, input clock frequency is up to 220MHz
q 0V ~ 1.318V/0-35.16mA analog output range

6. DMA Controller
There are 7 DMA channels in SV8860. The DMA controller significantly increases system
performance by performing data movements between system memory, and peripherals for audio,
memory card, SATA, GMAC, etc. Besides, DMA controller could be used together with
command queue to achieve scatter gathering DMA to further improve the system performance.
General Description
q Source and destination can be select from 64bits AXI DRAM and 32bits AHB bus.
q Support 2 channels DMA. (I2S, Card Read and memory block transfer)

q For every channel has a separate feed and sink state machine can access to two different system
bus at the same time (AHB & AXI).
q Write the register $DMA Byte Size[17:3]% with one none zero value will trigger a new DMA
operation (Writing zero value may cause unknown H/W actions with unwanted results.).
q $Source/Destination address% should be 4-byte aligned.
q $DMA Byte Size% should be 8-byte aligned.
q If the DMA start-address and end-address are in different DDR DRAMs, there is a 4KB
boundary limitation. That means you cannot set up the DMA engine to cross DRAM size
boundary.
q Support list:
Channel
DRM
inside
CMDQ
scatter
SATA
channel
CardReader
I2S channel
DMA APB
start address
DRM APB
start
address
CMDQ
cmdq_addr[8:6]
interrupt
DMA0 O O O C0FC_1200 3'b000 int11
DMA1 O O O C0FC_1240 3'b001 int23
DMA2 O O O C0FC_1280 3'b010 int31
DMA3 O O C0FC_12C0 C0FC_9600 3'b011 int1
DMA4 O O O C0FC_1600 3'b100 int13
DMA5 O O O C0FC_1640 3'b101 int19
DMA6 O O O C0FC_1680 3'b110 int30
*Channel 0~2, 4~6 are general DMAs.
*Channel 3 has a DRM engine inside and it does not support SATA 2 operations.
Register Definition
Channel 0 base address: 0xC0FC1200
Channel 3 base address: 0xC0FC12C0

7. Storage Controller

7.1 SATA II Controller
Serial ATA (SATA) is a high-speed serial link replacement for the parallel ATA attachment of
mass storage devices. The serial link employed is a high-speed differential layer that utilizes
Gigabit technology and 8b/10b encoding.
SATA is a half-duplex system. Either a receive or transmit operation is performed between the two
agents (host and device) at any given time, but no both. This is true only for data frames transfer.
Control traffic (primitives) is full duplex to maintain receiver synchronization.
The SV8860 implements the Serial Advanced Technology Attachment (SATA) storage interface for
physical storage device. The SV8860 consists of three main functional blocks: Bus interface,
Transport Layer, and Link Layer. Together with the physical layer (PHY) it forms a complete Serial
ATA (SATA) host adapter interface.



7.2 SD/MMC Card Reader
Support 2 sets SD/MMC card slots. These two interfaces have separate SDCLK and DATA pins and
allow system accessing each card individually.
q Support SD3.0/MMC4.3 1/4/8 bit mode
q 1-bit SD data transfer mode
q 4-bit SD data transfer mode
q Support automatic CRC16 generation and verification on DAT
q Process data in block or byte

7.3 MS-Pro/MS-Pro HG Card Reader
q Memory Stick Pro (ver.1.03-00)
q Memory Stick Pro HG (ver. 1.01-00)
l Support 2KB access mode
q Support 1bit and 4bit data bus
q The maximum of host clock frequency
q ECLK (External CLK) depends on CPU speed.
q Select HCLK frequency. (HCLK = ECLK or ECLK/2,4,8,16,32,64,128,256)
q HCLK stops in BS0
q Support 1bit and 4bit data bus
q 7 byte data registers for SET_RW_REG_ADRS TPC, WRITE_REG TPC, READ_REG TPC,
GET_INT TPC, SET_CMD TPC and EX_SET_CMD TPC

8. DDR2 SDRAM Controller
The SV8860 uses an external DRAM for data storage. The DRAM can be DDR2 SDRAM. The
SV8860 DRAM controller employs synchronous design scheme so that CPU and DRAM working
frequency can be in-phase. This scheme minimizes time delay and facilitates memory retrieving
process.

DDR2 SDRAM Controller Feature:
q Two 16-bit DRAM controller
q Double data rate synchronous DRAM (DDR2-800)
q Support A0 ! A14 address bits rows devices
q Support 8 banks of SDRAM devices
q Support A0 ! A9 address bits column devices
q Data path widths 32 bits or 16bits
q Support up to 2 channels 512MB external DDR2 SDRAM

9. Flash Controller
9.1 NOR Flash
The SV8860 supports SPI bus compatible serial interface NOR type Flash. (ex. S25FL016A) Direct
connect HOLD# to high and the bus mode is CPOL=0, CPHA=0.

9.2 NAND Flash
Featuring Skyviia#s proprietary know-how, SV8860#s NAND interface supports direct access to
different NAND type flash provided by major NAND manufacturers. The main features are
summarized as follows:
q Varieties of Supported NAND :
l SLC and MLC from Samsung, Hynix, Intel, Micron and STM
q Support up to 2CE pins, up to 4 NAND chips
q 24-bit error correction code(ECC) capability tailored for MLC NAND
q Proprietary wear-leveling algorithm to lengthen the MLC life time

Block Diagram of Card Interfaces

10. USB Controller

There are three USB ports in SV8860. Two of them are configured as USB2.0 Host and one of
them could be configured as USB2.0 Host or Device on the system board.

10.1 USB 2.0 Host/Device Controller
SV8860 integrates a USB2.0 OTG controller and PHY macro together which can communicate
with USB host device directly. It links to USB cable via USB2.0 Transceiver Macrocell Interface
(UTMI), which is a specification for USB2.0 physical layer transceiver defined by Intel. The
application buses of this controller runs on a 60MHz clock The built-in USB controller with PHY
are with the following main features:
q Complies with USB spec. Rev2.0 (transfer speed up to 480Mbps, backward compatible with
USB1.1)
q Complies with USB Mass Storage Class specification Rev1.0

10.2 USB 2.0 Host Controller
In addition to USB2.0 OTG controller with PHY, two USB2.0 host controller was also integrated to
support USB standard version 2.0. It is designed to be interfaced with the physical layer of the
Universal Serial Bus. It is capable of transmitting and receiving serial data both at high speed
(480Mbps) data rates.


DMA Controller uP Interface
Register Files
(Operation Registers,
Port Registers)
Bus Monitor Parallel Interface Engine
Port Status &
Control Signals
iTD/siTD
Data
Structure
QH Data
Structure
Periodic Schedule
Processing State
Machine
Asynchronous
Schedule
Processing State
Machine
Host Controller
FIFO
byte_count
FIFO Controller
1K SRAM
FIFO
Transcation Level
Control Signals
DMA
Control
Signals
Data
Structure
Stream
32
USB
Data
Stream
32
Operation
Control
Signals
AHB Bus
UTMI+ Level 2 PHY

Fig. 2 Functional Block Diagram of USB 2.0 Host Controller


11. Transport Stream Demuxer

11.1 Features :
q Compliant DTV standards
n ISO/IEC 13818-1:2000
n ATSC: A-65B
n DVB: ETS 300 428 v.1.4.1
n ARIB: STD-B32 Part3
q Processing one transport stream from external TS tuner or main memory.
q Support 64 filters to filter out packet with specific PID
n Filter0~2: used as PES filter
n Filter3~15: used as PES filter or PSI filter (with version filter)
n Filter16~63: used as PSI filter (with version filter and table ID filter)
q Each PES/PSI with the same PID is send to the one individual ring buffer.
q Support one picture forming engine to convert video PES into ES and split the ES at picture
boundary.
q One Adaptation Field extractor to extract PCR or capture entire AF to main memory.
q Support decryption engines for ISDB and DVB.
n ISDB - Multi2
n DVB - CSA
q Support section data CRC checking.
q Packet loss detection via continuity counter checking and packet length checking.
q $System Time Clock% recovery via extract PCR and load it to local system time clock reference
to alleviate the loading of processor.
q TS sync byte identification and TS sync checking for every packet.
q Support both parallel and serial TS tuner interface.
q Support programmable TS packet length.
q Support pattern matching scheme to alleviate the loading of processor when searching key frame
or other start code oriented application.
q Support recording engine to record input TS stream or descrambler output stream.

11.2 System Block Diagram :


TSDMX core parses TS data from external tuner or AXI bus. The parsed PSI & PES data will be
sent to AXI bus in a ring buffer structure for further process. TSDMX Core consist of 64 filters,
each filter can parse out TS packets with a programmable PID. TSDMX core operate at 27Mhz with
8 bit data bus width, thus, it is capable of parsing TS stream up to 216Mb/s.
Input-interface is in charge of converting ring structure Video PES into video ES. Each frame
of video ES occupies a continuous space in DDR. PES header is also parsed out and reported in
related registers.

12. 8051 Subsystem

8051 subsystem block diagram

8051 subsystem is used to control the user interfaces, including IR, SAR ADC & GPIO, and other
interfaces such as CEC & smart card. It is responsible for the system power management as well.
While in standby mode, 8051 could turn off the external power for the main parts of SV8860 to
lower the power consumption. Besides, 8051 could power down CPU PLL and reset
ARM926EJ-S through control registers.

q Default $halt51% is enabled, all system bus is switch to ARM926 used. ARM926 use this
interface to fill 8051#s program and data RAM first. Then disable $halt51% to enable normal
8051#s normal operation.
q $Mail Box to 51 4bytes% is an ARM926 send command to 8051 data path. It can only be written
by ARM926 and only be read by 8051. The valid bit is set when ARM926 write the latest byte
and is clear when 8051 read the latest byte. There are two another interrupt masks to inform
ARM926 or 8051 the valid status.
q $Mail Box to ARM 4bytes% is an 8051 send response status to ARM926 data path. It can only be
written by 8051 and only be read by ARM926. The valid bit is set when 8051 write the latest
byte and is clear when ARM926 read the latest byte. There are two another interrupt masks to
inform ARM926 or 8051 the valid status.
q The Mail Box contains or definition can be free defined by firmware. If more than 4 bytes is
need for application, firmware can define continue or others in the 4 bytes contains.


13. External Interface

13.1 I
2
S, SPDIF and AC97 Interfaces
The audio block includes three block: (1) AC97: the Audio Codec '97 Component Specification
2.3 for AC-link format. (2) I2S: Inter-IC Sound is a serial link protocol defined by Philips
Semiconductor. (3) SPDIF: Sony/Philips Digital Interconnect Format is standardized in IEC 60958
where it is known as IEC 60958 type II.
AC97, I2S, and SPDIF support input and output interface. The audio data can be transmitted
from system memory to pcmo fifo or from pcmi fifo to system memory through DMA to improve
performance. The I2S current implementation supports both master and slave modes and up to 7.1
channels output. Normal I2S and the Left-Justified, Right-Justified I2S format are supported.

Features :
q Support I2S, SPDIF, and AC97 in/out interface
q DMA transfer mode supported
q I2S support mono, 2 channels (stereo), 6 channels (5.1ch), and 8 channels (7.1ch)
q Support I2S and SPDIF output through HDMI
q Master/Slave mode selectable for I2S
q I2S support Left-Justified; I2S, Right-Justified I2S data formats
q 16/20/24-bit data per channel
q 32/48/64/192/256-Fs serial bit clock, where Fs is sampling frequency
q 192/256/384/512/768-Fs master cock

13.1.1 External Interface Connection
I2S format:


AC97 format:

13.1.2 Detailed Block Diagram


13.1.3 Timing diagram

q I2S:
For I2S format, data is presented most significant bit first, one BCLK delay after the transition
of LRCLK, and is valid at the rising edge of BCLK. For the I2S format, the left channel is presented
when LRCLK is low and the right channel is presented when LRCLK is high. The I2S format can
also be programmed for data to be valid at the falling edge of BCLK. There are left justified I'S
streams, where there is no bit clock delay and the data starts right on the edge of the word select
clock, and there are also right justified I'S streams, where the data lines up with the right edge of the
word select clock. These configurations however are not considered standard I'S.

q SPDIF:
The SPDIF signal format is shown in following figure.

A PCM signal is transmitted in sequential blocks. Each block consists of 192 frames. Each
frame contains two sub-frames, one for each channel. Each subframe is preceded by a preamble.
There are three types of preambles: B, M and W. Preambles can be spotted easily in an SPDIF

bitstream because these sequences never occur in the channel parts of a valid SPDIF bitstream. The
sub-frame format is represented in following figure.

A sub-frame contains a single audio sample word which may be 24 bits wide, a validity bit
which indicates whether the sample is valid, a bit containing user data, a bit indicating the channel
status and a parity bit for this sub-frame. The data bits 31 to 4 in each sub-frame are encoded using
a BMC scheme. The sync preamble contains a violation of the BMC scheme and can be detected.
The following table indicates the values of the preambles.

CHANNEL CODING PRECEDING
STATE 0 1
B 11101000 00010111
M 11100010 00011101
W 11100100 00011011

q AC97:
The following figures are AC-link serial data format. Audio data is MSB adjusted, regardless
of 8, 16, 18, 20, 24 bits sample size. When a 24-bits sample is transmitted, the LSB 4-bits are
truncated. When try to record 24-bits sample, 4-bits of 0 are appended in LSB. Please reference to
$AC #97 Component Specification Revision 2.3, 2002%, provided by Intel Corporation, for details
of AC #97 architecture and AC-link specification.

AC97 audio frame format:

AC97 tag phase, slot 0 format:

AC-link data phases, slot 1 ~ slot 12 format:


13.2 General Purpose Input/Outputs (GPIO)
There are two types GPIO pins provided by SV8860. One type is normal function GPIO. The
normal function GPIO#s input or output direction can be fully controlled by application. The other
type is 9 pins enhanced function GPIO. Except for the normal function, the enhanced function
GPIO can be managed to generate interrupt with level or edge trigger. The polarity of these
interrupts can also be configured. Some of these enhanced GPIO are used to detect hot plug card
inserted or removed. More detail information for the GPIO used as special function can be found at
section 6.1 Total Pin Description.

13.3 IR Decoder
IR decoder block is used to decode the TV remoter control signal from IR detecting unit. A typical
IR detecting unit is a 3-pin device: V
cc
, Output and Ground. The Output pin will convert the IR light
into high/low pulse. Typical remote control signal is encoded by the high-low sequence. There are
several remote controller protocols exists. Each vendor can provide one by himself. This IR decoder
supports the following decoder formats:
q NEC

13.4 I
2
C Interface
The SV8860 can support 1 master I
2
C and 1 slave I
2
C serial bus. They are controlled by ARM
CPU.
Feature
q 1 set Master and 1 set Slave
q Support Master/Slave Mode Selection
q 7-bits address
q 8 bytes transmit/receive buffer
q Manual Mode Supported

13.5 JTAG
The SV8860 video subsystem includes the industry standard JTAG interface for connectivity testing
and host debugging interface to external software debuggers and in-circuit emulators. The JTAG
can be chained together with other internal components supporting JTAG to provide coordinated
multi-processor debugging. A complete debugger tool chain provides full software debugging
capability through this interface.

13.6 UART
The SV8860 contains 2 channels of UART, one is for 8051 subsystem, and the other one is
available for ARM926 console message or other serial communication.

13.7 SAR-ADC
The SV8860 has the SAR-ADC interface to connect to the touch panel for either resistive or
capacitive touch screen.

Features :

q Incorporates Successive Approximate A/D
q Maximum conversion rate: 1MS/s and 10-bit resolution
q Include 17 channel analog voltage inputs
q Include Sample and Hold functions
q Wide input range: AVDH-AVS
q Power Down mode support to eliminate current in idle mode
13.8 RTC
SV8860 has one built-in Real Time Clock with the following features

Features :
q Independent power supply for battery operation when power off
q Low current consumption
q Built-in 32.768KHz crystal oscillator circuit
q Two built-in alarm interrupters
q One periodic interrupter
q Auto calendar with an automatic leap year calculation up to year 2255
q I2C bus interface to main core logic
q Built-in power on reset and power detector circuits

14. Gigabit Ethernet MAC
SV8860 integrates a high-performance Gigabit Ethernet controller for the application of consumer
electronics and home network markets that require a higher bandwidth of network connectivity. It
supports Gigabit Ethernet MAC, which is IEEE802.3 10Base-T, IEEE802.3u 100Base-T, and
IEEE802.3ab 1000Base-T compatible. The SV8860 supports full-duplex or half-duplex operation at
10/100Mbps speed and supports full-duplex operation at 1000Mbps speed. The SV8860 also
supports IP/TCP/UDP checksum to offload processing loading from microprocessor in an
embedded system.

Features
q High-performance non-PCI local bus
n Large embedded SRAM for packet buffers
l 32K bytes for receive buffer
l 8K bytes for transmit buffer
n Support IP/TCP/UDP checksum offloads
n Support interrupt with high or low active trigge mode
q Highly-integrated Gigabit Ethernet controller
n Compatible with IEEE802.3, 802.3u, and 802.3ab standards
n Support 10/100/1000Mbps data rate
n Support full duplex operation with 1000Mbps data rate
n Support full and half duplex operations with10/100Mbps date rate
n Support 10/100/1000Mbps N-way Auto-negotiation operation
n Support IEEE 802.3x flow control for full-duplex operation
n Support 10/100/1000Mbps data rate with RGMII or MII in 10/100Mbps data rate.
n Support back-pressure flow control for half-duplex operation
n Support packet length set by software
n Support max 4K bytes JUMBO packet


GMAC Block Diagram

15. Video Output Interface
15.1 Analog Video Output
15.1.1 TV Encoder
SV8860 is with a built-in TV Encoder. This block converts video data into NTSC-M, NTSC-J,
PAL-B, D, G, H, I, M, N, and combination N systems. For the analog outputs, it provides
Composite and S-Video (Y/C) video formats.

15.1.2 YPbPr
SV8860 design in a high performance YPbPr video output format interface for DTV (Digital
Television) and generates output analog signal from 3 channels, 10-bits video DAC. It supports the
480i, 480P, 576i for SDTV (Standard Digital Television) broadcasting system. Furthermore, it also
supports 720p, 1080p output for HDTV (Hi-definition Digital Television) system.

Interface format Resolution (pixels) Frame Rate (fps)
480i 720 x 480 29.97
480P 720 x 480 60
576i 720 x 576 25
720p 1280 x 720 60
1080i 1920 x 1080 29.97
1080p 1920 x 1080 60
SV8860 YPbPr Output Format

Note: fps = Frame per second

15.2 Digital Video Output

15.2.1 CCIR-601
A 8-bit CCIR-601(ITU BT.601) master mode is designed in SV8860. It is the 8-bit 4:2:2 YCbCr
data format for data streaming. In addition to the video data, there are four control signals: HSYNC,
VSYNC, BLANK, and Data Valid.
15.2.2 CCIR-656
An 8-bits CCIR-656 (ITU BT.656) output interface is supported. The CCIR-656 transmits the
blanking intervals, special sequences are inserted into the digital video stream to indicate the start of
active video (SAV) and end of active video (EAV). The EAV and SAV sequences indicate when
horizontal and vertical blanking are present and which field is being transmitted. The EAV and
SAV sequences must have the priority over video data to ensure that correct video timing is always
maintained at the receiver. The receiver decodes the EAV and SAV sequences to recover the video
timing.
The video timing sequences of the encoder is controlled by three timing signals: H (horizontal
blanking), V (vertical blanking), and F (Field 1 or Field 2). It also included the protection bits:
P0~P3.

15.2.3 24-bit RGB with TCON
A digital 24 bits RGB output interface is supported by SV8860. It is the 24-bits parallel RGB output
interface to connect to middle or small size LCD panels. The color resolution is up to 16,777,216
colors and the pixel resolution can be up to 1920x1200 (WUXGA) pixels with OSD function
supported. Besides, a digital TCON interface and PWM are also built in SV8860 including the
display direction control (Top to Bottom/ Bottom to Top; Left to Right/ Right to Left). In addition
to RGB888 LCD support, SV8860 could also support RGB666/565 LCD panel with built-in
dithering engine to improve the display quality.

15.2.4 HDMI with HDCP
HDMI v1.3a TX controller and PHY are integrated in SV8860, it also supports CEC by the internal
8051 (with a GPIO pin).

Features :


Fig. 3 Functional Block Diagram of HDMI with HDCP


HDMI TX Block Diagram

15.3 Digital Video Input
SV8860 could support CCIR656 input directly. This digital video input interface could be used to
display the external video source on top or alpha blended with the original video layer through LCD
with TCON, HDMI, composite, Svideo or component interfaces.

16. Timing Controller
SV8860 integrates a programmable timing controller to reduce total solution cost. This timing
controller integrates pattern generator, LCD TCON, small/middle LCD interface solution, OSD,
scaling, and DPWM controller. The TCON generates timing for most used digital display panels.
The OSD engine support alpha blending and can display multiple colors at the same time
overlaying to the background. The up-scaling engine can generate independent vertical/horizontal
scaling ratio. And the gamma engine provides three 16 segment gamma corrections, one for each
channel, for panel compensation.
The timing controller also provides video enhancement features. The video enhancement engine
processes luminance and chrominance separately. In the luminance enhancement, it provides
brightness and contrast adjustment; in the chrominance component, it provides hue and saturation
change.


Some Supported Resolutions in SV8860 integrated timing controller:

Interface format Resolution (pixels) Frame Rate (fps)
480 720 x 480 60
W480 960 x 480 60
576 720 x 576 60
W576 960 x 576 60
XGA 1024 x 768 60
720p 1280 x 720 60
1080p 1920 x 1080 60
Any resolution (up to 1920x1080 60fps) for LCD display
Tab. 3 SV8860 integrated timing controller support resolution

17. Pin Information

17.1 Pin Layout

17.1.1 Left


17.1.2 Right

17.2 Pin Listing by Ball Id

Ball ID Ball Name Type Function Description Remark
A1 VDAC_R A Component Y/R output
A2 VDAC_COMPR A
VDAC_COMPR (10uF, 0.1uF,
0.01uF connect to 3v3 power)

A3 VDAC_REXT A
VDAC external resistor interface
(Connect an external 2.7k_1% to
ground)

A4 AVPP_V PWR 3v3 VDAC power
A5 VDAC_COMPB A
VDAC_COMPR (10uF, 0.1uF,

A6 LCD_B7 I/O Digital RGB output_B7
A7 LCD_G5 I/O Digital RGB output_G5
A8 LCD_R1 I/O Digital RGB output_R1
A9 LCD_R7 I/O Digital RGB output_R7
A10 LCD_CKV I/O Digital RGB_CKV
A11 LCD_STV2 I/O Digital RGB_STV2
A12 LCD_PWM1 I/O Digital RGB_PWN1
A13 AVSS_H PWR TMDS ground
A14 HDMI_EXP2 A TMDS Data2 plus
A17 HDMI_EXCP A TMDS Control plus
A18 AVSS_H PWR TMDS ground
A19 AVSS_S PWR SATA ground
A20 EAREFCLKP I SATA CLKP
A21 EARXIP A SATA differential RX_P
A22 AVSS_S PWR SATA ground
B1 VDAC_G A Component Pb/G output
B2 AVSS_V PWR SATA ground
B3 VDAC_VREF A 1v2 power input
B4 VDAC_COMPG A
VDAC_COMPG (10uF, 0.1uF,

B5 LCD_B1 I/O Digital RGB output_B1
B6 LCD_B5 I/O Digital RGB output_B5
B7 LCD_G3 I/O Digital RGB output_G3
B8 LCD_G7 I/O Digital RGB output_G7
B9 LCD_R3 I/O Digital RGB output_R3
B10 CTSEL I/O
Card table select (Hi states = 432
BGA use, Low states = 256 LQFP
use)

B11 LCD_AP I/O Digital RGB_AP
B12 LCD_DIO2 I/O Digital RGB_DIO2
B13 AVSS_H PWR TMDS ground
B14 HDMI_EXN2 A TMDS Data2 minus

B17 HDMI_EXCN A TMDS control minus
B18 AVSS_H PWR TMDS ground
B19 AVSS_S PWR SATA ground
B20 EAREFCLKN I SATA CLKN
B21 EARXIN A SATA differential RX_N
B22 AVSS_S PWR SATA ground
C1 VDAC_B A Component Pr/B output
C2 CIO11 I/O Card IO
C3 CIO3 I/O Card IO
C4 CIO1 I/O Card IO
C5 LCD_B3 I/O Digital RGB output_B3
C6 LCD_B2 I/O Digital RGB output_B2
C7 LCD_G0 I/O Digital RGB output_G0
C8 LCD_G2 I/O Digital RGB output_G2
C9 LCD_R0 I/O Digital RGB output_R0
C10 LCD_HCLK I/O Digital RGB CLK
C11 LCD_STV1 I/O Digital RGB_STV1
C12 LCD_DIO1 I/O Digital RGB_DIO1
C13 AVDD_H PWR TMDS 1.2V power
C14 AVSS_H PWR TMDS ground
C18 A3V3_S PWR SATA 3.3V power
C19 AVSS_S PWR SATA ground
C20 EXTXOP A SATA differential TX_P
C21 EXTXON A SATA differential TX_N
C22 AVSS_S PWR SATA ground
D1 CIO18 I/O Card IO
D4 CIO5 I/O Card IO
D5 CIO9 I/O Card IO
D6 LCD_B0 I/O Digital RGB output
D7 LCD_B6 I/O Digital RGB output
D8 LCD_G6 I/O Digital RGB output
D9 LCD_R4 I/O Digital RGB output
D10 LCD_LRO I/O Digital RGB_LRO
D11 LCD_LD I/O Digital RGB_LD
D12 LCD_PWM0 I/O Digital RGB_PWN0
D13 AVDD_H PWR TMDS 1.2V power
D14 SPDIFO I/O SPDIF output
D15 IIS_DATA0 I/O I2S_D

D16 DDC_SCL I/O I2C_Serial CLK for HDMI
D17 VBLOW_HDMI A VBLOW for burn in HDCP key
D18 AVDD_S PWR TMDS 1.2V power
D19 AVSS_S PWR SATA ground
D22 CLK125 I
Free running clock 125MHz from
OSC
or Giga-PHY in RGMII mode. The
pin should be pulled down in MII
mode.

E1 CIO22 I/O Card IO
E7 LCD_B4 I/O Digital RGB output_B4
E8 LCD_G4 I/O Digital RGB output_G4
E9 LCD_R2 I/O Digital RGB output_R2
E10 LCD_REV I/O Digital RGB_REV
E11 LCD_OEV I/O Digital RGB_OEV
E12 LCD_POL I/O Digital RGB_POL
E13 DDC_SDA I/O I2C serial data
E14 HTPLG_HDMI I/O HDMI HOTPLUG detection input
E15 IIS_SCLK O I2S_SCLK
E16 AVPP_A PWR SAR ADC 3.3V power
E17 AADC_CHA A SAR_ADC_Channel A
E19 TXEN O
Transmit enable:
TXEN is transition synchronously
with respect to the rising and
falling edge of TXCX. TXEN
indicates that the port is presenting
nibbles on TXD [3:0] for
transmission

E20 MDIO I/O
Station management data input /
output

E21 MDC O Station management data clock
E22 RXD0 I Receive data
F1 CIO24 I/O Card IO
F19 TXCLK I
A clock from Giga-PHY operates in
MII mode.

F20 RXD3 I Receive data

G1 CIO28 I/O Card IO
G7 CIO6 I/O Card IO
G8 CIO2 I/O Card IO
G9 LCD_G1 I/O Digital RGB output_G1
G10 LCD_R6 I/O Digital RGB output_R6
G11 AVPP_H PWR TMDS 3.3V power
G12 IIS_DAT03 I/O I2S serial data
G13 IIS_DATO1 I/O I2S serial data
G14 AADC_CHB A SAR_ADC_Channel B
G15 AADC_VR A SAR ADC_VR
G16 AVSS_A PWR SAR ADC ground
G18 TXCX O
2.5M/25M/125MHz clock output in
RGMII mode.

G19 SW_U O
Upgrade firmware for USB
[force key]

G20 TXD3 O Transmit data
H1 CIO30 I/O Card IO
H5 CIO8 I/O Card IO
H7 CIO7 I/O Card IO
H8 CIO0 I/O Card IO
H9 LCD_R5 I/O Digital RGB output_G5
H10 SPDIFI I/O SPDIF Input
H11 IIS_DATO2 I/O I2S serial data_2
H12 IIS_DATI I/O I2S_Data input
H13 IIS_LRCK I/O I2S_LRCK
H14 IIS_MCLK O I2S_MCLK
H15 VPP_G25 PWR 2v5 GMAC power
H19 RXDV I Receive data valid
H20 RXCLK I Receive clock
H21 PHYINTN I
Interrupt signal from PHY, Active
low.

H22 TXD0 O Transmit data
J1 M2_CSN I/O Chip select_M2
J2 M2_AD0 I/O DDR2 Address bus_M2
J3 M2_AD4 I/O DDR2 Address bus_M2

J4 M2_OCD I/O OCD_M2
J5 M2_CASN I/O Column address strobe_M2
J7 CIO4 I/O Card IO
J8 VPP PWR 3v3 VPP power
J9 GND PWR Digital ground
J15 VPP PWR 3v3 VPP power
J16 CRS I Carrier sense.
J18 COL I
Collision:This signal is driven by
PHY when collision is detected.

J19 AVPP_O PWR 3V3 USB OTG power
J20 AVSS_O PWR USB OTG ground
K1 M2_AD8 I/O DDR2 Address bus_M2
K4 M2_CKE I/O Clock enable_M2
K5 M2_WEN I/O Write enable_M2
K7 CIO4 I/O Card IO
K8 VPP PWR 3v3 VPP power
K9 GND PWR Digital ground
K15 VDD PWR 1v2 Core Power
K16 EGPIO I EGPIO interrupt
K18 AVDD_O 1V2 USB OTG power
K19 AVPP_O 3V3 USB OTG power
K20 AVSS_O USB OTG ground
K21 USB20O_DP A USB receive plus
K22 USB20O_DM A USB receive minus
L1 M2_AD6 I/O DDR2 Address bus_M2
L4 M2_DQ1 I/O DDR2 Data bus_M2
L5 M2_DQ0 I/O DDR2 Data bus_M2
L7 VPP PWR 3v3 VPP power
L8 VPP PWR 3v3 VPP power
L9 GND PWR Digital ground

L15 CIO37 I/O Card IO
L16 CIO36 I/O Card IO
L18 NC Not connect ball
L19 NC Not connect ball
L20 USB20O_RREF A USB voltage reference
L21 AVSS_O PWR USB OTG ground
L22 AVSS_O PWR USB OTG ground
M1 M2_RASN I/O RASN_M2
M2 M2_BA1 I/O Bank select1 of M2
M3 M2_AD1 I/O DDR2 Address bus_M2
M4 M2_DQ3 I/O DDR2 Data bus_M2
M5 M2_DQ2 I/O DDR2 Data bus_M2
M7 VDD PWR 1v2 Core Power
M8 VPP PWR 3v3 VPP power
M9 GND PWR Digital ground
M15 CIO35 I/O Card IO
M20 AVDD_U PWR 1v2 USB Host power
M21 AVSS_U PWR USB Host ground
M22 AVSS_U PWR USB Host ground
N1 M2_AD9 I/O DDR2 Address bus_M2
N2 M2_AD5 I/O DDR2 Address bus_M2
N3 M2_DQ4 I/O DDR2 Data bus_M2
N4 M2_LDQS0N O Write / Read data strobe_M2
N5 M2_LDQM0 O Data write mask_M2
N7 VDD PWR 1v2 Core Power
N8 VDD PWR 1v2 Core Power
N9 GND PWR Digital ground

N15 URX0 I/O UART_RX0
N16 JT_TCK I/O CPUs debug and TAP clock
N18 JT_TDO I/O CPUs debug and TAP data output
N19 UTX0 I/O UART_TX0
N20 USB20H1_EXT12K A USB voltage reference
N21 USB20H1_DPPAD A USB receive plus
N22 USB20H1_DMPAD A USB receive minus
P1 M2_AD12 I/O DDR2 Address bus_M2
P2 M2_AD7 I/O DDR2 Address bus_M2
P3 M2_DQ5 I/O DDR2 Data bus_M2
P7 VDD PWR 1v2 Core Power
P8 VDD PWR 1v2 Core Power
P9 GND PWR Digital ground
P15 JT_TMS I/O CPUs debug and TAP mode select
P16 JT_TDI I/O CPUs debug and TAP data input
P18 I2C_SCL I/O I2C serial clock
P19 AVPP_U PWR 3v3 USB Host power
P20 AVDD_U PWR 1v2 USB Host power
P21 USB20H0_DPPAD A USB receive plus
P22 USB20H0_DMPAD A USB receive minus
R1 M2_AD3 I/O DDR2 Address bus_M2
R2 M2_AD10 I/O DDR2 Address bus_M2
R3 M2_DQ8 I/O DDR2 Data bus_M2
R4 M2_UDQM0 O Data write mask_M2
R5 M2_DQ11 I/O DDR2 Data bus_M2
R7 VPP_D18 PWR DDR2 1.8V power
R8 VPP_D18 PWR DDR2 1.8V power
R9 VPPD18 PWR DDR2 1.8V power
R10 VDD PWR 1v2 Core Power
R15 I2C_SDA I/O I2C serial data
R16 VPP PWR 3v3 VPP power
R18 VPP PWR 3v3 VPP power
R19 AVPP_U PWR 3v3 USB power_Host
R20 USB20H0_EXT12K A USB voltage reference

R21 AVSS_U PWR USB Host ground
R22 AVSS_U PWR USB Host ground
T1 M2_BA0 I/O Bank select0 of M2
T2 M2_BA2 I/O Bank select2 of M2
T3 M2_DQ12 I/O DDR2 Data bus_M2
T7 VPP_D18 PWR DDR2 1.8V power
T10 VDD PWR 1v2 Core Power
T18 VPP PWR 3v3 VPP power
T19 VPP PWR 3v3 VPP power
T20 TS_VALID I/O TSIN control signals
T21 TS_FAIL I/O TSIN control signals
T22 TS_D7 I/O TSIN parallel data
U1 M2_ODT O Memory on-die termination_M2
U2 M2_VREF A SSTL reference voltage_M2
U3 M2_CK I/O Clock to DDR_M2
U4 SC_IO I/O Smart card I/O
U19 VDD PWR 1v2 Core Power
U20 TS_SOP I/O TSIN control signals
U21 TS_D5 I/O TSIN parallel data
U22 TS_D6 I/O TSIN parallel data
V1 M2_LDQS0 O Write / Read data strobe_M2
V2 M2_DQ9 I/O DDR2 Data bus_M2
V3 M2_DQ10 I/O DDR2 Data bus_M2
V4 URX1 I/O UART_RX1
V6 AVDD_P PWR 1v2 PLL Power
V9 VPP_D18 PWR DDR2 1.8V power

V19 VDD PWR 1v2 Core Power
V20 VDD PWR 1v2 Core Power
V21 TS_D3 I/O TSIN parallel data
V22 TS_D4 I/O TSIN parallel data
W1 M2_UDQS0 ? Write / Read data strobe_M2
W2 M2_UDQS0N ? Write / Read data strobe_M2
W3 M2_DQ15 I/O DDR2 Data bus_M2
W4 VPP PWR 3v3 VPP power
W5 VPP_D18 PWR DDR2 1.8V power
W6 AVSS_P PWR PLL ground
W7 AVSS_P PWR PLL ground
W8 M1_CSN I/O Chip select_M1
W9 M1_AD13 I/O DDR2 Address bus_M1
W11 M1_BA1 I/O Bank select1 of M1
W18 VDD PWR 1v2 Core Power
W21 TS_D1 I/O TSIN parallel data
W22 TS_D2 I/O TSIN parallel data
Y1 M2_CKN I/O Inverted clock to DDR
Y2 VDD_8051 --- Up8051 D1.2V power
Y3 VPP_8051 --- Up8051 D3.3V power
Y4 UTX1 I/O UART_TX1
Y5 MGPIO0 I/O Up8051 MGPIO0
Y6 RTC_XO O RTC_32.768Hz output
Y7 AVSS_P PWR PLL ground
Y8 M1_OCD I/O OCD_M1
Y9 M1_AD8 I/O DDR2 Address bus_M1
Y11 M1_WEN I/O Write enable_M1
Y13 M1_BA0 I/O Bank select0 of M1
Y14 M1_CKE I/O Clock enable_M1
Y15 M1_DQ3 I/O DDR2 Data bus
Y16 M1_LDQS0N ? Write / Read data strobe
Y17 M1_AD12 I/O DDR2 Address bus

Y19 M1_VREF A SSTL reference voltage
Y21 TS_D0 I/O TSIN parallel data
Y22 TS_CLK I/O TSIN control signals
AA1 TESTMD I Test mode
AA2 SC_nRST O nRESET of smart card
AA3 SC_CLK O Clock for smart card
AA4 XI27 I System CLK (27Mhz)
AA5 MGPIO2 I/O Up8051 MGPIO2
AA6 RTC_XI I RTC_32.768Hz input
AA7 IR I IR data input
AA8 M1_CKN I/O Clock_N to DDR_M1
AA9 M1_AD4 I/O DDR2 Address bus_M1
AA11 M1_RASN I/O RASN_M1
AA12 M1_DQ11 I/O DDR2 Data bus_M1
AA14 M1_ODT O Memory on-die termination_M1
AA16 M1_LDQS0 ? Write / Read data strobe_M1
AA20 M1_UDQS0 ? Write / Read data strobe_M1
AB1 RESETB System reset
AB2 SC_NCD_PRES Smart card Detection flag
AB3 CEC HDMI CEC line
AB4 XO27 O System CLK (27Mhz)
AB5 MGPIO1 I/O Up8051 MGPIO1
AB6 RTC_VPP PWR RTC 3.3V power
AB7 PWR_ON O PWR_ON - Standby mode
AB8 M1_CK Clock_P to DDR_M1
AB9 M1_AD0 I/O DDR2 Address bus_M1
AB11 M1_CASN Column address strobe_M1
AB12 M1_DQ10 I/O DDR2 Data bus_M1
AB14 M1_BA2 Bank select2 of M1
AB16 M1_LDQM0 Data write mask_M1

AB20 M1_UDQM0 Data write mask_M1
AB21 M1_UDQS0N ? Write / Read data strobe_M1
Tab. 4 SV8860 Pin Assignment list

17.3 Shared Pin for Card Readers
Ball
Name
Type Schmitt
Driving
Current
(mA)
Pull
Up/Dn
NOR
FLASH
NAND
FLASH
SD/MMC
#0
SD/MMC
#1
MS
MSPRO
CIO0 I/O v 6 d NF_D[8]
CIO8 I/O v 6 u NF_D[0]
CIO16 I/O v 6 u NF_ALE
CIO17 I/O v 6 d SD_CLK0 MS_CLK
CIO18 I/O v 6 d SD_CLK1
CIO19 I/O v 6 u NOR_nWP NF_nWP
CIO20 I/O v 6 u NOR_DI NF_RDY
CIO21 I/O v 6 d NOR_CLK NF_CLE
CIO22 I/O v 6 u NOR_nCS0 NF_nCE0
CIO23 I/O v 6 u NOR_DO NF_nOE
CIO24 I/O v 6 u NF_nWEL
CIO25 I/O v 6 u NF_nWEH
CIO26 I/O v 6 u NF_nCE1
CIO27 I/O v 6 u SD_DO0 SD_DO10 MS_D[0]
CIO35 I/O v 6 u SD_CMD0 SD_CMD1 MS_BS
CIO36 I/O v 6 u SD_CD0 MS_INS
CIO37 I/O v 6 u SD_WP0
Tab. 5 SV8860 Shared Pin for Card Readers

17.4 LCD/Digital RGB/CCIR656 Input Mux Pins
LCD+TCON
LCD
(parallel RGB888)
CCIR 656 Input
form LCD
CCIR656 Input
from TS
Ball
id
Pin name
Ball
id
Pin name
Ball
id
Pin name
Ball
id
Pin name
C10 LCD_HCLK C10 LCD_HCLK C10 LCD_HCLK Y22 TS_HCLK
A9 LCD_R7 A9 LCD_R7 A9 LCD_R7 T22 TS _R7
G10 LCD_R6 G10 LCD_R6 G10 LCD_R6 U22 TS _R6
H9 LCD_R5 H9 LCD_R5 H9 LCD_R5 U21 TS _R5
D9 LCD_R4 D9 LCD_R4 D9 LCD_R4 V22 TS _R4
B9 LCD_R3 B9 LCD_R3 B9 LCD_R3 V21 TS _R3
E9 LCD_R2 E9 LCD_R2 E9 LCD_R2 W22 TS _R2
A8 LCD_R1 A8 LCD_R1 A8 LCD_R1 W21 TS _R1
C9 LCD_R0 C9 LCD_R0 C9 LCD_R0 Y21 TS _R0
B8 LCD_G7 B8 LCD_G7
D8 LCD_G6 D8 LCD_G6
A7 LCD_G5 A7 LCD_G5
E8 LCD_G4 E8 LCD_G4
B7 LCD_G3 B7 LCD_G3
C8 LCD_G2 C8 LCD_G2
G9 LCD_G1 G9 LCD_G1
C7 LCD_G0 C7 LCD_G0
A6 LCD_B7 A6 LCD_B7
D7 LCD_B6 D7 LCD_B6
B6 LCD_B5 B6 LCD_B5
E7 LCD_B4 E7 LCD_B4
C5 LCD_B3 C5 LCD_B3
C6 LCD_B2 C6 LCD_B2
B5 LCD_B1 B5 LCD_B1
D6 LCD_B0 D6 LCD_B0
C12 LCD_DIO1[vs] C12 LCD_DIO1[vs]
B12 LCD_DIO2[hs] B12 LCD_DIO2[hs]
C11 LCD_STV1 C11 LCD_STV1[de]
A11 LCD_STV2
E12 LCD_POL
E11 LCD_OEV
D11 LCD_LD
A10 LCD_CKV
D10 LCD_LRO
E10 LCD_REV
B11 LCD_AP
D12 LCD_PWM0
A12 LCD_PWM1

Tab. 6 SV8860 LCD/Digital RGB/CCIR656 Input Mux Pins


17.5 GPIO Pin List and Address Define
17.5.1 GPIO Pin Group List
Single
Name
Ball
Name
Shared as
Driving
Current
(mA)
Schmitt
Trigger
Pull
Up/Down
Default
Input/Output
Default
Value
GPIO[0] H14 IIS_MCLK 6 Input x
GPIO[1] E15 IIS_SCLK 4 Input x
GPIO[2] H13 IIS_LRCK 4 Input x
GPIO[3] H12 IIS_DATI 4 Input x
GPIO[4] D15 IIS_DATO0 4 Output 0
GPIO[5] G13 IIS_DATO1 4 Output 0
GPIO[6] H11 IIS_DATO2 4 Output 0
GPIO[7] G12 IIS_DATO3 4 Output 0
GPIO[8] D14 SPDIFO 4 Output 0
GPIO[9] H10 SPDIFI 4 v Input x
GPIO[10] P16 JT_TDI 4 Input x
GPIO[11] N16 JT_TCK 4 u Input x
GPIO[12] N18 JT_TDO 4 u Output 0
GPIO[13] N15 URX0 4 u Input x
GPIO[15] N19 UTX0 4 Output 0
GPIO[17] H8 CIO0 6 v d Input x
GPIO[18] C4 CIO1 6 v d Input x
GPIO[19] G8 CIO2 6 v d Input x
GPIO[20] C3 CIO3 6 v d Input x
GPIO[21] J7 CIO4 6 v d Input x
GPIO[22] D4 CIO5 6 v d Input x
GPIO[23] G7 CIO6 6 v d Input x
GPIO[24] H7 CIO7 6 v d Input x
GPIO[25] H5 CIO8 6 v u Input x
GPIO[26] D5 CIO9 6 v u Input x
GPIO[27] H4 CIO10 6 v u Input x
GPIO[28] C2 CIO11 6 v u Input x
GPIO[29] G5 CIO12 6 v u Input x
GPIO[30] D3 CIO13 6 v u Input x
GPIO[31] G4 CIO14 6 v u Input x

17.5.2 GPIO Pin Group Address Define
Single
Name
GPIO MODE
Enable
Address
GPIO
Directions
Address
GPIO
Write Enable
Address
GPIO
Data
Address
GPIO[0] 0xC1FC0044[0] 0xC1FC0000[0] 0xC1FC0018[0] 0xC1FC0004[0]

17.5.3 GPIOH Pin Group Pin List
Single
Name
Ball
Name
Shared as
Driving
Current
(mA)
Schmitt
Trigger
Pull
Up/Down
Default
Input/Output
Default
Value
GPIOH[0] E4 CIO15 6 v u Input x
GPIOH[2] F4 CIO17 6 v d Input x
GPIOH[3] D1 CIO18 6 v d Input x
GPIOH[4] D2 CIO19 6 v u Input x
GPIOH[6] E2 CIO21 6 v d Input x
GPIOH[8] F3 CIO23 6 v u Input x
GPIOH[10] G3 CIO25 6 v u Input x
GPIOH[14] H2 CIO29 6 v u Input x
GPIOH[17] M19 CIO32 6 v u Input x
GPIOH[21] L16 CIO36 6 v u Input x
GPIOH[22] L15 CIO37 6 v u Input x
GPIOH[23] D12 LCD_PWM0 8 Output 0
GPIOH[24] A12 LCD_PWM1 8 Output 0
GPIOH[25] C12 LCD_DIO1 8 Input x
GPIOH[26] B12 LCD_DIO2 8 Input x
GPIOH[27] C11 LCD_STV1 8 Output 0
GPIOH[28] A11 LCD_STV2 8 Output 0
GPIOH[29] E12 LCD_POL 8 Output 0
GPIOH[30] E10 LCD_REV 8 Output 0
GPIOH[31] E11 LCD_OEV 8 Output 0

17.5.4 GPIOH Pin Group Address Define
Single
Name
GPIOH MODE
Enable
Address
GPIOH
Directions
Address
GPIOH
Write Enable
Address
GPIOH
Data
Address
GPIOH[0] 0xC1FC0048[0] 0xC1FC0020[0] 0xC1FC0028[0] 0xC1FC0024[0]

17.5.5 GPIO2 Pin Group List
Single
Name
Ball
Name
Shared as
Driving
Current
(mA)
Schmitt
Trigger
Pull
Up/Down
Default
Input/Output
Default
Value
GPIO2[0] D11 LCD_LD 8 Output 0
GPIO2[1] C10 LCD_HCLK 8 Input x
GPIO2[2] A10 LCD_CKV 8 Output 0
GPIO2[3] A9 LCD_R7 8 Input x
GPIO2[4] G10 LCD_R6 8 Input x
GPIO2[5] H9 LCD_R5 8 Input x
GPIO2[6] D9 LCD_R4 8 Input x
GPIO2[7] B9 LCD_R3 8 Input x
GPIO2[8] E9 LCD_R2 8 Input x
GPIO2[9] A8 LCD_R1 8 Input x
GPIO2[10] C9 LCD_R0 8 Input x
GPIO2[11] B8 LCD_G7 8 Output 0
GPIO2[12] D8 LCD_G6 8 Output 0
GPIO2[13] A7 LCD_G5 8 Output 0
GPIO2[14] E8 LCD_G4 8 Output 0
GPIO2[15] B7 LCD_G3 8 Output 0
GPIO2[16] C8 LCD_G2 8 Output 0
GPIO2[17] G9 LCD_G1 8 Output 0
GPIO2[18] C7 LCD_G0 8 Output 0
GPIO2[19] A6 LCD_B7 8 Output 0
GPIO2[20] D7 LCD_B6 8 Output 0
GPIO2[21] B6 LCD_B5 8 Output 0
GPIO2[22] E7 LCD_B4 8 Output 0
GPIO2[23] C5 LCD_B3 8 Output 0
GPIO2[24] C6 LCD_B2 8 Output 0
GPIO2[25] B5 LCD_B1 8 Output 0
GPIO2[26] D6 LCD_B0 8 Output 0
GPIO2[27] Y22 TS_CLK 8 Input x
GPIO2[28] T21 TS_FAIL 8 Input x
GPIO2[29] T20 TS_VALID 8 Input x
GPIO2[30] U20 TS_SOP 8 Input x
GPIO2[31] Y21 TS_D0 8 Input x

17.5.6 GPIO2 Pin Group Address Define
Single
Name
GPIO2 MODE
Enable
Address
GPIO2
Directions
Address
GPIO2
Write Enable
Address
GPIO2
Data
Address
GPIO2[0] 0xC1FC004C[0] 0xC1FC002C[0] 0xC1FC0034[0] 0xC1FC0030[0]

17.5.7 GPIO3 Pin Group List
Single
Name
Ball
Name
Shared as
Driving
Current
(mA)
Schmitt
Trigger
Pull
Up/Down
Default
Input/Output
Default
Value
GPIO3[0] W21 TS_D1 8 Input x
GPIO3[1] W22 TS_D2 8 Input x
GPIO3[2] V21 TS_D3 8 Input x
GPIO3[3] V22 TS_D4 8 Input x
GPIO3[4] U21 TS_D5 8 Input x
GPIO3[5] U22 TS_D6 8 Input x
GPIO3[6] T22 TS_D7 8 Input x
GPIO3[7] B11 LCD_AP 8 Output 0
GPIO3[8] * B10 CTSEL 8 Input x
GPIO3[9] D10 LCD_LRO 8 Output 0
GPIO3[10] D22 CLK125 4 v Input x
GPIO3[11] H20 RXCLK 4 v Input x
GPIO3[12] F20 RXD3 4 Input x
GPIO3[15] E22 RXD0 4 Input x
GPIO3[16] H19 RXDV 4 Input x
GPIO3[17] J18 COL 4 Input x
GPIO3[18] J16 CRS 4 Input x
GPIO3[19] E20 MDIO 8 u Input x
GPIO3[20] H21 PHYINTN 4 Input x
GPIO3[21] F19 TXCLK 4 v Input x
GPIO3[22] E19 TXEN 8 Output 0
GPIO3[23] G20 TXD3 8 Output 0
GPIO3[26] H22 TXD0 8 Output 0
GPIO3[27] G18 TXCX 8 Output 0
GPIO3[28] G19 SW_U 8 Output 0
GPIO3[29] E21 MDC 8 Output 0
* GPIO3[8] (CTSEL) is dedicated for card table selection. Please don#t use.

17.5.8 GPIO3 Pin Group Address Define
Single
Name
GPIO3 MODE
Enable
Address
GPIO3
Directions
Address
GPIO3
Write Enable
Address
GPIO3
Data
Address
GPIO3[0] 0xC1FC0050[0] 0xC1FC0038[0] 0xC1FC0040[0] 0xC1FC003C[0]
GPIO3[8] * 0xC1FC0050[8] 0xC1FC0038[8] 0xC1FC0040[8] 0xC1FC003C[8]
* GPIO3[8] (CTSEL) is dedicated for card table selection. Please don#t use.

17.5.9 EGPIO Pin Group List
Single
Name
Ball
Name
Shared as
Driving
Current
(mA)
Schmitt
Trigger
Pull
Up/Down
Default
Input/Output
Default
Value
EGPIO[0] E14 HTPLG_HDMI Input x
EGPIO[1] M19 CIO32 6 v u Only Input x
EGPIO[2] M16 CIO33 6 v u Only Input x
EGPIO[3] L16 CIO36 6 v u Only Input x
EGPIO[4] K16 EGPIO 4 u Only Input x

17.5.10 EGPIO Pin Group Address Define
Single
Name
EGPIO
Interrupt
Enable
Address
EGPIO
Interrupt
Type
Address
EGPIO
Interrupt
Status
Address
EGPIO
Directions
Address
EGPIO
Write Enable
Address
EGPIO
Data
Address
EGPIO[0]
0xC1FC001C
[0]
0xC1FC0010[
0]
0xC1FC0014[
0]
0xC1FC0008[
0]
0xC1FC001C[
16]
0xC1FC000C
[0]
EGPIO[1]
0xC1FC001C
[1]
0xC1FC0010[
1]
0xC1FC0014[
1]
0xC1FC0008[
1]
0xC1FC001C[
17]
0xC1FC000C
[1]
EGPIO[2]
0xC1FC001C
[2]
0xC1FC0010[
2]
0xC1FC0014[
2]
0xC1FC0008[
2]
0xC1FC001C[
18]
0xC1FC000C
[2]
EGPIO[3]
0xC1FC001C
[3]
0xC1FC0010[
3]
0xC1FC0014[
3]
0xC1FC0008[
3]
0xC1FC001C[
19]
0xC1FC000C
[3]
EGPIO[4]
0xC1FC001C
[4]
0xC1FC0010[
4]
0xC1FC0014[
4]
0xC1FC0008[
4]
0xC1FC001C[
20]
0xC1FC000C
[4]

17.5.11 MGPIO Pin Group List
Single
Name
Ball
Name
Shared as
Driving
Current
(mA)
Schmitt
Trigger
Pull
Up/Down
Default
Input/Output
Default
Value
MGPIO[0] Y5 MGPIO0 8 Input x
MGPIO[1] AB5 MGPIO1 8 Input x
MGPIO[2] AA5 MGPIO2 8 Input x

17.5.12 MGPIO Pin Group Address Define
Single
Name
MGPIO
Output Enable
Address
MGPIO
Write Mask
Address
MGPIO
Data
Address
MGPIO[0]
CPU:0xC2400038[0]
DP8051:0x10000E[0]
CPU:0xC240003C[0]
DP8051:0x10000F[0]
CPU:0xC2400034[0]
DP8051:0x10000D[0]
MGPIO[1]
CPU:0xC2400038[1]
DP8051:0x10000E[1]
CPU:0xC240003C[1]
DP8051:0x10000F[1]
CPU:0xC2400034[1]
DP8051:0x10000D[1]
MGPIO[2]
CPU:0xC2400038[2]
DP8051:0x10000E[2]
CPU:0xC240003C[2]
DP8051:0x10000F[2]
CPU:0xC2400034[2]
DP8051:0x10000D[2]


18. System Specifications
18.1 DC Characteristics
18.1.1 Power Supply

Symbol Parameter Min. Typ. Max. Unit
VPP Power Supply of I/O Pad 3.0 3.3 3.6 Volt
VDD Power Supply of Core Power 1.1 1.2 1.3 Volt
VPP_8051 Power Supply of dp8051 I/O Pad 3.0 3.3 3.6 Volt
VDD_8051 Power Supply of sp8051 Core Power 1.1 1.2 1.3 Volt
RTC_VPP Power Supply of RTC 3.3V 3.0 3.3 3.6 Volt
AVDD_P Power Supply of PLL 1.2V 1.1 1.2 1.3 Volt
AVPP_H Power Supply of HDMI I/O Pad 3.0 3.3 3.6 Volt
AVDD_H Power Supply of HDMI 1.2V 1.1 1.2 1.3 Volt
AVPP_O Power Supply of USBO I/O Pad 3.0 3.3 3.6 Volt
AVDD_O Power Supply of USBO 1.2V 1.1 1.2 1.3 Volt
AVPP_U Power Supply of USB Host I/O Pad 3.0 3.3 3.6 Volt
AVDD_U Power Supply of USB Host 1.2V 1.1 1.2 1.3 Volt
VPP_D18 Power Supply of DDR 1.8V - 1.8 - Volt
VPP_G25 Power Supply of GMAC 2.5V - 2.5 - Volt
AVPP_V Power Supply of DAC 3.3V 3.0 3.3 3.6 Volt
AVPP_A Power Supply of ADC 3.3V 3.0 3.3 3.6 Volt
A3V3_S Power Supply of SATA I/O Pad 3.0 3.3 3.6 Volt
AVDD_S Power Supply of SATA 1.2V 1.1 1.2 1.3 Volt
18.1.2 Recommended I/O Pad Operating Conditions
Power Supply (VPP = 3.3V ( 0.3V / VDD = 1.2V ( 0.1V, VSS = 0V)
Ratings
Parameter Symbol
Min. Typ. Max.
Unit
VPP 3.0 3.3 3.6 Volt
Power Supply Voltage
VDD 1.1 1.2 1.3 Volt
1.2V CMOS VDDx0.7 - VDD+0.3 Volt
H-level Input Voltage
3.3V CMOS
V
IH

2.0 - VPP+0.3 Volt
1.2V CMOS -0.3 - VDD+0.3 Volt
L-level Input Voltage
3.3V CMOS
V
IL

-0.3 - VPPx0.3 Volt
Junction Temperature T
j
-40 - 125 Volt

18.1.3 I/O Pad Capacitance
Symbol Parameter Min. Typ. Max. Units
C
OUT
Output pin capacitance - - 16 pF
C
IN
Input pin capacitance - - 16 pF
C
IN/OUT
Input/Output pin capacitance - - 16 pF

18.2 AC Characteristics
18.2.1 Power On Sequence
Power Supply (VPP = 3.3V ( 0.3V / VDD = 1.2V ( 0.1V, VSS = 0V)

At Power On: VDD VPP Signals

At Power Off: Signals VPP VDD

18.2.2 Reset and System Clock Timing

Fig. 4 Reset and System Timing Diagram

Symbol Parameter Min. Typ. Max. Unit Note
TRST Reset Pulse Width 3 ms
TP_XI27 27MHz Clock Input Frequency 27 MHz 20pp
m
DT_XI27 27MHz Clock Input Duty Cycle 45 50 55 %

RESETB
XI2
7
Tp_XI2
7
1,2V
3.3V
System
clock
T
RST
> 3ms

18.3 Power consumption
18.3.1 Standby mode
Parameter Min. Typ. Max. Unit Notes
3.3V current - 4.8 - mA
1.8V current - 20 - mA For DDR2 SDRAM
1.2V current - 78 - mA Core power

18.3.2 Normal mode
Parameter Min. Typ. Max. Unit Notes
3.3V current - 20 - mA
1.8V current - 180 - mA For DDR2 SDRAM
1.2V current - 800 - mA Core power


19. Package Information

Fig. 5 432-pin TFBGA (19m x 19mm x 1.6mm) Package Outline Diagram


Fig. 6 432-pin TFBGA (19mm x 19mm x 1.6mm) Package Mechanical Information


Fig. 7 432-pin TFBGA (19mm x 19mm x 1.6mm) Ball Map

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