CMOS FABRICATION

Ashutosh Srivastava
Lecture No.6
EEE C443
ANALOG AND DIGITAL VLSI DESIGN
BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE,
PILANI
OUTLINE
1.
1.
Why CMOS preferred over NMOS or PMOS
Why CMOS preferred over NMOS or PMOS
2. CMOS Fabrication Sequence
2. CMOS Fabrication Sequence
3.
3.
N
N
-
-
Well CMOS
Well CMOS
Invertor
Invertor
4. Design Rules
4. Design Rules
5. Moore
5. Moore

s Law &
s Law &
Nano
Nano
-
-
electronics
electronics
Why CMOS Transistor
Why CMOS Transistor
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
0.
0.
Start:
Start:
For an n For an n- -well process the starting point is a p well process the starting point is a p- -type silicon wafer: type silicon wafer:
wafer: typically 200 to 300mm in diameter and less than 1mm thic wafer: typically 200 to 300mm in diameter and less than 1mm thick k
1.
1.
Epitaxial
Epitaxial
growth:
growth:
A p A p- -type single crystal film is grown on the surface of the wafer by type single crystal film is grown on the surface of the wafer by: :
subjecting the wafer to high temperature and a source of subjecting the wafer to high temperature and a source of dopant dopant material material
The The epi epi layer is used as the base layer to build the devices layer is used as the base layer to build the devices
P+ -type wafer
p-epitaxial layer
Diameter = 200 to 300mm
< 1mm
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
2. N 2. N- -well Formation: well Formation:
PMOS transistors are fabricated in n PMOS transistors are fabricated in n- -well regions well regions
The first mask defines the n The first mask defines the n- -well regions well regions
N N- -well well s are formed by ion implantation or deposition and diffusion s are formed by ion implantation or deposition and diffusion
Lateral diffusion limits the proximity between structures Lateral diffusion limits the proximity between structures
Ion implantation results in shallower wells compatible with toda Ion implantation results in shallower wells compatible with today y s fine s fine- -
line processes line processes
p-type epitaxial layer
n-well
Lateral
diffusion
Physical structure cross section Mask (top view)
n-well mask
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
3. Active area definition:
3. Active area definition:
Active area: Active area:
planar section of the surface where transistors are build planar section of the surface where transistors are build
defines the gate region (thin oxide) defines the gate region (thin oxide)
defines the n+ or p+ regions defines the n+ or p+ regions
A thin layer of SiO A thin layer of SiO
2 2
is grown over the active region and is grown over the active region and
covered with silicon nitride covered with silicon nitride
n-well
Silicon Nitride
Stress-relief oxide
p-type
Active mask
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
4. 4. Isolation: Isolation:
Parasitic (unwanted) Parasitic (unwanted) FET FET s s exist between unrelated transistors exist between unrelated transistors
(Field Oxide (Field Oxide FET FET s s) )
Source and drains are existing source and drains of wanted devic Source and drains are existing source and drains of wanted devices es
Gates are metal and Gates are metal and polysilicon polysilicon interconnects interconnects
The threshold voltage of FOX The threshold voltage of FOX FET FET s s are higher than for normal are higher than for normal
FET FET s s
p-substrate (bulk)
n+ n+
Parasitic FOX device
n+ n+
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
FOX
FOX
FET
FET

s
s
threshold is made high by:
threshold is made high by:
introducing a channel introducing a channel- -stop diffusion that raises the impurity stop diffusion that raises the impurity
concentration in the substrate in areas where transistors are no concentration in the substrate in areas where transistors are not t
required required
making the FOX thick making the FOX thick
4.1 Channel
4.1 Channel
-
-
stop implant
stop implant
The silicon nitride (over n The silicon nitride (over n- -active) and the active) and the photoresist photoresist (over n (over n- -well) act well) act
as masks for the channel as masks for the channel- -stop implant stop implant
n-well
p-type
channel stop mask = ~(n-well mask)
resit
Implant (Boron)
p+ channel-stop implant
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
4.2
4.2
Local oxidation of silicon (LOCOS)
Local oxidation of silicon (LOCOS)
The The photoresist photoresist mask is removed mask is removed
The SiO The SiO
2 2
/SiN layers will now act as a masks /SiN layers will now act as a masks
The thick field oxide is then grown by: The thick field oxide is then grown by:
exposing the surface of the wafer to a flow of oxygen exposing the surface of the wafer to a flow of oxygen- -rich gas rich gas
The oxide grows in both the vertical and lateral directions The oxide grows in both the vertical and lateral directions
This results in a active area smaller than patterned This results in a active area smaller than patterned
n - w e l l
p - t y p e
F i e l d o x i d e ( F O X )
p a t t e r n e d a c t i v e a r e a
a c t i v e a r e a a f t e r L O C O S
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
Silicon oxidation is obtained by: Silicon oxidation is obtained by:
Heating the wafer in a oxidizing atmosphere: Heating the wafer in a oxidizing atmosphere:
Wet oxidation: water vapor, T = 900 to 1000 Wet oxidation: water vapor, T = 900 to 1000 C (rapid C (rapid
process) process)
Dry oxidation: Pure oxygen, T = 1200 Dry oxidation: Pure oxygen, T = 1200 C (high temperature C (high temperature
required to achieve an acceptable growth rate) required to achieve an acceptable growth rate)
Oxidation consumes silicon Oxidation consumes silicon
SiO SiO
2 2
has approximately twice the volume of silicon has approximately twice the volume of silicon
The FOX is recedes below the silicon surface by 0.46X The FOX is recedes below the silicon surface by 0.46X
FOX FOX
X
FOX
0.54 X
FOX
0.46 X
FOX
Silicon wafer
Silicon surface
Field oxide
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
5. 5. Gate oxide growth Gate oxide growth
The nitride and stress The nitride and stress- -relief oxide are removed relief oxide are removed
The devices threshold voltage is adjusted by: The devices threshold voltage is adjusted by:
adding charge at the silicon/oxide interface adding charge at the silicon/oxide interface
The well controlled gate oxide is grown with thickness The well controlled gate oxide is grown with thickness t t
ox ox
n - w e l l
p - t y p e
n - w e l l
p - t y p e
t
o x
t
o x
G a t e o x i d e
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
6.
6. Poly Poly- -silicon deposition and patterning silicon deposition and patterning
A layer of poly A layer of poly- -silicon is deposited over the entire wafer surface silicon is deposited over the entire wafer surface
The poly The poly- -silicon is then patterned by a lithography sequence silicon is then patterned by a lithography sequence
All the MOSFET gates are defined in a single step All the MOSFET gates are defined in a single step
The poly The poly- -silicon gate can be doped (n+) while is being deposited to silicon gate can be doped (n+) while is being deposited to
lower its parasitic resistance (important in high speed fine lin lower its parasitic resistance (important in high speed fine line e
processes) processes)
n-well
p-type
Polysilicon gate
Polysilicon mask
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
7. 7. PMOS formation PMOS formation
Photoresist Photoresist is patterned to cover all but the p+ regions is patterned to cover all but the p+ regions
A boron ion beam creates the p+ source and drain regions A boron ion beam creates the p+ source and drain regions
The The polysilicon polysilicon serves as a mask to the underlying channel serves as a mask to the underlying channel
This is called a self This is called a self- -aligned process aligned process
It allows precise placement of the source and drain regions It allows precise placement of the source and drain regions
During this process the gate gets doped with p During this process the gate gets doped with p- -type impurities type impurities
Since the gate had been doped n Since the gate had been doped n- -type during deposition, the final type during deposition, the final
type (n or p) will depend on which type (n or p) will depend on which dopant dopant is dominant is dominant
n-well
p-type
p+ implant (boron)
p+ mask
Photoresist
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
8 8. NMOS formation . NMOS formation
Photoresist Photoresist is patterned to is patterned to define define the n+ regions the n+ regions
Donors (arsenic or phosphorous) are ion Donors (arsenic or phosphorous) are ion- -implanted to dope the n+ implanted to dope the n+
source and drain regions source and drain regions
The process is self The process is self- -aligned aligned
The gate is n The gate is n- -type doped type doped
n-well
p-type
n+ implant (arsenic or phosphorous)
n+ mask
Photoresist
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
9.
9. Annealing Annealing
After the implants are completed a thermal annealing cycle is ex After the implants are completed a thermal annealing cycle is executed ecuted
This allows the impurities to This allows the impurities to diffuse diffuse further into the bulk further into the bulk
After thermal annealing, it is important to keep the remaining p After thermal annealing, it is important to keep the remaining process steps at as rocess steps at as
low temperature as possible low temperature as possible
n-well
p-type
n+
p+
10.
10.
Contact cuts
Contact cuts
The surface of the IC is covered by a layer of CVD The surface of the IC is covered by a layer of CVD
oxide oxide
The oxide is deposited at low temperature (LTO) to avoid that The oxide is deposited at low temperature (LTO) to avoid that
underlying doped regions will undergo diffusive spreading underlying doped regions will undergo diffusive spreading
Contact cuts are defined by etching SiO Contact cuts are defined by etching SiO
2 2
down to the down to the
surface to be contacted surface to be contacted
These allow metal to contact diffusion and/or These allow metal to contact diffusion and/or
polysilicon polysilicon regions regions
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
n-well
p-type
n+
p+
Contact mask
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
11.
11. Metal 1 Metal 1
A first level of metallization is applied to the wafer surface a A first level of metallization is applied to the wafer surface and nd
selectively etched to produce the interconnects selectively etched to produce the interconnects
n-well
p-type
n+
p+
metal 1 mask
metal 1
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
12. Metal 2
Another layer of LTO CVD oxide is added
Via openings are created
Metal 2 is deposited and patterned
n - w e l l
p - t y p e
n +
p +
V i a
m e t a l 1
m e t a l 2
CMOS FABRICATION SEQUENCE
CMOS FABRICATION SEQUENCE
13. Over glass and pad openings
13. Over glass and pad openings
A protective layer is added over the surface A protective layer is added over the surface
The protective layer consists of The protective layer consists of
A layer of SiO A layer of SiO
2 2
Followed by a layer of Followed by a layer of silicon nitride silicon nitride
The The SiN SiN layer acts as a diffusion barrier against layer acts as a diffusion barrier against
contaminants ( contaminants (passivation passivation) )
Finally, contact cuts are etched, over metal 2, on the Finally, contact cuts are etched, over metal 2, on the
passivation passivation to allow for wire bonding. to allow for wire bonding.
N
N
-
-
WELL CMOS INVERTOR
WELL CMOS INVERTOR
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+ p+
SiO
2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
Design Rules
Design Rules
Layout (design) rules: prescription for preparing Layout (design) rules: prescription for preparing photomasks photomasks
used in fabrication used in fabrication
From circuit designer to process mask engineer From circuit designer to process mask engineer
Trade Trade- -off between off between yield, circuit area, reliability yield, circuit area, reliability
Two broad components to design rules: Two broad components to design rules:
Minimum Minimum dimension associated with a particular dimension associated with a particular feature feature
Allowable separation Allowable separation and and overlap between layers overlap between layers
Geometric constraints on design rules ensure that fabricated Geometric constraints on design rules ensure that fabricated
patterns will patterns will preserve preserve the the topology topology and and geometry geometry of the design of the design
Design rules are usually proprietary to a company Design rules are usually proprietary to a company
Design Rules, Cont
Design Rules, Cont

d
d
Design rules are described in two ways Design rules are described in two ways
Absolute ( Absolute ( micron micron ) or ) or
relative ( relative ( ) rules ) rules
The l rules are simplifications of micron rules, and can be scal The l rules are simplifications of micron rules, and can be scaled ed
The value of The value of may be defined as may be defined as
= = f f/2 /2
Feature size Feature size f f = distance between source and drain = distance between source and drain
Set by minimum width of Set by minimum width of polysilicon polysilicon
Design Rules, Cont
Design Rules, Cont

d
d

Design rules represent
Design rules represent
tolerances
tolerances
which would
which would
insure a high probability of correct fabrication
insure a high probability of correct fabrication

They are not a hard boundary between correct
They are not a hard boundary between correct
and incorrect operation
and incorrect operation

Deviations
Deviations
in line widths during processing:
in line widths during processing:

If line widths are too small, line may break
If line widths are too small, line may break

If a via is too small, it may open or have high
If a via is too small, it may open or have high
resistance
resistance

Wires placed too close to each other may short
Wires placed too close to each other may short
The MOSIS Scalable CMOS Rules
The MOSIS Scalable CMOS Rules
- -based rules based rules
Designs using these rules are fabricated by a variety of Designs using these rules are fabricated by a variety of
companies companies
Multiple designs are put on a single die. Each chip wired to a Multiple designs are put on a single die. Each chip wired to a
particular design particular design
Support for submicron digital CMOS, analog (buried poly Support for submicron digital CMOS, analog (buried poly
layer for capacitor), layer for capacitor), micromachines micromachines, etc. , etc.
W/L ratio determine transistor size (and hence speed, area, and W/L ratio determine transistor size (and hence speed, area, and
power) power)
Typical design flow
Typical design flow
-
-
Mask Layout
Mask Layout
MOSIS Layout Design Rules
MOSIS Layout Design Rules
(Sample set)
(Sample set)
R1 Minimum active area width 3 R1 Minimum active area width 3
R2 Minimum active area spacing 3 R2 Minimum active area spacing 3
R3 Minimum poly width 2 R3 Minimum poly width 2
R4 Minimum poly spacing 2 R4 Minimum poly spacing 2
R5 Minimum gate extension of poly over active 2 R5 Minimum gate extension of poly over active 2
R6 Minimum poly R6 Minimum poly- -active edge spacing 1 active edge spacing 1 (poly outside active (poly outside active
area) area)
R7 Minimum poly R7 Minimum poly- -active edge spacing 3 active edge spacing 3 (poly inside active (poly inside active
area) area)
R8 Minimum metal width 3 R8 Minimum metal width 3
R9 Minimum metal spacing 3 R9 Minimum metal spacing 3
R10 Poly contact size 2 R10 Poly contact size 2
MOSIS Layout Design Rules
MOSIS Layout Design Rules
(Sample set)
(Sample set)
R11 Minimum poly contact spacing 2 R11 Minimum poly contact spacing 2
R12 Minimum poly contact to poly edge spacing 1 R12 Minimum poly contact to poly edge spacing 1
R13 Minimum poly contact to metal edge spacing 1 R13 Minimum poly contact to metal edge spacing 1
R14 Minimum poly contact to active edge spacing 3 R14 Minimum poly contact to active edge spacing 3
R15 Active contact size 2 R15 Active contact size 2
R16 Minimum active contact spacing 2 R16 Minimum active contact spacing 2 (on the same active (on the same active
region) region)
R17 Minimum active contact to active edge spacing 1 R17 Minimum active contact to active edge spacing 1
R18 Minimum active contact to metal edge spacing 1 R18 Minimum active contact to metal edge spacing 1
R19 Minimum active contact to poly edge spacing 3 R19 Minimum active contact to poly edge spacing 3
R20 Minimum active contact spacing 6 R20 Minimum active contact spacing 6 (on different active (on different active
regions) regions)
MOSIS Layout Design Rules
MOSIS Layout Design Rules
(Sample set)
(Sample set)
Simplified Design Rules
Simplified Design Rules
CMOS Inverter Layout
CMOS Inverter Layout
Nano-Electronics 1 - 100 nanometer
range
Moores Law Continues
CMOS Inverter Layout
CMOS Inverter Layout

Selective breakdown of a multi Selective breakdown of a multi- -walled carbon walled carbon nanotube nanotube and the building of and the building of
nano nano- -tube transistors tube transistors
IBM Scientists Develop Breakthrough
IBM Scientists Develop Breakthrough
Transistor Technology with Carbon
Transistor Technology with Carbon
Nanotubes
Nanotubes