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EE 432/532
Metal Contact Lithography CyMOS process
April 22, 2014

Group 5

Group leader Rui Li
Zhen Zhang
Mouhamadou Diallo
Ximeng Sun

Lab instructor Clinton Young

Overview
We are finally coming to the last fabrication step of the CyMOS process. We initially started
with growing a layer of field oxide on a bare n-type Silicon wafer. Then we created, through
photolithography and a two-step diffusion, a PWELL that serves as substrate for the NMOS
devices. Then through the same techniques we have created the source and drain regions of the
PMOS then of the NMOS. The final step in making working transistors was to create the gate
regions through lithography and oxidation. Figure 1 depicts the current state of our device and
test wafers.

Figure 1: Current state of the CyMOS process after gate oxidation
(White-Si, green-B, brown-P, blue-SiO2)
Now the final fabrication step of the CyMOS process is contact and vias lithography followed
with aluminum deposition through electron-beam evaporation, and metal patterning.
Photolithography
Photolithography is a process that allows the user to give a set of predefined patterns to the
surface of a wafer. The steps involved in the process are photoresist application, soft baking,
mask alignment, exposure, development, and hard baking. Photoresist is a light sensitive
polymer that changes chemical structure when exposed to UV light, allowing the exposed parts
to be soluble in the developer solution. First we spin about 4 drops of HMDS
(hexamethyldisilazane) on the surface of the wafer at 4000 rpm for 20 seconds. This is done to
promote adhesion of the photoresist on the surface of the wafer. In our process we spin coat
AZ5214 (photoresist) at 4000 rpm for another 20 seconds. We pay great attention in producing a
thin uniform layer of photoresist with no air bubble trapped. The next step is to prebake the
wafers at 90C for 25 minutes, in order to evaporate the coating solvent and densify the
photoresist after spin coating. Then we move to the alignment and exposure step during which

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we select the region to be exposed through the use of the corresponding mask (see figure 1). This
process is particularly tedious as we need to match the patterns on the mask and the wafer in
order to make sure the correct regions will be etched. The wafers are then exposed to UV light
for 90 seconds, then immersed in a developer solution (MIF-300) for another 90 seconds in order
to dissolve the exposed regions. Finally the wafers are baked at 120C for 20 minutes for the
purpose of hardening the photoresist and improving adhesion to the wafer surface.

Figure 2: Overview of alignment/expose/develop steps (R.B. Darlings)

In this lab we first perform the lithography process to create openings through the field oxide for
the source, drain and gate contacts using mask 5. Then the last step in contact via lithography is
the SiO2 etch and photoresist strip. The SiO2 etch is done through a buffered oxide etching
(BOE), using TW2 as our etch rate indicator using the fact that Si is hydrophobic while SiO2 is
hydrophilic. The wafers are left in the BOE for about 5 minutes then dipped into the cascade
rinse to verify if the etching is complete. This process is repeated every 30 seconds as often as
necessary. Overall the BOE lasted for 11 minute, then the wafers were put in cascade rinse for 2
minutes, then dipped into acetone for 4 minutes to strip away the photoresist and methanol for 1
minute to dissolve the acetone.

Figure 3: Cross-sectional view of wafers after contact via lithography
(White-Si, green-B, brown-P, blue-SiO2)

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The second photolithography step occurs after the aluminum deposition and follows overall the
same process as the initial one. The only difference lies in the etching step, at which we use a
solution of Phosphoric, Acetic, and Nitric acids (PAN) instead of BOE, to pattern the aluminum.
The etching time is also lower (3-5 minutes) and does not require the use of test wafers.

Figure 4: CMOS after metal patterning
(White-Si, green-B, brown-P, blue-SiO2 and grey-aluminum)

Metallization
In order to test our devices and evaluate the CyMOS process, we need to extract electrical
parameters from our various devices. Therefore we need to make electrical contact between
devices and test equipment. Similarly in a commercial process individual devices are meant to be
interconnected through metal lines in order to make integrated circuits. The procedure of creating
the metal interconnects, typically made of aluminum or copper, is called metallization. First the
SiO2 on the wafer is patterned through lithography and etching, removing the regions of contact.
Then a layer of metal is deposited on the surface usually through physical or chemical vapor
deposition (PVD or CVD). The basic idea behind PVD is to heat the source material inside an
evacuated chamber to the point where it will evaporate, then the vapor diffuses and condenses on
the relatively cool substrate, effectively depositing a layer of metal.

Figure 5: generic evaporation system

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For our process we use electron beam evaporation to deposit aluminum on our wafers. Figure 6
describes a basic e-beam system.

Figure 6: Basic e-beam heating system

In the system, the source wafer is placed in a crucible usually made of grapheme. Underneath a
filament is heated with a very high current on the order of 100A. Some electrons in the filament
acquire enough thermal energy to escape from the material and are accelerated by a big electric
field (V10KV) and then directed towards the source by a magnetic field. The succession of
collision between electrons and the source result in heating up the material to evaporation
temperatures. The advantages of using e-beam heating systems lies in obtaining a good control
over the emission current, being able to sweep a very small spot size and finally also having
large reservoir of source materials. In addition in order to maintain uniformity over the different
wafers, the e-beam evaporation system also uses a planetary substrate holder.


Figure 7: E-beam system with planetary substrate holder



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Results
a. Contact and via lithography:
The contact via lithography occurred without any major issues. As usual aligning the wafers with
the mask was a very tedious process. The resulting openings on the field oxide turned out to be
very good as shows figure 8.


Figure 8: Devices after contact openings

The total SiO2 etch time was of 11 minutes. One of our device wafers has been overdeveloped
during photolithography as can be seen in figure 9.


Figure 9: Overdeveloped wafer

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b. Aluminum deposition:
We have done a manual four-point probe measurement on two of our device wafers as well as
TW1 and TW2 in order to obtain the aluminum sheet resistance (from the device wafers) as well
as the sheet resistance of the phosphorous source and drain diffusion from TW1 and boron
source and drain diffusion from TW2. The thickness of the deposited aluminum layer was
measured with the Filmetrics system to be 0.315m.


Figure 10: Calculation table for metal contact sheet resistance

As expected the metal sheet resistance is very low. However we notice that the boron diffusion
and phosphorous sheet resistance are about two order of magnitudes apart. This is due to the fact
that the phosphorous sheet resistance consist of the diffused phosphorous layer added to the
boron diffused layer from the PWELL. The combination of these two layers is modeled as
parallel resistances. Consequently the sheet resistance of TW1 is as should be expected much
lower than the sheet resistance of TW2.

c. Metal patterning

The photolithography after the aluminum deposition was more difficult than usual, because of
the high reflectivity of the aluminum. However we managed to make good contacts on most of
our devices as can be seen in figure 11.
We have also noticed some defective devices after taking the pictures (figure 12) mostly
suffering from over etching and misalignment with mask 6.

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Figure 11: Successful metal patterning devices


Figure 12: Misaligned PMOS (left) and over etched NMOS (right)



Appendix
We have attached the process traveler pages for Pattern for contact vias, Metallization as well as
Contact Metallization as Appendix.

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