Design of Inductor

DESIGN AND TEST OF INTEGRATED INDUCTORS
FOR RF APPLICATIONS
Design and Test
of Integrated Inductors
for RF Applications
by
Jaime Aguilera
Vision Technologies,
Spain
and
Roc Berenguer
Centro de Estudios e Investigaciones Tcnicas de Gipuzkoa (C.E.I.T.),
Spain
KLUWER ACADEMIC PUBLISHERS
NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
eBook ISBN: 0-306-48705-5
Print ISBN: 1-4020-7676-2
2004 Kluwer Academic Publishers
New York, Boston, Dordrecht, London, Moscow
Print 2003 Kluwer Academic Publishers
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Contents
Dedication v
Contents vii
List of Figures xi
List of Tables xvii
List of Abbreviations xix
Preface xxi
1. Introduction 1
4
8
9
1.
2.
Conventional IC fabrication technologies
Keys to progress in RF transceiver design; High Q integrated inductors
2.1 LC Parallel Tank
2.1.1
2.1.2
Low Noise Amplifiers (LNA)
Voltage Controlled Oscillators (VCO)
2.2
2.3
Inductive degeneration for matching purposes
RF Filters
3. The challenge of integrating high quality inductors
3.1
3.2
Metal losses
Substrate losses
4. Structure of the book
11
14
16
18
19
20
21
21
viii Design and test of integrated inductors for RF applications
2. General considerations
1. Ways of integrating an inductor
1.1
1.2
Conventional fabrication processes
Non-conventional fabrication processes
23
23
24
27
28
29
30
30
31
34
35
36
37
37
38
38
40
41
41
44
45
47
48
48
49
50
51
51
51
53
54
56
58
60
63
66
66
68
73
75
76
76
2. Spiral inductors on silicon based technologies
2.1 Physical overview: Difficulty of integrating an inductor
2.1.1 Inductance
2.1.1.1
2.1.1.2
2.1.1.3
Self inductance
Mutual inductance
Total inductance
2.1.2 Resistance
2.1.2.1
2.1.2.2
Skin effect
Proximity effects
2.1.3 Parasitic effects in the substrate
2.1.3.1
2.1.3.2
Magnetically induced parasitic effects in the substrate
Electrically induced parasitic effects in the substrate
2.1.4 Parasitic capacitance between metal turns
2.2 Spiral inductor electrical models
2.2.1
2.2.2
2.2.3
model
Transformer model
Wideband model
2.3 Quality factor definition
2.3.1
2.3.2
2.3.3
definition
definition
definition
2.4 Different attempts to predict the performance
2.4.1
2.4.2
2.4.3
Field electromagnetic simulators
ASITIC
Method based in the model parameter definition
2.5 Quality factor improvement methods
2.5.1
2.5.2
2.5.3
2.5.4
Broken guard ring
Biased N-well beneath the inductor
Substrate shielding
Non conventional fabrication processes
3. Inductors test and characterization
1. On wafer measuring equipment
1.1
1.2
1.3
1.4
Vector Network Analyzer
Probes
Probe station
Commercial calibration kits
2. Measuring accuracy and Repeatability
2.1 Different types of measuring errors
Design and test of integrated inductors for RF applications ix
2.2
2.3
Random errors
Systematic errors
77
77
78
79
80
80
82
85
87
88
89
89
90
91
92
93
95
96
102
104
105
109
113
113
114
114
115
115
115
116
118
118
120
121
127
2.3.1
2.3.2
2.3.3
Systematic errors due to VNA
Cables and connectors
Probes
2.4 Calibration
2.4.1 SOLT Calibration
2.5 Repeatability and accuracy
3. Measuring configuration: 1-port versus 2-port configuration
3.1 General Case
3.1.1
3.1.2
3.1.3
Two-Port measurement with the device placed in series
Two-Port measurement with the device placed in parallel
One-Port measurement
3.2 Inductor model case
3.2.1
3.2.2
3.2.3
Two-Port measurement with the model placed in series
Two-Port measurement with the model placed in parallel
One-Port measurement
3.3 Sensitivity analysis
4. Test fixture design
4.1
Substrate related issues
4.1.1
4.1.2
Interterminal coupling
Interport coupling
4.2 Metallization related issues
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
Pad material
Probe tip material
Probe alignment
Setup stability
Tolerances
Wear of the probes and the pads
4.3 General Guidelines
5. De-embedding techniques
5.1
5.2
5.3
Test-fixture model
In-fixture standards
De-embedding procedure
6. model inductor characterization
4. Influence of the geometric parameters on the inductors performance:
Design rules 135
135
137
137
139
141
1.
2.
Problem description
Analytical study and simulations
2.1
2.2
2.3
Number of sides
Spacing between tracks
External radius and number of turns
x Design and test of integrated inductors for RF applications
2.3.1
2.3.2
Number of turns
External radius
2.4
2.5
Width
Metal layers connected in parallel
141
142
143
145
148
148
149
150
152
153
156
158
160
162
163
165
167
168
168
168
169
170
173
177
185
3. Empirical study
3.1
3.2
3.3
Inductor selection
Fabrication and measurement
Analysis of the empirical data
3.3.1 External radius and number of turns
3.3.1.1
3.3.1.2
Influence of the proximity effect on the internal turns
Link between the track width and proximity effect
3.3.2
3.3.3
3.3.4
Skin and corner effects
Geometry of the via
Track width higher than
4. Design considerations
5. Inductors design flow
1.
2.
Generation phase
Filtering phase
2.1
2.2
Inductance filtering
CM and internal radius
3.
4.
Performance estimation phase
Verification phase
Appendix
References
Index
List of Figures
Figure 1-1.
Figure 1-2.
Figure 1-3.
Weight and size improvement experimented by mobile phones from
year 1993 to 2001. 2
3 a)Super heterodyne and b) Low IF radio architectures.
RF Technologies: a)GaAs MESFET b) GasAs HBT
Si-Bipolar d) SiGe HBT e) CMOS
c) Advanced
7
9
10
12
13
14
15
17
Figure 1-4.
Figure 1-5.
Figure 1-6.
Figure 1-7.
Figure 1-8.
Figure 1-9.
Parallel LC tank circuit.
Realistic model for a parallel LC tank.
Narrow-band differential low noise amplifier topology.
Simplified small signal equivalent circuit.
Different VCO topologies depending on implemented feedback.
Basic LC-tuned oscillator.
Figure 1-10.
Figure 1-11.
LNA input with inductive degeneration.
Small signal equivalent circuit of the input of the LNA of Figure 1-10.
Figure 1-12.
Figure 1-13.
Figure 2-1.
Figure 2-2.
LC Low-pass filter.
Loss mechanisms.
Microphotography of a squared, octagonal, and icosagonal inductor
18
19
20
24 with a CMOS technology.
Microphotography of a voltage controlled oscillator using two spirals
fabricated with a CMOS technology in a mirror configuration.
25
25
26
26
27
Figure 2-3. Microphotography of a balanced inductor fabricated on a
SiGe.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Geometry of a centre-tapped inductor.
Diagram of a multilevel inductor using two metal layers.
Multilevel geometry for maximizing the inductance per unite area.
xii
Figure 2- 7.
Figure 2-8.
Figure 2-9.
Design and test of integrated inductors for RF applications
Microphotography of: a) toroidal inductor b) solenoidal inductor with
inclined top and bottom conductor [Ahn98] and c) solenoidal inductor
28
Cross-section of an integrated spiral inductor on a Si technology and
the physical effects that arise when a time-varying voltage is applied
29
Self inductance value for a rectangular conductor versus its length and
31
32 Figure 2-10.
Figure 2-11.
Method for computing the GMD between areas.
Mutual inductance of two rectangular conductors versus distance
between centres and width. 33
Figure 2-12. Mutual inductance of two rectangular conductors versus width and
separation between them. 33
Figure 2-13. Illustration of the positive and negative mutual inductance of a
squared planar spiral. 35
36 Figure 2-14.
Figure 2-15.
Figure 2-16.
Figure 2-17.
Illustration of the skin effect in a rectangular conductor.
Schematic representation of the induced currents in the substrate
to the magnetic field penetration.
due
38
39
the
40
Schematic representation of the metal-substrate capacitance.
Schematic representation of the displacement currents due to
metal-substrate capacitance.
Figure 2-18. Schematic representation of the parasitic capacitance between layers
and metal tracks. 41
42
44
45
46
49
52
54
55
56
the
57
58
59
the
61
63
64
Figure 2-19.
Figure 2-20.
Figure 2-21.
Figure 2-22.
Figure 2-23.
Figure 2-24.
Figure 2-25.
Figure 2-26.
Figure 2-27.
Figure 2-28.
Two-port model.
One-port model.
Transformer Model.
Wideband model.
Simplified model.
Equivalent energetic model for the one-port model.
Schematic view of a spiral with a broken guard ring.
One-port model of a spiral with a broken guard ring.
Schematic view of an inductor with a biased N-well beneath it.
One-port model of an inductor with a biased N-well beneath
inductor.
Figure 2-29.
Figure 2-30.
Figure 2-31.
Figure 3-1.
Figure 3-2.
One port model of a spiral with substrate shielding.
View of a squared spiral with a patterned ground shield underneath
the spiral.
Microphotography of an inductor without substrate underneath
spiral [Chan98].
Individual die mounted on a test fixture.
Basic elements involved in the characterization of a passive element.
with parallel conductor [Yoon99].
across its ends.
width (the thickness is fixed at
Design and test of integrated inductors for RF applications xiii
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 3-6.
Figure 3-7.
Figure 3-8.
Figure 3-9.
Figure 3-10.
Figure 3-11.
Figure 3-12.
Figure 3-13.
Figure 3-14.
Figure 3-15.
Figure 3-16.
Figure 3-17.
Figure 3-18.
Figure 3-19.
Figure 3-20.
Figure 3-21.
66
67
68
69
70
71
71
72
73
74
76
78
79
81
82
83
84
85
87
88
89
90
91
92
92
93
96
103
105
106
107
108
Test fixture and DUT.
Applicability of the different measuring methods.
Simplified block diagram of a vector network analyzer.
Typical construction for an air coplanar probe (ACP).
Electric field pattern of a balanced and unbalanced coplanar probe.
Coplanar probe planarization (Reference plane definition).
Checking of the probe tip planarity by means of a contact substrate.
Alignment marks to set skating.
Resulting open stub under the probe due to skating.
Standard setup of a manual probe station.
General purpose impedance standard substrate (ISS).
VNA based system.
Major systematic errors.
Measuring setup 12 term error model.
ISS short standard.
ISS load standard.
Comparision between load and short reflection responses.
ISS thru standard.
Three possible configurations for measuring a two-port device
with a VNA.
Figure 3-22.
Figure 3-23. Setup for the calculation of the scattering parameters of a two-port
measurement with the device placed in series.
Figure 3-24.
Figure 3-25.
Setup for the calculation of the scattering parameters of a two-port
measurement with the device placed in parallel.
Setup for the calculation of the scattering parameters of a one-port
measurement.
Figure 3-26.
Figure 3-27.
model of an integrated inductor.
measurement with the model placed in series.
Figure 3-28.
Figure 3-29.
measurement with the model placed in parallel.
measurement.
Figure 3-30.
Figure 3-31.
Figure 3-32.
Inductor measurement with and without de-embedding.
Test fixture interterminal and interport coupling.
ground (G) pads.
Figure 3-33.
Figure 3-34.
Configuration to measure the input capacitance of a generic device
with value
Different pad shapes.
Two port network.
Setup for the calculation of the scattering parameters of a one-port
General model for the coupling mechanism between signal (S) and
xiv Design and test of integrated inductors for RF applications
Figure 3-35.
Figure 3-36.
Figure 3-3 7.
Figure 3-38.
Figure 3-39.
Figure 3-40.
Figure 3-41.
Figure 3-42.
Figure 3-43.
Figure 3-44.
Figure 3-45.
Figure 3-46.
Figure 3-47.
Figure 3-48.
Figure 3-49.
Figure 3-50.
Figure 3-51.
Figure 3-52.
Figure 3-53.
Figure 3-54.
Figure 3-55.
Figure 3-56.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Recommended implementation of a signal pad for a
108
Interport coupling of different test-fixtures with different distances
110
Cross sectional view of two test-fixtures with and without ground
111
Interport coupling measurement of two test-fixtures with and without
ground contacts. 112
Interport coupling measurement of different test-fixtures, where the
113
Measured mean and standard deviation of the DC contact resistance
115
Contact resistance degradation after reprobing over the same pad
116
Use of n-well or metal shield underneath the pads to reduce effect of
Test-fixture model.
117
119
120
In-fixture standards: single open, single short, open and short standars.
121
122
123
124
126
128
128
129
130
Measurement of the single short.
Measurement of the single open.
Measurement of the short standard.
Measurement of the open standard.
Integrated inductor model.
Microphotography of the inductor to model.
and of the inductor under test.
and of the inductor under test.
Comparison between the de-embedded S-parameters of the integrated
131
Comparison of the real part between the measured and simulated data.
132
Comparison of the imaginary part between the measured and
133
135
137
138
Geometric parameters that define an integrated inductor.
Ideal variation of the quality curve as the track width is increased.
Quarter of a square and circular inductor.
Simulation of the influence of the number of sides on the quality at
139
Simulation of the influence of the spacing on an inductors quality. 140
Simulation of the influence of the number of turns on an inductors
quality. 142
CMOS
process.
between ports and different types of substrate.
contacts.
pads are placed at different distantes: and
for different applied skate.
several times.
parasitic pad capacitance
Integrated inductor test-fixture.
inductor and simulated S-parameters of the obtained model.
simulated data.
1.8GHz.
Design and test of integrated inductors for RF applications xv
Figure 4-7.
Figure 4-8.
Figure 4-9.
Figure 4-10.
Figure 4-11.
Figure 4-12.
Figure 4-13.
Figure 4-14.
Simulation of the resistance for different track widths.
Different possibilities of connecting two metal layers in parallel.
Equivalent circuit used to simulate the influence of the via area.
Microphotography of some of the fabricated inductors.
Microphotography of one of the de-embedding structures.
Measured inductance and quality of a 2.8 nH inductor.
Measured resistance of a 2.8 nH inductor.
144
146
147
149
150
151
151
Measured resistance of several inductors with a track width of
154
Figure 4-15.
Figure 4-16.
Figure 4-17.
Figure 4-18.
Measured resistance of two pairs of inductors with the same
155
Measured resistance of two inductors used to analyze the effect of the
156
157 Proximity effect between two metal layers connected in parallel.
Measured resistance of eight inductors selected to demonstrate that the
influence of the skin and corner effect is minimum in comparison to
159
Figure 4-19. Zoomed out of the resistance curves of b_5, Bo_21, Bo_24 and
Bo_62. 160
Figure 4-20.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Measured quality and inductance of a same geometry with different
vias. 161
166
170
171
Proposed design flow.
Relation between and an inductors area.
Relation between and an inductors area.
the proximity effect.
width on the proximity effect.
inductance.
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List of Tables
Table 1-1. Commonly used technologies for communication components
5
Table 1-2.
Table 3-1.
Table 3-2.
Table 3-3a.
Table 3-3b.
Table 3-4a.
Table 3-4b.
Table 3-5.
Performance comparison of some RF IC Technologies [Kuc00].
Geometrical characteristics of the fabricated inductor.
model parameters of the fabricated inductor.
Results of the analysis of the parameter: (a) Argument.
Results of the analysis of the parameter: (b) Module.
Results of the analysis of the parameter: (a) Argument.
Results of the analysis of the parameter: (b) Module.
8
97
97
98
99
100
101
General values for substrate and metallization parameters of some
104
128
130
138
143
147
154
155
158
159
Geometric characteristics of the inductors used to analyze the
161
Table 3-6.
Table 3-7.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 4-5.
Table 4-6.
Table 4-7.
Table 4-8.
fabrication technologies.
Dimensions of the balanced inductor.
Optimization result.
Relation between the number of sides and the quality of an inductor.
Skin depth for the aluminum at 1 GHz.
Variation of the inductance and resistance with the via area.
Resistances slope of the selected inductors.
CM and internal radius on an inductors performance.
Geometric characteristics of the inductors used to analyze the effect of
Relevant geometric characteristics of the inductors used to
demonstrate that the influence of the skin effect is minimum on
inductors with a track width between 10 and
Resistances slope of the selected inductors.
influence of the geometry of the via.
[Kuc00].
xviii Design and test of integrated inductors for RF applications
Table 4-9.
Table A-1.
than
Relevant data of five measured inductors with a track width higher
Geometrical characteristics of the fabricated inductors.
162
173
List of Abbreviations
AC
ACP
AlSiCu
AMS
Au
BeCu
BiCMOS
BJT
CM
CMOS
CSP
Cu
DC
DECT
DUT
EDGE
EPI
F
GaAs
GMD
GPRS
GSM
Alternating current
Air Coplanar Probe
Aluminum Silicon Copper
Austrian Mikro Systeme AQ
Gold
Berillium Copper
Bipolar Complementary Metal Oxide Semiconductor
Bipolar Junction Transistor
Metal Quantity
Complementary Metal Oxide Semiconductor
Chip Scale Package
Copper
Direct Current
Digital Enhanced Cordless Telecommunication
Device Under Test
Enhaced Data Rated for GSM Evolution
Epitaxial
Noise Figure
GalliumArsenide
Geometric Mean Distance
General Package Radio Service
Global System Mobile
xx Design and test of integrated inductors for RF applications
HBT
IC
IF
ISS
LNA
LO
LRM
LRRM
MESFET
PA
PCB
Q
RF
SA
SiGe
SOLT
TRL
UMTS
VCO
VLSI
VNA
W
WLAN
Heterojunction Bipolar Transistor
Integrated Circuit
Intermediate Frequency
Impedance Standard Substrate
Low Noise Amplifier
Local Oscillator
Line, Reflect, Match
Line, Reflect, Reflect, Match
Metal Semiconductor Field Effect Transistor
Power Amplifier
Printed Circuit borrad
Quality Factor
Radio Frequency
Spectrum Analyzer
Silicon-Germanium
Short, Open, Load, Thru
Thru, Reflect, Line
Universal Mobile Telecommunications System
Voltage Controlled Oscillator
Very Large Scale Integration
Vector Network Analyzer
Tungsten
Wireless Local Area Network
Preface
This book is the result of several years of research on the field of
radiofrequency integrated circuit design, specifically on the design of
integrated inductors for RF applications on conventional technologies.
One of the key elements today in the wireless industry, especially in the
silicon RF integrated circuits field, is the design of high-quality passive
elements. The performance of several basic RF blocks such as low noise
amplifiers, mixers and voltage controlled oscillators depends on the quality
of these elements.
The work done establishes the design guidelines for the definition of the
inductors geometrical characteristics and new techniques to improve their
quality. It also covers their measurement and characterisation. This fact is
not always taken into account by the designers due to the lack of information
in bibliography regarding to this topic.
The approach of this book is novel due to two facts; first it tries to help
designers with poor or none experience by describing the whole design flow
of an inductor. From the definition and analysis of the physical effects that
appear in them to their modelization. It also covers issues such as the
maximization of the quality factor by a correct definition of the geometry,
novel aggressive design rules, measuring setup, test-fixture parasitics de-
embedding, etc.
Secondly it will help designers with high experience due to the fact that,
based on empirical data, some design rules that have been widely used by
the design community have been proved to be conservative and breaking
them will lead up to higher quality designs.
To make intuitive and helpful to any designer, the book has been
structured as follows. The first chapter shows how the performance of some
xxii Design and test of integrated inductors for RF applications
RF building blocks, like LNAs, VCOs or RF Filters, highly depend on the
quality factor of the integrated inductors used to implement them.
It also introduces the difficulty that entails the integration of RF passive
elements in conventional Si based low cost technologies, due to metal losses
and substrate losses.
Chapter 2 covers some general considerations like the physical analysis
of the integrated inductor, the existing electrical models to model them
model, transformer model or wide band modified model), or some
methods to improve the quality factor of an integrated inductor (Broken
guard rings, Substrate shielding, etc.).
Inductors test and characterization is covered in chapter 3. In the
inductor modelling, the accurate measurement of the device is very
important due to the fact that these are elements with very low resistance,
where a single ohm makes a big difference in the quality factor. This is the
reason why the book also covers the design of the test fixture and the
measurement setup.
Chapter 4 analyses the influence of the geometrical parameters in the
inductors performance and will establish the design guidelines for the
definition of the elements geometrical characteristics. These design
guidelines are derived from analytical and empirical data. It also introduces
some new techniques to improve the quality factor.
Finally due to the fact that foundries only supply models for discrete
values of inductance, and that these inductors are not optimized for an
specific frequency range, there is a need of an inductors design flow in
order to be able to obtain a specific inductor value, optimized for a specific
application or what is the same a specific frequency range. The inductors
design flow is covered in chapter 5, where design rules derived in chapter 4
are applied.
We also wish to express our gratitude to all persons who have contributed
to the development of this book. We would like to thank Prof. Andrs
Garca-Alonso and Prof. Joaquin de No for all their support. Our thanks also
goes to the University of Navarra, and CEIT for offering us the possibility of
this research work and all our colleagues at the Electronics and
Communication department (Guillermo, Juan, Erik, Iigo, Josu, ...) for their
direct or indirect contributions to this work. We would also like to thank
Mrs. Carmen Conde for her comments and corrections to our English.
Finally, we thank to our families for their support and patience. Without
it this book would not have been possible.
Jaime Aguilera
Roc Berenguer
Chapter 1
INTRODUCTION
The fast growing of the wireless market has created an urgent demand for
smaller and cheaper handsets with increased functionality and performance
while still meeting the tight constraints for mass production within a short
product life cycle.
The successful achievement of these conflicting trends has been possible
due to the development of key technical capabilities in the design and
production of each new wireless device generation.
In the baseband section of the handset, the great development
experimented by the CMOS processes in the last decade, has shrunk the
silicon real estate required for the processor, memory and interface ICs.
The advanced chip scale package (CSP) techniques and multi-layer
laminate printed circuit boards (PCB) have minimized the electronic
interconnect and packaging volume. The battery technology has advanced
from the older nickel cadmium and nickel metal-hydride to the lithium ion
and lithium polymer technologies, improving the battery pack size, weight
and performance. The antenna has migrated from outside in the old designs
to inside the plastic housing in the new ones, giving more freedom in the
handset form and design. As it is shown in Figure 1-1, all these
improvements have led to lighter, smaller and compact handsets.
In contrast to this situation, the improvement in the passive component
content of the handset has been much less dramatic compared to other
technical areas. This inertia has not been due to the lack of attention by the
set-makers or in the literature.
2 Introduction
Design and test of integrated inductors for RF applications 3
It is estimated that in a single-mode telephone, passive components
suppose the 90 percent of the component count, 80 percent of the size and 70
percent of the cost [Pul02]. High quality passive components are specially
prevalent in the RF Front-end and radio transceiver sections of the wireless
terminal, and these increase proportionally as new standards (GPRS, EDGE,
UMTS, Bluetooth, ...), are incorporated to the handset. In addition to
dominating the component count, size and cost of the terminal the large
number of passive components is a major factor in the assembly line
production and yield and contribute to unwanted reliability failures. Thus a
big research effort has been done in that field in order to reduce the passive
component count of the handset.
4 Introduction
One of the main methods to reduce the passive component content of the
mobile device has focused primarily on optimizing the system architecture
and partitioning to increase the level of integration on the ICs without
sacrificing the performance or cost. In the radio transceiver section, as it is
shown in Figure 1-2, the move from the super heterodyne architecture to the
zero or low IF architecture has eliminated the set of passive components
required for the IF functions, thus reducing the number of required passive
devices.
But the direct approach to reduce the passive component content in the
mobile terminal is the integration of the passive components into a substrate.
This trend has been accelerated by the steady improvement in the
performance of the passive components integrated in the RF IC processes,
enabling the integration of passive components on chips where previously
only external surface mount components could meet the required RF
performance.
The following chapters explore the possibility of obtaining high quality
integrated inductors on low cost silicon substrates and the test considerations
to obtain accurate models of them. Previously, next section briefly describes
the competing RF fabrication technologies where the inductors can be
integrated. After that, section 2 illustrates how the quality factor of the
integrated inductor determines the performance of the basic RF building
blocks like Low Noise Amplifiers (LNAs), Voltage Controlled Oscillators
(VCOs) or filters. Section 3 gives a short introduction of the challenge of
integrating high quality inductors, and finally section 4 establishes the need
for an inductor design flow.
1. CONVENTIONAL IC FABRICATION
TECHNOLOGIES
The competing technologies on the RF market are briefly described in
this section. Traditionally, the GaAs based technologies were the preferred
option to implement the RF part of the mobile handsets.
The MESFET still is the working horse GaAs technology. It is mostly
based on ion implantation into semi insulating substrates (Figure 1-3a). This
is the least expensive process concerning raw material cost, since no
epitaxial layers are required. The technologies on the market are processed
with gate length from down to values in the range of
25GHz are available in production depending on the gate length used. FETs
can easily achieve noise figures below 1 dB in the 1-2GHz frequency range.
The other still used GaAs technology is the based on HBT transistors.
The HBT transistor is a modified bipolar transistor (Figure 1-3b). The
emitter and base layers are formed with different band gap materials. The
emitter having the wider band gap, thus the emitter delivers a barrier against
the hole injection into the base. In this way, the main deficiencies of a
standard homojunction bipolar are overcome. Due to the required EPI layer
the raw material cost is higher compared to MESFET. The min feature size
for GaAs based HBTs are about width. in the range of 30-
60GHz is reached in production. The HBT delivers an excellent RF power
density due to its vertical current flow.
These two GaAs technologies based on HBTs and MESFET transistors
covers arround 15 to 20 % of the RF applications on the market [Ber99]. As
shown in table 1.1, these RF applications are limited to the RF power
amplifiers (PA) and Low Noise Amplifiers (LNA) of medium and high
performance systems like GSM, DECT or CDMA. The other RF
applications are covered by the Silicon based technologies mainly due to
their lower cost.
6 Introduction
The most used Si based technologies to implement the RF function of
commercial handsets are the advanced silicon bipolar processes and the SiGe
processes. The advanced performance silicon bipolar processes with the
up to 25GHz are processed on refined high performance IC technology lines.
Standard feature sizes of emitter width in double poly self aligned
technique, side wall spacer technique, buried layers, selective implanted
collector are build into these highly sophisticated devices (Figure l-3c).
Even more advanced technologies with further shrunk emitter widths are
available with up to 45GHz. One of the biggest advantages of the Si
processes is the potential to use the high integration capability of Si. Not
only in highly integrated bipolar only circuits, but also the combination with
CMOS technology offering the possibility of integration of the RF functions
and the baseband functions in one chip.
The SiGe HBT is a further improvement of the Si advanced bipolar
process. The base layer is replaced by a hetero SiGe layer (Figure 1-3d).
Features sizes of emitter width with up to 75GHz are achieved
using advanced sophisticated processes. The other processes optimised for
low noise applications show in production from 60 to 70GHz. Like the
advanced silicon bipolar processes, the SiGe processes take advantage of the
high integration capability of Si, being also fully compatible with CMOS
technologies. To serve also power applications, higher breakdown voltages
are required. The base layers together with the min feature sizes have to be
enlarged. This reduces the performances drastically; e.g. the goes down to
about 30GHz, that is the reason why this kind of processes have not yet
substituted the GaAs ones in the power amplification function of the
transceiver. The general bipolar advantage of low phase noise is valid for
the SiGe HBT also, and they are widely used on the implementation of
frequency synthesizers.
As it is shown by table 1.1 all baseband functions of the mobile phone
are implemented using digital CMOS processes. The technologies on the
market are processed with gate length from down to (Figure
l-3e). values in the range of 45GHz are available in production depending
on the gate length used. During the last decade there has been a strong
motivation to extend the application of CMOS processes to the RF part, due
to its much lower cost. In fact as shown in table 1.2 the performance of the
MOS transistor is comparable with the performance of the transistors of
other technologies.
But as also illustrated by table 1.2 the quality factor of the passive
integrated on a Si BJT or CMOS processes are poor compared to the
integrated on SiGe or GaAs ones. This is one of the reasons why the
introduction of CMOS processes in the RF part of high and medium
performance transceivers has been delayed, and they are limited to low cost,
low performance systems like Bluetooth or WLAN.
8 Introduction
A key parameter to obtain high performance RF circuits is the quality factor
(Q) of the integrated passives. The next section will explain how the quality
factor of the integrated passives determines the performance of the basic RF
building blocks, like LNA, VCO or RF Filter.
2. KEYS TO PROGRESS IN RF TRANSCEIVER
DESIGN; HIGH Q INTEGRATED INDUCTORS
Figure l-2b shows the block diagram of a low IF front-end. It is
composed by a LNA, a RF Filter, a down conversion mixer and a VCO. One
characteristic of these RF circuits is the relatively large ratio of passive to
active components. In contrast with the digital VLSI circuits or even with
other low frequency analog circuits, such as Op-amps, many of those passive
components may be inductors or even transformers.
A widely used LC network, when implementing LNAs or VCOs, is the
so-called LC parallel tank or simply tank circuit (Figure 1-4). The
performance of these two RF circuits will depend on the quality factor Q of
the tank circuit.
2.1 LC Parallel Tank
For this network, the impedance is:
From inspection of the network or of the Equation 1.1, it is easy to see
that the impedance goes to zero both at DC, because the inductor acts as a
short there, and at very high frequencies, because the capacitor acts like a
short there. We may even say that, at very low frequencies, the networks
impedance is dominated by the inductor, and is that of the capacitor at very
high frequencies. What divides low from high is the frequency at which
the inductive and capacitive parts cancel. Known as the resonance
frequency, this is given by Equation 1.2:
Purely parallel LC networks rarely exist in practice, so it is important to
analyse configurations that might be more real. Because inductors tend to be
significantly lossier than capacitors, the model shown in the Figure 1-5 is a
more realistic approximation to the typical parallel LC tank.
10 Introduction
Let us convert now the circuit of Figure 1-5 to a purely RLC network by
replacing the series LR section by a parallel one. Such a substitution will not
be valid in general; only at frequencies near the resonance the equivalence
will be reasonable. To show this formally, let us equate the parallel and
series impedances of the LR section:
If we equate the real parts, and note that we
obtain equation 1.4.
If we equate now the imaginary parts we obtain equation 1.5.
From inspection of equation 1.4 it is easy to see that the impedance of the
tank at the frequency of resonance is determined by the series resistance
of the inductor and its quality factor Q. To obtain a high impedance value at
the resonance it is necessary to dispose of a high quality inductor or what is
the same an inductor with very low series resistance
Let us analyse in the following section which are the implications of this
statement in the design of low noise amplifiers and voltage controlled
oscillators.
2.1.1 Low Noise Amplifiers (LNA)
As shown by Figure 1 -2 the LNA is the first gain stage in the receiver
path. The most important requirements for the LNA are detailed below.
1.
2.
3.
4.
To provide enough gain to overcome the noise contribution of
the next stages in the receiver path.
To add as little noise as possible.
To provide impedance to the RF antenna at the input and
impedance to the RF Filter at the output, with the minimum external
components. The overall gain should be insensitive to tolerances of
typical external components.
To provide enough linearity at the output.
Applying the Friis equation to a simple front-end consisting of a LNA
and a mixer, the noise factor of the whole front-end can be expressed as
follows (Equation 1.6).
The equation 1.6 shows the importance of the LNA performance in the
whole receiver chain. The LNA must provide enough gain to
overcome the noise of the next stages, adding as little noise as
possible. Once explained the importance of the LNA gain in the performance
of the whole front-end let us analyse the typical LNA configuration. Figure
1-6 shows the most extended differential topology in Bipolar and CMOS
technologies for narrow-band applications.
It consists in a cascode stage and a LC tank. This configuration is
expected to achieve near optimum noise performance while providing a
specific input and output impedance [Sha97].
12 Introduction
Let us consider now the simplified small signal equivalent circuit for the
CMOS LNA (Figure 1-7).
Where is the transconductance of the transistor is the
equivalent parallel inductance of the inductor L, is total capacitance due
to the capacitor C and the terminal capacitances of the transistor
is the total parallel resistance due to the output resistance of the cascode
stage and the equivalent parallel resistance of inductor L, and finally is
the source inductance of transistor
From inspection of the circuit of Figure 1-7 and not considering the
effect of we can obtain that the gain of the low noise amplifier at the
frequency of interest, the frequency of resonance, is determined by the
impedance of the LC tank and the transconductance of the input
transistor. The obtained gain is expressed by equation 1.7:
where
As we can see from equation 1.7 if we want to design a high gain LNA it
is necessary to implement a LC tank with a high value or what is the
same to dispose of an inductor with a high quality factor.
From another point of view, we could consider the case where we were
given a certain gain. If we dispose of high quality inductors we could
achieve this given value of gain with less power consumption, because the
will present a higher value and therefore the required value of will
14 Introduction
be lower. This statement is especially important when considering mobile
applications. Thus one of keys to progress in the design of low power LNAs
is the implementation of high quality inductors.
2.1.2 Voltage Controlled Oscillators (VCO)
VCOs are key building blocks in wireless transceivers and other
communication systems. As shown in Figure 1-2, the VCO is part of the
frequency synthesizer which generates the LO signal.
The key performance specifications are detailed below.
1.
2.
The power consumption.
The phase noise performance.
The toughest one to achieve is usually the phase noise spec. This is due
to the very narrow channel spacings used in cellular telecommunications
networks, such as GSM or DCS.
Figure 1-8 shows different VCO topologies depending on implemented
feedback [Zan98]. All this topologies have in common that they are LC-
tuned.
This is due to LC-tuned oscillators are expected to have much better
phase noise because they can use the bandpass characteristic of the LC-tank
to reduce the phase noise. Other types of oscillators, like ring oscillator,
suffer from switching effects that can introduce noise in the power supply,
and have therefore a worse phase noise than LC-tuned oscillators.
A strong effort has been done in order to explain and model the phase
noise performance of LC-tuned oscillators [Cran98, Cran95, Lee00]. For
instance, equation 1.9 mathematically expresses the phase noise performance
of the basic LC-tuned oscillator of Figure 1-9 operating in the linear region
[Cran95], where is associated with the series resistance of the capacitor,
with the series resistance of the inductor and with the output
resistance of the transconductor and the parallel resistances across C and L.
Where is the oscillation amplitude, the oscillation frequency
which is equal to the resonance frequency of the LC tank, A is a factor
equal to or larger than 1 that takes into account the active element
contribution to the phase noise, and finally is the effective resistance of
the tank, which is equal to:
16 Introduction
If we considerer equations 1.9 and 1.10, we can deduce two efficient
ways to improve the phase noise performance of the oscillator. The first one
is to enlarge the oscillation amplitude and thus making the signal
larger than the noise. And the second one is to reduce the effective resistance
of the tank.
Due to the fact that at RF frequencies inductors usually dominate the
quality of the tank [Her02], it is the passive component which
determines the phase noise performance of the VCO. Thus to design a VCO
with low phase noise it is necessary to dispose of high quality inductors.
As we have mentioned at the beginning of this section the other
important spec when designing VCOs is the power consumption, specially
if it is intended to be used in a mobile application.
The necessary power consumption to maintain the oscillation in the basic
LC-tuned oscillator is given by equation 1.11 [Cran95]:
If we analyse equation 1.11 we can deduce two ways to reduce the
necessary power consumption to maintain the oscillation. The first one is for
a given frequency of oscillation to reduce the capacitive part of the tank and
increase the inductive part while not decreasing the quality factor of the
tank. The second one is to decrease the effective resistance of the tank or
what is the same to increase the quality factor.
Therefore, like in the design of low power LNAs, one of the keys to
progress in the design of low power VCOs is the implementation of high
quality inductors.
In next sections we will see other applications of integrated inductors like
inductive degeneration for input and output matching purposes and RF
filtering.
2.2 Inductive degeneration for matching purposes
Many RF circuits need to match their input and/or their output ports to a
impedance value, in order to maximize the transferred power between
the different RF circuits or blocks. That is the reason why, as mentioned in
section 1.2.1.1, one of the most important requirements for the LNA is to
provide impedance to the RF antenna at the input and to the RF
Filter at the output. It forces in certain occasions to place matching networks
at the input and output ports of the circuit to fit its impedance to
There are many methods to match the input and output ports of RF
circuits. Probably the simplest one uses a matching network based on
resistances, so that the influence of the frequency on the impedance value is
minimized. A broadband matching is obtained with this method. But it has
an important drawback; it is the excess of generated noise which seriously
affects the yield of the circuit.
A method, widely used, that avoids the matching of the input and output
ports by means of resistances is the so called inductive degeneration
[Rud97]. This method is broadly used in the design of narrow band LNAs
and mixers, since it is the matching configuration which presents the best
noise performance. Figure 1-10 shows the case of a low noise amplifier
(LNA) which input port is matched using the inductive degeneration
configuration.
The provides the ground connection of the LNA. It plays two
important roles in the circuit:
1.
2.
As already mention, it allows conjugate matching of the input.
Linearizes the circuit.
Figure 1-11 shows the small signal equivalent circuit of the input of the
LNA of Figure 1-10.
18 Introduction
If we neglect the effect of and we can write the input impedance
as:
Thus, with proper choice of and we can achieve an input
impedance while the last two terms in equation 1.12
cancel.
For this kind of applications the inductors quality factor is not critical,
but lower quality factors will lead to a decrease in the noise performance of
this matching configuration.
2.3 RF Filters
As mentioned before, low power wireless communication systems are
becoming a dominant force in microelectronic systems. Ultra low power RF
design using Si based technologies will offer low cost components for small
portable wireless communication systems. Regardless of the specific
transceiver architecture, all RF functions require in the receiver path a
bandpass filter with minimum insertion loss to select the frequency band of
interest and in the transmitter path a low pass filter to pass the wanted signal
and eliminate or attenuate harmonics, mainly at the output stage of the
power amplifier.
A strong research effort has been done during recent years to fullfil, with
integrated passive RLC structures, the insertion loss in the pass-band and the
attenuation levels at the harmonics frequencies required by the strict
commercial specifications. The result has been very poor mainly due to the
low quality factor of the integrated inductors. Thus there is a strong
motivation for the implementation of high quality inductors.
Figure 1-12 shows the typical configuration for a low-pass filter
implemented with inductors and and capacitors and Some
implementations can be found in [Nguy90, Kim02].
3. THE CHALLENGE OF INTEGRATING HIGH
QUALITY INDUCTORS
In this section we are going to explain why the quality factor of the
integrated passive elements is critically determined by the characteristics of
the substrate and the metallization of the technology in which they are
implemented. The different loss mechanisms are shown in Figure 1-13 and
explained in the following paragraphs [Nik00].
It is necessary to mention that in chapter 4 of this book all these effects
are analyzed with greater depth. The objective of this section is only to
introduce the difficulty that entails the integration of RF passive elements in
conventional Si based low cost technologies.
20 Introduction
3.1 Metal losses
The passive elements generally make use of one or more metallization
layers. For example, an inductor is made up of one or more metal tracks in
parallel forming one or several concentric turns. Usually at lower
frequencies than the frequency of maximum quality, the quality of these
elements is determined by the conductivity of the metal tracks since the
current circulation produces ohmic losses [Agu00], That is the reason why
advanced RF processes, like the B7HF from Siemens, replace the AlSiCu
metallizations by copper metallizations, in order to increase the conductivity
of the metal tracks and reduce the series resistance of the integrated
inductors. Other RF processes, like the CMOS process from UMC,
implement a thick top metal layer with higher conductivity to reduce the
resistivity of the metal tracks and increase the quality factor of the integrated
inductors.
At high frequencies, the distribution of the current in the metal tracks
stops being uniform due to skin and proximity effects. In any metal track,
the alternating current tends to circulate around the way of minimum
impedance, but due to the magnetic field that penetrates in, generating
electric fields that move the current to the surface, it is accumulated in the
surface of the conductor. As the frequency increases, the effective area
around which the current circulates decreases increasing to the current
density and therefore losses by Joule effect [Burg96]. That is one of the
reasons why to implement high quality inductors at high frequency is a
difficult task.
Additionally, another effect exists that mainly limits the use of integrated
passive elements in applications in which it is needed to handle high power,
for example in power amplifiers. This effect is known as electromigration
and establishes the maximum current density that can handle the metal track
once it is fixed its width [AMS00].
3.2 Substrate losses
The substrate of the low cost silicon based technologies is one of the
greater sources of loss at high frequencies due to its high conductivity,
tipically between 2 and
The conductive nature of the substrate causes several loss mechanisms:
Electric coupling between the different metal layers and the
conductive substrate due to the existing dielectric among them.
Currents induced in the substrate due to the variable magnetic fields
that are originated by the different metal layers and that penetrate in
the substrate.
All these mechanisms reduce the quality factor of the integrated passives.
4. STRUCTURE OF THE BOOK
In this chapter we have seen how the performance of some RF building
blocks, like LNAs, VCOs or RF Filters, highly depend on the quality
factor of the integrated inductors used to implement them.
We have also introduced the difficulty that entails the integration of RF
passive elements in conventional Si based low cost technologies, due to
metal losses and substrate losses.
Chapter 2 will cover some general considerations like the physical
analysis of the integrated inductor, the existing electrical models to model
them model, transformer model or wide band modified model), or
some methods to improve the quality factor of an integrated inductor
(Broken guard rings, Substrate shielding, etc.).
Inductors test and characterization is covered in chapter 3. In the
inductor modelling, the accurate measurement of the device is very
important due to the fact that these are elements with very low resistance,
22 Introduction
where a single ohm makes a big difference in the quality factor. This is the
reason why the book also covers the design of the test fixture and the
measurement setup.
Chapter 4 will analyse the influence of the geometrical parameters in the
inductors performance and will establish the design guidelines for the
definition of the elements geometrical characteristics. It will also introduce
some new techniques to improve the quality factor.
Finally due to the fact that foundries only supply models for discrete
values of inductance, and that these inductances are not wide band modelled
there is a need of an inductors design flow in order to be able to obtain a
specific inductor value, optimized for a specific application or what is the
same a specific frequency range. The inductors design flow is covered in
chapter 5.
Chapter 2
GENERAL CONSIDERATIONS
In 1990 was reported one of the first Silicon Integrated Circuit with
integrated inductors. It was a passive filter [Nguy90] for radio-frequency
applications. Since then, many advances have been accomplished regarding
the integration of silicon passive components.
This chapter is a review of the state of the art of these devices when
integrated on Silicon technology. It will cover the different methods
available for inductor integration, as well as the latest techniques for
improving their quality. In addition, after studying in detail the physical
behavior of spiral inductors and the electrical models utilized to describe
their functionality in the frequency range of GHz, the most common
definitions of inductor quality will be presented.
We will end the chapter giving some rough notes about inductors on non-
conventional fabrication processes.
1. WAYS OF INTEGRATING AN INDUCTOR
This section describes the different configurations that an integrated
inductor can adopt for RF applications, considering both conventional and
non-conventional technologies. By non-conventional technologies it is
meant those technologies allowing stages of post-processing in which some
part of the wafer is eliminated by etching, or where the characteristics of the
different composition layers are modified.
There exist many solutions for the implementation of an inductor and the
designer should understand which configuration is the most appropriated for
his needs.
24 General considerations
1.1 Conventional fabrication processes
Today, the most common configuration used for the design of an
inductor is known as the geometric spiral. This configuration is simply a
spiral around a center and, depending on the permitted angle between the
metal tracks dictated by the fabrication technology used, the geometry of the
inductor could be squared, hexagonal, circular etc. Figure 2-1 shows four
inductors with spiral geometry and different number of edges.
As it is shown in the previous figure, an inductor can only be fabricated
with technologies having two or more metal layers since the inner
connection requires a metal layer different from the one used by the spiral.
In many instances, it is important to produce an inductor with symmetric
behavior, that is to say, its characteristics should be independent from which
input port the inductor is analyzed. Symmetry will occur when the centers of
the magnetic and electric fields of the inductor coincide, something that
does not happen in spiral geometries. This inconvenience is special relevant
when the inductor is used in differential circuits where the goal is to
minimize or suppress by circuit symmetry interferences of common mode
like temperature or voltage supply variations.
To avoid this problem when designing differential circuits, two inductors
rather than one are used, and they are implemented using a mirror
configuration like the one shown in figure 2-2 [Cran97].
Other possibility to solve the lack of symmetry is by implementing
centre-tapped inductors. There exist different methods to design this kind of
inductor geometries, but the most common is called balanced geometry
[Long97]. A micro-photography of this geometry is shown in figure 2-3. It
can be seen that the level of metallization changes every half turn of the
spiral. In this way, a fairly symmetric geometry is obtained, making viable
the use of these inductors on differential circuits.
Figure 2-4 [Kuhn95] shows another centre-tapped geometry very useful
for application where the differential circuit should be biased through an
inductor, like in a VCO with a NMOS configuration.
Other problem the designer could face is the available area for inductor
integration. This aspect gave rise to the concept of multilevel inductor. This
technique consists in implementing the same spiral in different metal layers,
and serially connecting them, as shown in figure 2-5 [Burg96].
With this structure, the mutual inductance among the metal layers of the
inductor increases. This in turn increments the inductance per unit of area,
permitting the implementation of inductors with large inductances within
areas smaller than the areas required by the corresponding mono-level
configurations. For example, in a CMOS process with five metal
layers, it is possible to produce inductors of 45 nH within an area of
[Zolf01].
Figure 2-6 shows a modification of the geometry shown in the previous
Figure, in order to maximize the inductance per unit area [Agu0l]. The way
the tracks are placed is such that it maximizes the coupling between tracks,
giving as a result an increase of the total inductance.
1.2 Non-conventional fabrication processes
The previous section has presented a review of the different geometries
currently used for the integration of an inductor with standard fabrication
technology. Depending on the requirements of the designer, there exist a
variety of solutions, for example for the case of a balanced circuit, or when
only a small area is available for the integration of the inductor, etc.
All the previously mentioned geometries can be implemented using
either conventional or non-conventional technologies; however, there exist a
group of geometries that can only be produced by the latter technologies. In
particular they are the solenoidal and toroidal structures.
It is important to emphasize that these are conventional configurations
used in lumped inductors. In the toroidal case, cores of iron-nickel in two
metallization levels are also integrated by using micro-mechanization, and
strips of copper metallization are then wrapped around them, as shown in
figure 2-7 a).
In the case of solenoids, either for the inclined or parallel conductor,
(Figure 2-7 b-c), the oxide thickness is increased up to levels that are not
viable with standard processes. The reason is that when using standard
processes, thickness larger than [Kim01] will create prohibitive
stresses between the Si and the due to their thermal expansion
coefficients
Also, as in the previous case, magnetic cores are added to coil around
them copper or aluminum metallizations. For example, there have been
reported solenoidal copper inductors with a quality of 16.7 at 2.4 GHz and
an inductance of 2.67 nH [Yoon99].
In the case where the designer has access to any of these processes, it is
possible to integrate inductors with the same geometries than lumped
inductors: solenoidal and toroidal, etc. However, all these processes are too
expensive, generally making its commercial application non-viable.
2. SPIRAL INDUCTORS ON SILICON BASED
TECHNOLOGIES
Once explained the different conventional and non-conventional
fabrication options for the integration of an inductor, this section describes in
detail the spiral inductors built on a silicon substrate.
The section begins analyzing the electromagnetic effects induced by
these inductor geometries, and reviewing some of the most up to date
electrical models used to characterize their behavior in the frequency range
of GHz. Then the quality factor of an inductor is defined, and the section
ends by analyzing some methods to improve the quality of a spiral inductor
for a given geometry.
2.1 Physical overview: Difficulty of integrating an
inductor
As already explained in the previous section, a spiral inductor is built by
a metal strip spiral shaped as a square, hexagon, etc. The spiral is built by
using one of the metal layers embedded in silicon oxide and placed at some
distance from the semiconductor substrate. As it is shown in Figure 2-8,
when a time-varying voltage is applied between the ends of the spiral, three
electrical and one magnetic field are generated.
In what follows the reasons for the generation of theses fields and their
effects on the behavior of the spiral are explained.
Magnetic field B(t): Any time-variant current flowing along a conductor
induces a magnetic field. Two effects are produced:
The self and mutual inductance coupling among the metal tracks
composing the inductor.
Current is induced in the substrate and metal tracks.
Electric field along the spiral, It is generated as a consequence of
the existing voltage difference between the two ends of the spiral. It
produces:
Ohmic losses in the spiral due to the resistivity of the metal tracks.
Electric field passing through the oxide between strips, It is
generated as a result of the existing voltage difference between adjacent
strips, and between those and the inner connection. It produces:
Capacitative coupling among the coils of the inductor.
Electric field passing through the oxide and the substrate It is
generated as a result of the existing voltage difference between the spiral
and the substrate. It produces:
Capacitative coupling between spiral and substrate,
Ohmic losses in the conductor substrate due to displacement
currents induced through the capacitative coupling between the
spiral and the substrate.
Next, each one of these effects is studied more in detail.
2.1.1 Inductance
The inductance of an inductor has two components, self and mutual
inductance.
2.1.1.1 Self inductance
According to Amperes law [Sanc01], an alternating current flowing
along a conductor induces a magnetic field. The self inductance of a
rectangular conductor was derived by Grover [Grov62] and is written as
Where denotes the conductor inductance in nH, and 1, w, and t
represents the length, width, and thickness of the conductor in cm,
respectively.
It is important to mention that expression (2.1) fails to be valid when the
width or the thickness dimensions double the length of the conductor.
However, this is not a restriction for inductor integration since the above
situation never occurs.
Figure 2-9 shows the self inductance for a rectangular conductor
computed by using expression (2.1). Length and width dimensions are varied
while maintaining fixed its thickness at This parameter has not been
changed, since in conventional fabrication process it remains fixed to
approximately the above value.
It can clearly be seen the influence that width has in the value of self
inductance. This is due to the fact that inductance is mainly determined by
the outer magnetic flux generated by the conductor [Yue96]. Consequently,
when the width diminishes the self inductance increases.
2.1.1.2 Mutual inductance
Mutual inductance, between two circuits, 1 and 2, can be defined as
the ratio between the flux generated by circuit 1 crossing to circuit 2
and the current that flows in circuit 1 It is determined by equation (2.2).
In case of two parallel conductors the mutual inductance is defined as
Where M is the inductance in nH, 1 is the length of the conductor in cm
and Q is a coefficient that depends on the geometry, and it is given by
[Ling98].
GMD is the geometric average of the distance between the areas of the
two conductors. The GMD between two areas can be obtained by
partitioning the areas in differential intervals elements and computing the
geometric average of the distance between these elements like it is shown in
Figure 2-10.
The geometric average of the distance between these two areas is
computed in the following way:
Where n and m denote the number of differential elements within areas
A' and A, respectively. Dij' is the distance from element i in area A, to
element j in area A'. For the case of two conductors with rectangular shape,
the GMD is defined as [Moha99]
Where w and d are the width and distance, center to center, between the
conductors in cm, respectively. Figure 2-11 and Figure 2-12 show the
mutual inductance between two rectangular conductors of length as
a function of the distance center to center and separation, respectively. These
curves are displayed for three different widths.
As it can be observed, the mutual inductance hardly varies with the
width of the strip when the distance center to center remains fixed. This
implies that the value of mutual inductance of coils, having the same
distances between spirals barely change when the width of the strips is
modified.
2.1.1.3 Total inductance
Total inductance of a conductor in a system is given by the sum of three
terms. The self inductance plus the sum of the magnetic couplings of those
conductors (represented by mutual inductances) that contribute to increase
the self magnetic flux, minus the sum of magnetic couplings of the
remaining conductors that reduce the self magnetic flux of the original
conductor. In other words
Based on the study of Grover, equation (2.1), Greenhouse [Gree74]
developed an algorithm to compute the inductance of a planar rectangular
spiral. The method determines the total inductance of a rectangular spiral as
the addition of the self inductance contributions of each segment forming the
spiral, plus the sum of the positive and negative mutual inductances of all
segment pair combinations.
Mutual inductance between two segments depends on their angle of
intersection, length and separation. Two orthogonal metal tracks have no
mutual inductance since their magnetic fluxes are not linked together. In
parallel metal tracks the sign of the mutual inductance is set by the direction
of the current. This last consideration is shown in Figure 2-13 [Soye98].
Later, other algorithms suitable for calculating the inductance of
inductors with different geometries (hexagonal, etc) had appeared in the
literature. However, due to their computational complexity they are more
appropriated to be used with simulation tools than for analytic calculations.
After having analyzed the inductance of an integrated spiral inductor, it
is proceed to study the second most important characteristic of these
elements: resistance.
2.1.2 Resistance
When a DC current flows through a conductor, the current distribution is
uniform over its entirely surface. A conductor has a value of resistance, since
it presents a resistivity to any current carried by the conductor. This value is
given by
Where is the resistivity, L the length and A the conductor area. As
frequency increases, the resistance is no longer constant due to the fact that
distribution of the current is not uniform across the conductor cross section.
In case of a spiral inductor the dependence of the resistance with frequency
not only depends on the conductor itself (skin effect) but also on the
influence of neighborhood strips (proximity effects).
2.1.2.1 Skin effect
The skin effect in a conductor accounts for the alteration of the current
density distribution from the magnetic field generated by the current itself.
As it is shown in Figure 2-14, when a magnetic field generated by a
current in a conductor crosses its cross-section induces a force over the
current itself. This force is perpendicular to the magnetic field and to the
direction of the current flow. This effect is known as Lorenzs force
[Lore01].
As it can be observed, the current is pushed toward the outer surface of
the conductor. The higher the frequency is, the higher the resistance of the
conductor will be, since the current is restricted to a small part of its total
cross-sectional area.
The influence of the skin effect over the resistance of a conductor is
evaluated by means of the skin depth. This parameter is defined as the
equivalent thickness of a hollow conductor having the same resistance at the
frequency of interest. As an example, for a cylindrical wire the skin depth is
defined as [Ling98]
Where is the magnetic permeability of the material, the conductivity
and the angular frequency of interest. The resistivity of this conductor is
then defined as
Where is the skin depth in cm, is the conductivity in is
the magnetic permeability of the conductor in and f is the frequency of
the AC current [Stey01].
2.1.2.2 Proximity effects
Proximity effects in a conductor are a consequence of the influence of an
external time-varying magnetic field over the conductor. In this case, an
induced current is generated regardless whether or no there is a current flow
through the conductor. In case there is an alternating current, the skin effect
and the proximity effect will add together, changing the current distribution
and increasing the resistance of the conductor [Sanc01].
The induced currents in the tracks of a spiral inductor have a negative
side effect, especially in the inner coils turns since it is in the center of the
spiral where the magnetic field reaches its maximum intensity. In a fully
winding coil (the coil turns reach the center) a large portion of the magnetic
field passes through the inner coil turns, inducing in these turns a strong
current density, and therefore increasing their resistivity. When adding this
effect to the small inductance contribution from the inner coil turns with
respect to the outer coil turns due to the difference in length, one conclude
that it is better to fabricate hollow inductors [Stey01].
This section began by studying the variations of the resistance of a
conductor due to the magnetic field induced by an alternating current carried
by the conductor itself, without considering any external influence. Latter it
has been shown that when a wire is within a system of conductors, like for
example a spiral, the variation of the resistance versus frequency it is not
only due to skin effects but also to proximity effects.
2.1.3 Parasitic effects in the substrate
When an inductor is integrated on a Silicon based technology, some
undesirable induced effects show up. The reason being that the metallic
layers are separated from the semiconductor substrate by a layer of silicon
oxide. These effects can be classified in two types, magnetically induced and
electrically induced.
2.1.3.1 Magnetically induced parasitic effects in the substrate
One of the fundamental properties of an inductor is that generates a
magnetic field. This alternating field penetrates into the conductive substrate
and induces a voltage difference, which in turn generates a current. This
phenomenon diminishes the energy in the coil, decreasing at the same time
the quality of the inductor.
Figure 2-15 schematically shows this effect for a cross section cut of an
inductor integrated on Silicon technology. It is important to mention that
some studies indicate that the radius of the spiral approximately gives the
depth of penetration of the magnetic field into the substrate [Yue96].
Inductance is other parameter affected by the induced currents in the
substrate. These currents flow in the opposite direction than the current
carried by the coil, resulting in a reduction of the magnitude of the total
magnetic field. Therefore, the value of the inductance will decrease, since
the inductance is defined as the ratio between the magnetic flux and the
current in the spiral [Cran97].
2.1.3.2 Electrically induced parasitic effects in the substrate
Other parasitic effect that shows up in Silicon integrated inductors is the
capacitative coupling between the inductor and the substrate. The reader can
understand this effect by realizing that a capacitor is just two conductive
plates (metallic layer form by the inductor and semiconductor substrate)
separated by a dielectric (Silicon oxide), as shown in Figure 2-16. This has a
negative effect since depending on the capacity and the frequency, a portion
of the inductor energy will be stored in this capacitor. It could even happen
that the inductor starts behaving like a capacitor rather than as an inductor.
The value of the frequency where this occurs is called resonance frequency
of the inductor
In addition, ohmic losses are produced since there are displacement
currents induced in the substrate. This is illustrated in Figure 2-17.
2.1.4 Parasitic capacitance between metal turns
When a voltage is applied to the ends of a coil, it creates a voltage
distribution along its metal tracks. Recall on the other hand, that the silicon
oxide isolates the metal tracks of a spiral inductor. Therefore, due to the
structure metal/oxide/metal appears a parasitic capacitor between the metal
tracks. On the other hand, there is a voltage difference between the plates so
energy will be accumulated in the capacitor. This capacitance is called
parasitic capacitance between metal turns. Figure 2-18 schematically shows
this effect.
This capacitance includes both the adjacent capacitance between tracks
on the same metallic layer and the vertical capacitance between tracks
located on different layers.
As it can deducted from this section the common property of all low
price fabrication technologies this is the low substrate resistivity
propitiates the occurrences of undesired effects. Clearly this is a great
handicap when designing inductors in this kind of technologies due to the
poor quality.
2.2 Spiral inductor electrical models
This section provides a review of integrated inductors electrical models
use to describe their behavior in the range of GHz under the constraint of
low cost fabrication technologies. There exist several models with the
model [Nguy92] being the most well known the transformer model
[Matt0l] and the wideband model [Pino02]. It is important to mention
that the parameters of the electrical circuits representing these models are
not only empirical but they also have a physical meaning. In what follow
these models are explained in detail.
2.2.1 model
Due to its simplicity the model is the most common model utilized
today by the designers. It is simple its parameters are easy to adjust to
empirical data and they have a clear physical meaning. As a drawback it is
a narrow band model that is to say it is only valid for modeling the
behavior of an inductor in a small range of frequencies. For this reason it is
normally used only to model the spiral at the frequency of interest [Pino02].
As it can be seen from Figure 2-19 the model uses ideal components
such as resistors inductors and capacitors. These elements present a clear
correlation with the behavior of an integrated inductor in a Silicon based
fabrication technology.
accounts for both the capacitance among the strips and between the
strips and the coil inner connection. Its value is usually negligible
represents the inductor resistance it accounts for the ohmic losses due
to the metal track resistance induced effects in the metallic conductor
and magnetic induced currents in the substrate.
models the inductance of the coil.
represents the parasitic capacitance between the metal of the spiral
and the substrate.
accounts for the ohmic losses in the substrate produced by the
displacement currents induced in the substrate.
models the capacitative effects of the substrate due to its
semiconductor characteristics.
As it has been said before the drawback of the Model is that many of
its components like resistance inductance substrate parasites etc. depend
on frequency. This makes the model only valid for a small range of
frequencies to 1 GHz) or when losses in the substrate are
negligible [Pino02].
In 1996 Patrick Yue [Yue96] developed expressions for the computation
of each parameter in the model as a function of the inductor geometric
values and fabrication process parameters. These expressions are given by:
Where w is the width and t the depth of the strip 1 the length of the
spiral the skin depth at the considered frequency and the resistivity of
the metal.
The inductance is computed by using the H.M. Greenhouse algorithm
explained in section 2.1.1.3.
Where n is the number of crossings between the coil and the central
lower connection w is the width of the strips is the oxide dielectric
constant is the oxide depth between the spiral tracks and its central
interconnection.
Where l is the length of the metallic spiral w is the width of the strip
is the depth of the oxide and is the oxide dielectric constant.
Where are the substrate capacitance and conductance per unit
area respectively. These two constants are empirically computed.
It is important to emphasize that the above expressions allow a
qualitative rather than a quantitative analysis of the inductor since there are
limitations in the validity of some of the equations. For example the
resistance is computed based only on the DC resistance of the metal and
on the skin effect without considering the losses resulting by the proximity
effects of the metal and substrate. Other drawback is that the proposed
expression for the computation of the resistance is more appropriate for
circular conductors rather than rectangular.
The model just described is only valid when none of the two ports of
the inductor is connected to AC ground. When this is not the case the
resulting model is simpler and is called the one-port model. Figure 2-20
shows this model.
The meaning of the parameters of the one port model is identical to its
counterpart the two-port model.
2.2.2 Transformer model
The transformer model arises as an evolution of the model. As shown
in Figure 2-21 its main advantage is that permits independently characterize
the effect of the induced magnetic field in the substrate.
The parameters of this model are identical to the corresponding
parameters in the two-port model. However the model has three
additional parameters describing the effect of the magnetic induced current
in the substrate
M represents the magnetic coupling between the substrate and the spiral.
A percentage of the magnetic field generated by the spiral penetrates into
the substrate inducing currents.
accounts for the magnetic field generated by the substrate. This field is
a consequence of the induced currents within the substrate and confined
in a close loop. This magnetic field opposes to the original field.
represents the substrate ohmic losses due to the currents being
induced in the substrate.
2.2.3 Wideband model
In [Pino02] it is derived a modification of the model. Its major
advantage from other models is that permits the characterization of an
inductor over a wider range of frequencies. This is achieved by improving
the characterization of the losses arising by the capacitative coupling
between tracks in Figure 2-22).
In the GHz frequency range the common procedure followed by a
designer to characterize an inductor at particular frequency is to adjust the
parameters of the model so that its S parameters match the corresponding S
measured parameters. Based on the large bandwidth of the wideband
model in [Pino02] are given expressions directly relating the values of the
parameters of the model in Figure 2-22 to the measured S parameters. These
expressions are:
Where denotes the admittance parameters obtained from the S
parameters and the angular frequency. In the above expressions the sub-
index Low and High indicates that the corresponding expressions should be
evaluated with the Y parameters measured at a frequency range below or
above the 1-2 GHz interval respectively.
It should be clear by now that all the previous models are based on
modifications of the model. Even though these models have better
characteristics than the model it is the simplicity of the latter that makes
the the most frequently used model.
2.3 Quality factor definition
The quality factor of an inductor (Q) gives a measure of the goodness of
an inductor. As presented in chapter 1 it critically determines the
performance of basic RF blocks like LNAs or VCOs. There exist three
definitions for the quality factor: and They are defined
next.
2.3.1 definition
The quality factor is defined as the ratio between the maximal
energy stored by the inductor and its average power dissipated on a duty
cycle. [Fink79]. That is
Where is the angular frequency the maximal magnetic energy
stored in the device and the average dissipated power. Unfortunately it
is very difficult to accurately measure these values.
2.3.2 definition
In RF applications the characterization of an inductor is made by its S
parameters. By using the fact that the admittance parameters are easily
obtained from the S parameters is defined as [Ashb96]
being the admittance in port 1 of the inductor when port 2 is
grounded. Based on the simplify model shown in Figure 2-23 the
definition of can be extended to
Where and denote the average electric and magnetic energy
stored in the system and the average dissipated power. Since in general
is one order of magnitude higher than and represent the
energy stored in the inductor and in the capacitance respectively.
Looking at expression 2.25 depends on the difference between the
average magnetic and electric stored energies rather than in the total energy
like in the previous definition.
When the average magnetic stored energy is much higher than the
electric energy is close in value to However for integrated
inductors on silicon based technologies where is high often happens that
a large percentage of the energy is stored in this capacitance making to
deviate substantially from
2.3.3 definition
There exist other ways of defining the quality factor depending on the
meaning one wants to give to the concept of goodness of an inductor. In
occasions the definition of the quality factor should depend on the system
where the spiral is part of. For example in an matching network the quality
factor should be related to losses whereas in pass band filters should be
related to -3dB bandwidths [Desp69]. In oscillators the quality factor is
related to their phase stability and phase noise.
Summarizing the parameters of interest when defining a quality factor of
an inductor are: losses bandwidths in resonance circuits and frequency
stability in oscillators [Kenn98].
Data like bandwidths or stability factors are defined at the resonance
frequency and therefore they could be derived from the parameters
measured at the resonance frequency of the inductor. However this has little
practical interest since the inductors are rarely used at its resonance
frequency.
A method to obtain the values of bandwidth and stability factor at
frequencies other than at resonance is to modify the measured parameter
by placing in parallel to a capacitor and numerically computing the new
value. In this way the data is computed at the resonance frequency of the
resulting RLC circuit. By varying the value of the capacitor the stability
factor and bandwidth of the inductor can be obtained at frequencies different
than at resonance.
From the 3 dB bandwidth of an RLC circuit [Desp69] and the
frequency stability factor of an oscillator with a simple RLC tunable filter
the quality factor is given by
Where is the inductor resonance frequency and the stability factor.
Notice that when a capacitor is added to the model of an inductor the
resulting RLC circuit is not any more a basic RLC filter however equations
2.27 and 2.28 [Kenn98] defining the quality factor are still valid.
In short there are four ways of defining the quality factor of an inductor
for RF applications and depending on the definition used the
corresponding values can vary substantially. In [Kenn98] a comparative
study of the quality factor computed by the four methods is presented. Two
different inductors were used in the study. It is shown that when the spirals
are working at frequencies where the stored magnetic energy is much larger
than the electric energy the quality factors derived by the above four
methods are nearly similar. The large deviations occur when the stored
magnetic energy is comparable or even smaller than the electric energy. In
this case the quality factor defined by and is much larger than when
defined by and
Due its simplicity has been chosen in this book as the quality factor
of an inductor since is directly obtained from its S parameters.
2.4 Different attempts to predict the performance
Since the announcement in 1990 of a successful integration of a spiral
using a Silicon fabrication technology [Nguy90] the need of predicting the
behavior of these devices without requiring their fabrication and
measurement has grown.
Clearly it is very convenient for any designer to have an algorithm or
subroutine that permits the estimation of the characteristics of a spiral
whatever its fabrication technology is.
Although it is relatively easy to compute the value of the inductance once
the geometry of the spiral is given the estimation of its losses is a much
harder problem. This is a consequence of the large number of parasitic
effects occurring at the same time.
In what follows some of the techniques utilized by the designers to
characterize the behaviour of an inductor are described.
2.4.1 Field electromagnetic simulators
To solve the problem some designers have used algorithms based on
electromagnetic simulators in 2 and 2.5 dimensions. However in spite of the
high computational cost and large computing time of the algorithms these
methods are only valid for a small number of spirals [Raza0l]. In addition
these simulation methods require the knowledge of fabrication parameters
like resistivity of the substrate etc. which in many instances are confidential
data.
2.4.2 ASITIC
In 1998 [Nikn98] Berkeley developed a free distribution software for the
simulation of integrated spiral inductors. This program called ASITIC
characterizes the behavior of an inductor given its geometry and fabrication
parameters parameters often not available to the general public.
It is important to mention that this simulation tool is useful as a first
approximation step in the design of an inductor due to some limitations in
the implementation of the algorithm. Among the limitations it is especially
notorious the lack of account for the magnetic induced current effects in the
substrate and the proximity effects between metallic layers of the inductor.
On the other hand its main advantage lies on its low computational cost and
the accuracy of the results despite the limitations.
2.4.3 Method based in the model parameter definition
In 1996 Stanford [Yue96] developed a method for the prediction of a
spiral inductor based on a model and on the quality factor. As it was
already explained in section 2.3.2 the quality factor of a spiral is defined as
In this case the quality factor has been defined as a function of energy
peaks instead of average values like it was done in equation 2.25.
Figure 2-24 shows the energetic model equivalent to the one port
model when a sinusoidal voltage at frequency and amplitude is applied
at its ends.
Where and represent the total inductance the
conductor losses the substrate losses and the total capacitance respectively.
Notice that and represent the combine effects of and
From this model one obtains that
Where denote the maximum electrical and magnetic
energies stored in the inductor respectively. represents the energy loss
in the inductor. Substituting these definitions into the above equation the
quality factor of an inductor is given by
Where the first term is associated to both the stored magnetic energy and
the losses in the metal tracks of the inductor. The second term is the
substrate loss factor representing the dissipated energy in the silicon
substrate.
The last term is the self- resonance factor describing the reduction in Q
when the stored electrical energy nears its peak (the electrical energy stored
in the parasitic capacitance begins to predominate over the magnetic energy
stored in the inductor).
This way of predicting the quality factor of a spiral inductor has the
drawback that requires the knowledge all model parameters as a function
of frequency. It assumes that these values are obtained by the expressions
given in section 2.2.1. However as discussed there these equations are only
valid for specific cases and frequencies. In other words the use of equation
2.30 is not advised except when all frequency dependent parameters are
known something that is only possible if the spiral has been previously
measured and its model derived for all frequencies.
This section has introduced some of most well known methods used
currently by designers for the characterization of spiral inductors. Although
these techniques avoid the need of inductor fabrication and subsequent
measurements they are only recommendable as a starting point in any
design.
2.5 Quality factor improvement methods
As already explained in this chapter the quality of an inductor is
determined by its geometry and fabrication process. Therefore there exist
two methods to improve the quality factor of an inductor the optimization of
its geometry (this will be explained in detail in chapter 4) and for a fixed
geometry alter the surroundings of the inductor.
Some of these techniques are reviewed in this section. Both conventional
and non-conventional technologies are considered. The reason for including
the latter group is to allow the reader to acquire a deeper understanding of
the parasitic effects occurring in inductors.
2.5.1 Broken guard ring
The broken guard ring technique consists in placing biased P+ or N+
diffusion regions surrounding the coil. The diffusion ring is connected to
ground. The effect accomplished by the ring is to provide a low-impedance
path to ground for the induced currents in the substrate.
Figure 2-25 shows a plot of a spiral surrounded by a broken guard ring.
The reason for the ring discontinuities is to avoid the generation of induced
currents in the ring.
Some studies have shown that the broken guard ring enhances the
quality factor [Burg97]. This effect can be explained by analyzing the one-
port model of an inductor with a broken guard ring.
Where denotes the ring impedance. The energy loss in the substrate
due to the capacitative coupling between the substrate and the spiral can be
expressed as:
Where V is the input voltage between the port and the ground Z the
impedance of the branch representing the coupling between the substrate and
the spiral and R the real part of the above impedance. In these
computations one can consider negligible the value of In this case the
ohmic losses due to displacement currents induced in the substrate can be
expressed as
Where R is the parallel arrangement of and Notice that the
resistance of the substrate is made smaller than since the value of is
much lower than the value of As R decreases so does the loss of energy
Clearly the smaller the losses in the substrate are the larger the quality
factor of the inductor will be.
The problem that arises with this method is to know at what distance
from the spiral the ring has to be placed. If placed too near it could affect
parameters of the spiral like the inductance if placed too far away its
contribution to the quality factor could be negligible [Ling98].
2.5.2 Biased N-well beneath the inductor
One of the reasons for the reduction of the Q factor is the capacitive
coupling between spiral and substrate. This value is mainly given by
the spiral geometry and fabrication process. However by placing a biased
N-well beneath the inductor as shown in Figure 2-27 the value of this
capacity can be changed without modifying the inductor geometry.
When a positive DC voltage is applied between the contacts of an N-well
and a P substrate a depletion region in the PN junction is formed. This
depletion region can be model as an additional capacitance in series
with the existing parasitic capacitance between substrate and metal.
Therefore the effective total capacitance between the inductor and substrate
is reduced and so it is the electrical energy stored in this capacitance.
Consequently this technique improves the quality factor of an inductor by
increasing the frequency where its Q factor begins to degrade.
Looking at the electrical model shown in Figure 2-28 from a point of
view of energy storage one can observe the influence that capacitance
will have in the behavior of the whole inductor.
As in the previous section energy loss in the substrate due to the
capacitive coupling between the spiral and substrate can be expressed by
equation 2.31. In this case the ohmic losses due to the displacement
currents induced in the substrate can be written as
As explained placing a N-well underneath the inductor creates a
capacity in series with Therefore the total capacity to the substrate C
will be
Since C is smaller than the ohmic losses in the substrate are reduced
and consequently the Q factor will improve.
2.5.3 Substrate shielding
Another solution to reduce the ohmic losses in the substrate due to
electrical coupling is to insert between the spiral and the substrate a solid
conductive ground shield to provide a short to ground [Alan98].
In terms of the parameters of the equivalent circuit the insertion of a
substrate shielding is similar to substitute the components and in
the one-port model of Figure 2-20 by y This is shown in
Figure 2-29.
Where:
represents the resistance of the conductor ground shield
since the ground shield is made of much more conductive layer than the
substrate.
denotes the capacitance between the shielding and the substrate.
due to the fact that the conductor ground shield is closer to the
spiral than to the substrate.
Based on these parameters a set of conditions can be found determining
when the use of a conductor ground shield is a convenient solution.
The ohmic losses without a substrate shielding are given by
The ohmic losses with a substrate shielding are given by
The substrate shielding will be useful when
One of the serious drawbacks with this approach is that solid ground
shield also disturbs the inductors magnetic field. According to the Lenzs
law loop currents will be induced in solid ground shield by the magnetic
field of the spiral inductor. This result in a reduction of the effective
magnetic energy and in the appearance of ohmic looses in the solid ground
shield.
To avoid the appearance of induced currents the ground shield is
patterned with slots. The slots act as an open circuit to cut off the path of the
induced loop current. Figure 2-30 illustrates an example of a patterned
ground shield underneath a squared spiral.
The slots should be sufficiently narrow so that the electric field cannot
leak through the patterned ground shield into the substrate. The ground strips
are merged together around the outer edges of the spiral and the merged area
of the shield is strapped with the top layer metal to provide a low-impedance
path to ground avoiding in this way unwanted loop currents.
The thickness of the shield is other critical design parameter since as the
magnetic field passes through the patterned ground shield its intensity is
weakened [Whee42]. To avoid this attenuation the shield must be
significantly thinner than the skin depth at the frequency of interest. This
sets the thickness of the shield that should be fabricated. In general a better
choice for the ground shield is to use polysilicon due to its higher resistivity
rather than aluminum.
This implies that using a typical metal layer for the shield may result in
reduction of the magnetic field intensity. From the results in [Yue98] the
patterned ground shield should be of polysilicon the width of the ground
strips should be approximately and the slots between strips should be
approximately
2.5.4 Non conventional fabrication processes
This section describes techniques to enhance the quality factor of an
inductor built with non-conventional fabrication processes. Non
conventional processes open a window of possibilities for improving the
quality of a spiral which are radically different from the approaches used in
conventional fabrication [Grov00] Furthermore they can diminish or even
eliminate the losses due to the magnetic induced currents something
impossible with a standard technology. One of the fundamental limitations
in integrated inductors is the parasitic current induced in the substrate by
magnetic and electric fields. One possible solution to this problem is to
fabricate the spiral further away from the substrate with thicker oxide. In this
way the parasitic effects are reduced and consequently the quality of the
inductor improved [Alan98]. Another possibility is to increase the resistivity
of the substrate making more difficult the appearance of induced currents
and therefore reducing the substrate losses.
Using this method of fabrication inductors of 5.7 nH of 29 at
7GHz and a frequency of resonance higher than 20 GHz have been reported
[Kim0l].
The limit case of fabricating an inductor with a large thickness of oxide
and with a substrate highly resistive is equivalent to eliminate the substrate
underneath the spiral. Using this technique inductors have been reported
with inductances of 100 nH and resonance frequencies higher than 3 GHz
[Chan98]. Figure 2-31 shows one of such inductors. Finally it is important to
mention that even though the quality of an inductor improves it is not at all
that clear the commercial viability of this technique due to its high
fabrication cost.
Chapter 3
INDUCTORS TEST AND CHARACTERIZATION
Before the advent of RF coplanar probes, finding the RF behavior of an
integrated circuit was a complicated process. First the wafers were diced and
the individual dies containing the desired integrated circuits were mounted
into a test fixture. This fixturing process also involved the attachment of the
die to a PCB and the wire-bond to the bond pads (Figure 3-1). Only then the
RF performance of the integrated circuits could be known.
A key point was the discrimination between the dies and the fixtures
responses. This was a difficult issue to overcome [Bes01]. Furthermore, the
fixturing process was very time consuming, making it impractical for high
volume applications. Because of these difficulties on wafer characterization
was developed.
Some of the on-wafer devices to characterize are active, like transistors
or diodes, while others are passive, like resistors, inductors or capacitors. On
this chapter we will concentrate on the on-wafer characterization of
integrated inductors.
64 Inductors test and characterization
The electrical models of the devices are obtained from the RF
measurements made on-wafer. Since circuits are designed with these
models, it is important that the on-wafer characterization be accurate.
The goal of this chapter is to present the basic elements to test and
characterize integrated inductors. By choosing the correct elements the
results obtained will be reliable, repeatable and accurate.
Figure 3-2 shows the basic elements involved in the characterization of
an integrated inductor. These are the test equipment, the probe station and
the RF probes.
The test equipment used to perform the on-wafer measurements is the
same as the equipment used to characterize discrete devices or circuits. For
the characterization of RF circuits, we normally use:
Vector Network analyzers (VNA)
Noise Figure Meters
Spectrum analyzers (SA)
etc.
A key point is the way we establish an electrical connection between the
device under test (DUT) and the test equipment. The RF probes perform the
physical contact to the DUT. Finally, in order to control the position of the
probes, these are mounted in a probe station. The station enables a high
accuracy alignment as well as a tight control of the pressure applied to the
probes.
Section 3.1 analyzes the above issues, and the most suitable test
equipment to accurately characterize an integrated inductor at RF
frequencies.
The measuring accuracy and repeatability of measurements performed is
discussed in section 3.2. This section also introduces the types of errors and
the calibration process used to characterize the different integrated inductors.
Section 3.3 analyzes which is the best measuring configuration in order
to characterize the integrated inductor: the 1-port or the 2-port
configuration.
Another point to consider is the design of the interface between the
probes and the DUT. This interface is called the test fixture (Figure 3-3). It
should be designed with few and easily identifiable parasitics. These
conditions will facilitate an easier and more accurate correction of the
measurements. The way to design the test fixture and how to extract the
parasitics that have been introduced is presented in sections 3.4 and 3.5
respectively.
Finally, section 3.6 presents the methodology to obtain the model of
the integrated inductor from the RF measurements.
1. ON WAFER MEASURING EQUIPMENT
This section establishes a short guide in order to choose the most suitable
test equipment to accurately characterize integrated inductors in the GHz
range.
1.1 Vector Network Analyzer
The first decision that we should make is the selection of the measuring
method and this implies the selection of the test equipment. The criterion to
select among the measuring methods mainly depends on:
The frequency of operation of the DUT.
The expected impedance of the DUT.
The required accuracy.
Figure 3-4 shows the range of application of the measuring methods
(bridge method, I-V method, etc.), according to the frequency of operation
and the expected impedance of the DUT [Amo00].
As shown in figure 3-4, at low frequencies the usual methods are the
Bridge method and the I-V method. These methods are very accurate,
achieving accuracy values in the range of 0.5% of error when measuring
impedances from a few up to several Nevertheless these two
methods are limited to frequencies of operation of up to 100 MHz. Thus the
characterization of an integrated inductor for the GSM band if we use these
methods will be highly inaccurate. At higher frequencies the usual methods
are the RF I-V and the reflection (network) method. While the first is more
accurate than the second, the former is limited to frequencies of operation of
up to 2 or 3 GHz. If we want to perform a wide-band characterization of an
integrated inductor up to 10 GHz the only valid method is the reflection
method.
The equipment that performs measurements based on the reflection
method is the Vector Network Analyzer (VNA). Figure 3-5 shows a
simplified block diagram of a vector network analyzer.
The VNA uses a RF source to generate the reference signal. Using a
switch, the signal is applied to either port 1 or port 2 of the DUT. Often
internal attenuators are available, such that the measuring accuracy and
reliability can be improved for a large range of device characteristics.
The incident RF signal is detected by a receiver after downconversion to
an intermediate frequency (IF) and stored for reference. Through directional
couplers, power splitters, etc. both the reflected signal from the current port
of the DUT as well as the transmitted signal through the DUT are detected
and stored. From the three stored signals, the two S-paramcters relating to
the current port are calculated. From the S-parameter and after some
mathematical computations the impedance seen by each port can be also
calculated.
1.2 Probes
After the selection of the test equipment, we consider now some
important features of the RF probes. The probes can be viewed as an adapter
from the traditional coax interface used with RF cables to the contact pads
placed on the chip. For RF measurements, the most common probe is the air
coplanar probe (ACP). As the name indicates, the ACPs are implemented as
a coplanar waveguide in air.
Figure 3-6 shows the typical construction for an air coplanar probe. The
tips are usually made of two kinds of materials. They arc made of flexible
beryllium-cooper (BeCu) or Tungsten (W). The tips made of BeCu are
optimal for probing gold pads on fragile GaAs wafers, since they present
lower contact resistance and keep them from digging into the dies probe
pads. When probing aluminium pads on silicon wafers the BeCu based
probes are not the best ones, since due to their flexible behaviour they cannot
break the oxide film on the pads, resulting on a poor electrical contact. The
tungsten (W) probes are firmer, being able to break through the oxide film to
make a good electrical contact. Usually to break through the oxide a big
over-travel of the probes is needed, it causes the probes to wear out sooner.
Furthermore, the pads must be large in order to accommodate skating of the
probes, and larger pads add bigger parasitics to the measurement. In spite of
these drawbacks the tungsten probes are the common choice when probing
on aluminium pads. A general rule of thumb could be; use BeCu probes
when probing on gold pads and tungsten probes when probing on aluminium
pads.
Let us now consider the probe configuration: balanced or unbalanced.
The most popular coplanar probe configuration to measure integrated
inductors is the ground signal ground (G-S-G) configuration. Two ground
tips shield the signal tip in between. Thus its principal advantage is in tightly
controlling the fields around the signal tip. The electric fields emanating
from the signal (S) tip terminate on the ground (G) tips while the magnetic
fields between S and G cancel.
The principal advantage of an unbalanced probe (ground-signal or signal-
ground) is in reducing the overall die size. Since an inductor is usually a
pad-limited component, if we only use two pads (G-S), it results in a slightly
smaller die, thus for the same wafer area we can increase the number of dies.
The drawback is that it results in a less shielding of the signal (S) tip,
originating crosstalk problems. A second ground tip on the other side of the
signal tip ensures a better wave propagation along the line as compared to
the G-S propagation (Figure 3-7).
Thus if there is not any area constrain the most common choice is the
balanced configuration since it provides more accurate measurements.
After selection of the probe tip material and the probe configuration, let
us now consider some probe related issues in order to perform accurate
measurements, like planarization of the probe, amount of skate, cleaning of
the probes, etc.
Planarization
When a coplanar probe wears out, the tips are often no longer in the same
plane. Figure 3-8 shows the case of a Ground-Signal-Ground (G-S-G) probe
that has weared out. As we can see the reference plane at the probe tips is no
longer a straight line. This poor reference plane definition introduces
uncertainty to the DUT measurement. Consider the case where two
resistors are placed in parallel. The equivalent resistance should be
(That is the case of the standard for on-wafer calibration). If one of
the ground tips does not touch the pad, the measured load resistance will be
near Thus before to proceed with the on-wafer measurement of any
DUT we should always check the planarity of the probes. Otherwise the
performed measurements may present large errors.
The common way to check the probe tip planarity is by means of a
contact substrate [War03]. The contact substrate is simply a metallized field.
When the probes are lowered onto this field, the probe tips leave scratches in
the metal (Figure 3-9). The scratch depth indicates when the probe tips are
not in the same plane.
Skating
When a coplanar probe touches down on the pad, the tip arrives normal
to the wafer surface (Figure 3-10). Yet because the probes body is at an
angle to the wafer, lowering it more causes the tip to move across the pad.
This phenomenon is known as skating. Some skating is always necessary
since the signal and ground pad metal may not be deposited with the same
thickness on all wafers, causing in some cases connectivity problems.
When designing the die, is always useful to place some alignment marks
near the dies pads to align the coplanar probe for a consistent amount of
over-travel (Figure 3.10).
Skating has both a mechanical and an electrical impact on the
measurement [War03]. Mechanically, skating leaves marks on the die pad,
visible under a microscope. These marks tell when the die has been probed,
useful in post-probe inspection. A disadvantage is that the scrubbing action
of the skating scrapes some metal of the pads. Over time, it accumulates on
the probe tips, requiring periodic cleaning. Electrically, skating resembles
the open stub under the probe (Figure 3-11). This is important when
performing the VNA calibration or measurements after calibration. In order
to establish an accurate reference plane, which should be the same during
calibration and during measurement of the DUT; it is important that the
values of the probe tip parasitics remain constant. If the amount of applied
skate is different from calibration to DUT measurement the values of the
probe tip parasitics will not remain constant introducing uncertainty in the
measurements mainly at high frequencies.
Cleaning
After extended use, the probes accumulate rubbish such as lifted probes
pads or metal strings around the pads. Probes can be cleaned with either
compressed air or isopropyl alcohol applied with a swab [War03]. The
wiping should be done in a direction away form the probe tips, otherwise the
tips may be damaged.
1.3 Probe station
After the selection of the probes, the next decision that we should make
is the selection of the proper probe station.
This selection depends on the measuring requirements. If there is a need
for a large number of repeated measurements, like in statistical
characterization or matching verification, it would be quite desirable to have
a semi-automatic probe station in order to reduce the measuring time and
increase the reliability and repeatability of the measurements.
In terms of performance, automatic probe stations provide the highest
degree of probing repeatability. This applies to the contact reliability as well
as the accuracy of the calibration [Kol00], Unfortunately this kind of
automatic probe stations are very expensive and are usually required by IC
manufacturers only. Therefore manual stations are the most common choice
and are widely used in research labs and small companies.
The basic purposes of the probe station are:
Stable mounting of the die under test.
Accurate positioning in x, y and z axis of the probes.
Adjustment of the planarity of the probes.
Visiual interface to the very small measuring environment
(microscope).
Depending on the measuring requirements, the probe station may also
have some additional purposes:
Shielding of the measuring environment by using a microchamber.
Thermal control of the measuring environment.
Maintaining stability and avoiding undesired vibrations by using a
anti-vibration table.
Figure 3-12 shows the standard setup of a manual probe station. The
chuck is the part of the station that is in charge of the stable mounting of the
die under test. The x, y and z micrometers enable the high accuracy
alignment as well as a tight control of the pressure applied to the probes. The
planarity micrometer enables the adjustment of the planarity of the probes.
Finally the microscope establishes the visual interface to the small device
under test.
In general, we could affirm that very accurate measurements can be
performed with most commercially available probe stations.
1.4 Commercial calibration kits
To calibrate the VNA directly at the probe tip interface, there are
available on-wafer calibration kits. The commercial version of these kits is
known as Impedance Standard Substrate (ISS). These ISSs are available in a
number of configurations depending on the used probe configuration (G-S-
G, G-S, S-G-S, ...) and the desired form of calibration (SOLT, LRM, ...).
They are usually implemented on an alumina substrate with low loss factor
and high dielectric constant. Metallizations are implemented with gold for
low contact resistance and oxidation.
Figure 3-13 shows a general purpose ISS. It contains the SOLT
calibration standards: trimmed (+/-0.3%) resistors, shorts and thru lines.
The open is usually implemented by lifting the probes high into the air.
The ISS also contains several components which can be used to evaluate
the accuracy of the performed calibration, like attenuators, capacitors,
inductors, etc.
2. MEASURING ACCURACY AND
REPEATABILITY
2.1 Different types of measuring errors
Once we have selected the appropriate test equipment for on-wafer
measurement, in this section we describe the basic sources of measurement
error.
The ultimate goal of any measurement is validity. A measurement is
valid only if it is accurate and repeatable. We understand for a repeatable
measurement when it yields the same result on repeated trials. In practice
this term relates to the degree of consistency found in repeated
measurements. We understand for an accurate measurement when it actually
measures the desired parameter and not a distorted form of it.
There are three basic error sources that impact the validity of any
measurement. These error sources are known as systematic, random and drift
errors.
Systematic errors are usually due to imperfections in the VNA and the
test setup. They are repeatable and therefore predictable, and are assumed to
be time invariant. Systematic errors are characterized during the calibration
process and mathematically removed during measurements.
Random errors are unpredictable since they vary with time in a random
fashion. Therefore, they cannot be removed by calibration. The main
contributors to random error are the instrument noise, like source phase
noise, sampler noise, etc.
Finally, drift errors are due to the test equipment or test-system
performance changing after a calibration has been performed. Drift is
primarily caused by temperature variation, degradation of the electrical
contacts or increased electromagnetic interference from outside
environment. It can be removed by further calibrations.
In the following sections we will deeply analyze the random and
systematic errors. We will also define the conditions for an accurate and
repeatable measurement.
2.2 Random errors
As already mentioned, random errors are unpredictable since they vary
with time in a random fashion. They are inherent to every measuring system
and are assumed to have zero mean and do therefore not influence the
accuracy of the system, but merely the repeatability. Thus, one way to
improve repeatability is by measuring the same parameter several times and
doing the average of the obtained results. This way, the random effects are
averaged and the error variance is reduced by a factor corresponding to the
number of measurements. It should be noted that this assumption for the
improvement of repeatability is only valid if random errors from
measurement to measurement are uncorrelated. To ensure uncorrelated
random errors, it is important to re-do as much as possible of the
measurement from time to time. In practice, the complete re-calibration of
the system is highly undesirable, due to it is very time consuming. But
fortunately, the effects particular to the DUT interface are usually the most
important, and therefore the system do not need to be re-calibrated every
time. It is enough to re-probe and re-measure the device a number of times.
2.3 Systematic errors
As mentioned before, in section 2.1, the systematic errors are repeatable
and therefore predictable, and are assumed to be time invariant. In a Vector
Network Analyzer (VNA) based system (Figure 3-14), like we normally use
for the characterization of integrated inductors, we can divide the treatment
of systematic errors into three major parts:
1.
2.
3.
The VNA itself.
The cables and connectors that connect the VNA with the probes.
The probes.
2.3.1 Systematic errors due to VNA
From the receiver part of the VNA, the contribution to systematic errors
depends on the applied input power levels and originates from the dynamic
range limitation and the nonlinearities and tracking errors in the front-end
and processing stages of the VNA. For instance if the applied input power
level is too high, it may move the front-end mixer or IF amplifiers into
compression or if it is too low, the noise floor of the VNA may degrade the
measuring accuracy. In the IQ demodulator, errors may happen due to
quadrature errors.
These errors are difficult to correct and must be minimized by choosing
the appropriate measuring power levels and the selection of high
performance measuring equipment.
But the major systematic errors associated with the VNA are (Figure 3-
15):
1.
2.
3.
The errors related to signal leakage. These errors are directivity and
crosstalk.
The errors related to signal reflections. These errors are load and
source match.
The errors related to frequency response of the receivers. These errors
are called reflection and transmission tracking errors.
The full two port error model includes all six of these terms for the
forward direction and the same six (with different data) in the reverse
direction, for a total of twelve error terms. This is why we often refer to two
port calibration as twelve term error correction.
2.3.2 Cables and connectors
When performing the on wafer measurement of an integrated inductor,
usually the calibration and the DUT measurement is conducted without re-
assembling any connector, all connections are done on the die. So the errors
due to connectors can be minimized by calibration since any connector
interface is reassembled between calibration and DUT measurement.
The cables may introduce error, not minimized by calibration, if they are
bended or flexed between calibration and DUT measurement since they
change their characteristics. This problem is less pronounced for on wafer
measurements since we are able to move the die rather than the probes
avoiding any extra cable flex.
2.3.3 Probes
The RF probes introduce systematic errors similar to those described by
the VNA. There are several issues:
1.
2.
3.
Insertion loss, corresponding to reflection and transmission
measurements.
Reflections, corresponding to source and load match.
Crosstalk since they radiate to its environment.
These errors can be minimized by proper calibration of the test setup.
2.4 Calibration
In the previous section we have identified the origin of the different
systematic errors. The sum of these errors could lead to unacceptable levels
of measuring inaccuracy. Thus we need to compensate them. The
compensation procedure is known as calibration.
It starts by defining the 12 term error model to represent the measuring
setup. These terms will take into account the errors introduced by directivity
crosstalk source and load mismatch, reflection
tracking and transmission tracking for both forward (F) and
reverse (R) ports (Figure 3-16).
Usually crosstalk error term is omitted since it is difficult to estimate due
to it is usually low and noise floor of the test equipment disturbs direct
measurement.
From the error model, without crosstalk terms, we can obtain expressions
that relate the measured S-parameters to DUT parameters through the error
terms (Equation 3.1-4).
Calibration consists then, in replacing the DUT with well known
calibration standards and then use measurements to solve for the error
parameters. In the case of on wafer measurements, the well known
calibration standards are the ones contained on the impedance standard
substrate (ISS).
There are many calibration approaches TRL, LRM, LRRM, but the most
extended one is the SOLT (Short-Open-Load-Thru) approach and for that
reason it is the one that will be addressed in this section.
2.4.1 SOLT Calibration
The SOLT calibration procedure goes through a well defined number of
steps. These steps are:
1.
2.
3.
4.
Measuring the short standard.
Measuring the open standard.
Measuring the load standard.
Measuring the thru standard.
Usually the isolation measurement is omitted for the reasons already
mentioned.
Measuring the short standard
The short standard is implemented as a line of Au metallization on the
ISS. For the Cascade ISS, the short standard is a metal track (Figure
3-17).
In terms of self-resistance it is usually considered as an ideal short. To
properly measure the short standard it is very important that the probe has
been planarized and the overtravel has been accurately adjusted using the
alignment marks, otherwise parasitics of the standard may change from the
well known ones and have an impact on the measuring accuracy. The
calibration procedure assumes that both probes are sufficiently isolated
during measurement of the short, thus it is important to guarantee that both
ports are properly isolated. It is usually enough to lift the other probe in air
and remove it a few centimeters.
It is interesting to mention that thanks to the measurement of the short
standard the reference plane, after calibration, will take into account the
contact resistance between the probe and the standard.
Measuring the open standard
The measurement of the open standard is performed by lifting the probes
into the air. Usually by lifting the probes in air it should be enough.
As for the short standard, it is important to guarantee that both ports are
sufficiently isolated.
In order to check if we are properly measuring open and short standards
it is useful to compare both reflection responses. Both responses in
magnitude should be quite similar since both standards reflect all the
incident power, but a difference close to 180 should be observed in the
phase.
Measuring the load standard
The load standard is implemented with high-precision resistors that are
laser trimmed (Figure 3-18). The resistive value remains very constant
versus frequency and as for the short standard, planarity and overtravel are
critical issues.
Isolation between both ports is also required, like in the measurement of
the open and short standards.
Like in the open standard case, we can check that we are properly
measuring the load standard by comparing its reflection response with the
one of the open or short standard. The reflection response (S11) of the load
standard should be at least l0dB lower, over the complete measuring range,
than the reflection response of the open or short standard (Figure 3-19).
If the reflection response of the load standard is not 10dB lower than the
short or open response, it points out that:
The contact probe is not good enough. The origin of this bad contact
can be the bad state of the probe tips, a not good planarization of the
probe, etc.
The return loss of the measuring system is too poor to facilitate good
accuracy calibration, due to bad state of the cables or connectors.
Measuring the thru standard
The thru standard is implemented as a coplanar waveguide thru
connection (Figure 3-20).
The thru standard is more sensitive to the probe alignment than the other
standards (short open and load). The alignment should be very accurate
including the distance between the probes
To check the uncalibrated response of the thru standard the same already
mentioned issues as for the load standard apply.
2.5 Repeatability and accuracy
Once the system is calibrated we should check repeatability and
accuracy of the system. A good check of the repeatability is to re-measure
the calibration standards with the correction enabled. This way we can check
that the probe contact during calibration has been consistent. Typical values
are [Ko100]:
Open
Where is the VNA input impedance usually and is the
probe parasitic capacitance when open.
Short
Where is the probe parasitic inductance when the probe tips are
shorted on the ISS short standard.
Load
Where is the probe parasitic inductance when measuring the ISS
load standard. The values for and are usually supplied by the
manufacturer and are dependent of the probe pitch.
Thru
Where is the delay time of the thru standard usually 1ps.
Once we have check the calibration repeatability the next step is to
check calibration accuracy. To check calibration accuracy we can measure
some of the test-resistors test-inductors test-attenuators ... present on the
ISS. Notice that these components are not trimmed to a very high accuracy
so detailed consideration of the reflection response is not appropriate but we
should observe in every case the typical response. For example when
measuring a test-resistor we should observe a small dot near the desired
value on the real axis of the Smith chart.
MEASURING CONFIGURATION: 1-PORT
VERSUS 2-PORT CONFIGURATION
3.
In the last sections we have analyzed the different available test-
equipment to measure integrated inductors and the errors that they may
introduce. In this section we will study which is the most suitable setup for
measuring an integrated inductor using a VNA when it is to be modelled
with the most often used lumped equivalent circuit the model.
As shown in Figure 3-21 there are three possible setups for measuring an
inductor with a vector network analyzer (VNA):
One-port measurement.
Two-port measurement with the device placed in series with the ports.
Two-port measurement with the device placed in parallel with the
ports.
where and are the RF ports of the VNA and and are the
RF-ports characteristic impedance usually
In order to study which is the most suitable configuration the
expressions of the scattering parameters (S parameters) have been obtained
for the three different setups. First of all for a generic impedance (section
3.1) and afterwards for the case when the generic impedance is
substituted by the inductor model (section 3.2).
After that a sensitivity analysis has been applied to the obtained
expressions in order to study the sensitivity of the measuring setup to
variations in frequency and variations in the model parameters (section 3.3).
If the sensitivity of the measurement of one of the parameters of the
model is very low the measurement method is obviously inappropriate to
determine this parameter. Taking into account the analysis for all the
parameters the most suitable setup for measuring integrated inductors may
be selected.
3.1 General Case
The aim of this section is to introduce the way in which the expressions
of the scattering parameters should be calculated when the equivalent circuit
of the impedance to be measured is known. For that purpose the expressions
of the scattering parameters of a generic two-port network (Figure 3-22) arc
presented. Then these expressions are applied to the measurement of an
impedance with the three different measurement setups described before.
The scattering parameters of a two-port network have the following
expressions [Ko100]:
Here and are calculated with the generator shorted to ground
and vice versa with the calculation of and and are the
impedances seen from port 1 and port 2 respectively. Also and
represent the reference impedance of each port.
Next these expressions are applied to the measurement of an impedance
with the three different measurement setups described before. For these
calculations and are assumed to be equal to (usual case).
3.1.1 Two-Port measurement with the device placed in series
The measurements setup after applying the conditions for the calculation
of and where is shown in Figure 3-23. The calculation of
and is done in the same way.
Applying the expressions of and shown in equation 3.9 for this
setup the expressions of and for this setup are obtained:
3.1.2 Two-Port measurement with the device placed in parallel
The measurement setup after applying the conditions for the calculation
of and is shown in Figure 3-24.
and for this setup have the following expressions:
3.1.3 One-Port measurement
The measurement setup after applying the conditions for the calculation
of is shown in Figure 3-25.
Applying the expression of shown in equation 3.9 to this setup the
expression of for this setup is obtained:
3.2 Inductor model case
The model Figure 3-26 is the electric circuit most often used by the
electronic designers to describe the performance of integrated inductors for
RF applications in a small frequency range typically 0.2 GHz around a
central frequency of a few GHz (1 to 3 GHz). So it is important to measure
the inductor with the setup that minimizes the uncertainty of the parameters.
In this section the expressions of the S parameters are calculated in the same
way as in section 3.1 but introducing the model into each measuring
configuration.
3.2.1 Two-Port measurement with the model placed in series
In this case the measurement setup is shown in Figure 3-27. The S
parameters have been obtained as indicated previously.
has the following expression:
has the expression shown by equation 3.16 in next page.
3.2.2 Two-Port measurement with the model placed in parallel
In the same way the S parameters are calculated as above. The
measurement scheme is shown in Figure 3-28.
9
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The value of is:
The value of is shown in equation 3.18.
3.2.3 One-Port measurement
In this case since there is only one port just one S parameter exists.
Thus the calculations are simplified. The proposed measurement scheme is
described in Figure 3-29.
The expression of is obtained:
3.3 Sensitivity analysis
In this section a sensitivity is conducted to illustrate how the expressions
of the S parameters for each of the setups respond when the parameters of
the inductor model and frequency are varied. This will determine which
is the best measurement setup the aim of this section.
A sensitivity analysis cannot be made without numerical values. So it is
necessary to carry out some measurements of an integrated inductor with a
typical value at a representative RF frequency range. For that purpose an
inductor has been fabricated and modeled with the model at around
1.65GHz. The technology used was a standard CMOS three metal
layer. It was measured in series with the two-port vector network analyzer.
At the time of research it was not necessary to have the exact values but
only a realistic order of magnitude to carry out the sensitivity analysis. The
geometrical characteristics of the inductor and the parameters of the inductor
model at 1.65GHz are shown in table 3-1 and table 3-2.
For the study the values of table 3-2 were introduced in the expressions
of the S parameters of the three measurement setups. The simulations were
achieved by varying different parameters and reading the deviation of the S
parameters. Two kinds of parameters were varied:
The frequency.
The model parameters.
When the frequency was varied (between 1.5GHz and 1.8GHz) the
related model parameter was fixed at a certain value which could be:
The medium value (shown in table 3-2).
+30% (referred to the medium value).
-30% (referred to the medium value).
On the other hand when the model parameter was varied (between
30% and +30% of its medium value) a fixed frequency was used (1.5GHz
1.65GHz or 1.8GHz). These two processes were repeated for each
measurement method.
The results of these simulations are given in tables 3-3 and 3-4.
Note that the parameters of the model varied were
and The other parameters such as and were not modified
due to the symmetry of the model.
From the analysis of tables 3-3 and 3-4 we can draw the three following
conclusions:
The parameter is not completely characterized when the one-port
measurement method is employed due to the fact that this setup is not
sensitive to variations in the value of
The or parameters are not completely characterized when the
two-port measurement setup with the device placed in parallel is used.
This is due to the fact that this setup is not sensitive to variations in
their values.
The sensitivity of the measurement of an integrated inductor with the
one-port measurement setup is always very close or lower than the
sensitivity of the measurement of an inductor with the two-port
configuration with the device placed in parallel and at the same time
the sensitivity of the latter (two-port measurement setup with the
device placed in parallel) is lower than the sensitivity of the two-port
measurement with the device placed in series.
So to accurately characterize an integrated inductor the best
measurement setup is the two-port configuration with the inductor under test
placed in series between the two ports of the vector network analyzer.
4. TEST FIXTURE DESIGN
In the previous sections of this chapter we have presented the different
pieces of available test equipment for the measurement of integrated
inductors. We have also analyzed which is the most suitable measurement
setup to accurately characterize them. The next step now is the design of
the test fixture.
As we mentioned at the beginning of this chapter the test fixture is an
interface to connect the device under test (DUT) and the probes. The lateral
probe dimensions are usually many times larger than the surface dimensions
of the DUT thus it is quite difficult to design a test fixture with negligible
effect on the DUT measurement. To illustrate this fact figure 3-30 shows the
measurement of a 4.8nH integrated inductor with and without the effect of
the test fixture. The integrated inductor was fabricated in a two metal layer
BiCMOS process.
As shown by figure 3-30 the effect of the test fixture is not negligible.
Thus the proper design of the test fixture is an important matter if we want to
characterize an integrated inductor with accuracy.
There are well-known techniques to subtract the effect of the test fixture
from the measurement of the DUT. These techniques are called de-
embedding and will be presented in section 5 of this chapter. But in spite of
the existence of these techniques it is very important to reduce as much as
possible all the parasitics due to the test-fixture. There are two convincing
arguments [Ko100]:
It is important that as much as possible of the transmitted and reflected
power is caused by the DUT and not by the parasitics of the test-
fixture. This results in a higher dynamic range of the DUT
measurement.
Tolerances on parasitics are usually relative so when parasitics are
reduced so are the overall measuring tolerances. This is an important
matter since parasitics are often estimated using separate test
structures.
1.
2.
Thus the first thing that we should do is to identify which are the critical
process related parameters that determine the test fixture parasitics. These
parameters are mainly related to substrate and metallizations. As an
example table 3-5 shows some general values for substrate and
metallization parameters of some fabrication technologies [Ko100].
Once we have identified the critical process parameters we should then
design the test fixture in such a way that they have minimum impact.
In the following sections all these parameters are analyzed in detail and
after that some general guidelines are presented for the design of low
parasitic test fixtures.
4.1 Substrate related issues
The underlying substrate of any low cost technology process has a great
impact on device and circuit performance. Its characteristics are also
important for on-wafer device characterization. In the following sections we
consider which are the most noticeable effects that can be ascribed to the
substrate and which are the different techniques to mitigate their impact on
the device measurement.
We should consider two noticeable effects (Figure 3-31). The first one is
the coupling effect between the tips of the same probe (interterminal
coupling) or in other words the coupling between the signal pad and the
ground pads of the same probe. The second one is the coupling effect
between two different probes (interport coupling) or in other words the
coupling between the signal pad of one port and the signal pad of the other
port.
4.1.1 Interterminal coupling
Figure 3-32 shows the cross sectional view of two pads: signal (S) and
ground (G). It also shows a general model for the coupling mechanism
between these two pads (interterminal coupling). As shown the signal
couples to ground in two different ways:
Through the dielectric insulator layer
Through the dielectric insulator layer and the conductive substrate
and
This is the general coupling model for most of the silicon based
technologies like Bipolar SiGe or CMOS. There are other technologies like
GaAs that introduce a ground plane under the substrate and consequently a
new signal path to ground (Figure 3-32). This one will not be considered in
this book since it is limited to low cost silicon based technologies which do
not implement a ground plane under the substrate.
The coupling through the dielectric insulator layer is usually quite small;
therefore the interterminal coupling is determined by the coupling through
the dielectric insulator layer and the conductive substrate or in other words
by the equivalent input capacitance of the signal path For silicon
based technologies this input capacitance can be as high as 300 or 400fF
depending on the oxide layers and the pad design rules. Such values may
have detrimental effects on most device measurements if no compensation
techniques are applied. And even then if the input capacitance is associated
with large tolerances we may make significant errors when subtracting its
average equivalent value due to tolerances alone.
To illustrate this issue let us consider the case in which we measure the
input capacitance of a generic device with value To measure the device
we mount it for measurement with a GSG probe pad configuration (Figure 3-
33). The equivalent parasitic capacitance of the input probe pads is so
the total measurement yields an error of
Let us assume that we are able to estimate the value of from a
special test-structure located near the structure under test. However, due to
the process tolerances, we might have a discrepancy between the parasitic
capacitance of the test-structure and the one of the structure that contains de
DUT. Let us consider now that we have a relative tolerance on the parasitic
capacitance of T. Thus, even if we subtract the estimated value for we
may make an error of farads. The relative tolerance of the parasitic
capacitance depends on the process technology, and usually, as designers,
we are not able to change it, thus the only way that we have to improve the
accuracy of our measurement is to design a test-fixture that reduces the
parasitic input capacitance as much as possible. This means having to
reduce the parasitic capacitance of the signal pad, so that the coupling of the
signal to substrate is minimized. And having to increase the parasitic
capacitance of the ground pad, so that any signal in the substrate will be
coupled to ground and will not have any effect in the incoming signal.
Next some ways of reducing the parasitic capacitance of the signal pad
are explained.
To reduce the parasitic capacitance of the input pads the signal pad
dimension should be as small as possible. Its minimum size is determined by
the lateral dimension of the probe tips and the necessary skate to guarantee a
reliable contact between the probe tip and the pad. Typically for on-wafer
measurement the lateral dimension of the signal pad is 60 ~
Shape
Pad dimension
The parasitic capacitance is directly proportional to the occupied pad
area. Usually the signal pad is implemented with a square piece of metal
(Figure 3-34). This type of shape is not efficient from the point of view of
occupied contact area to occupied pad area. There are other shapes like
hexagonal or octagonal that are more efficient, keeping the same contact
area but occupying a smaller pad area (Figure 3-34).
Implementation
Typically, it is recommended to implement the signal pad with the union
of three of four layers in parallel in order to guarantee that the pad has
enough mechanical consistency when bonding the chip or skating the probe
tips over the pad. Figure 3-35 shows the recommended implementation of a
signal pad for a CMOS process with 3 metal layers.
As shown the pad is implemented by the union of all the available metal
layers plus the two poly layers. On the one hand, these type of
implementations present very good mechanical consistency, but on the other
hand, they also present a big parasitic input capacitance. In the test fixture
design, we should reach a compromise between mechanical consistency and
input capacitance. A proved solution that guarantees enough mechanical
consistency and drastically reduces the parasitic capacitance is the
implementation of the signal pad with only the top metal layer or at least the
two top metal layers.
It is also useful, in order to reduce the parasitic capacitance, to introduce
an N-well under the pad. This way an extra capacitance appears between the
N-well and the substrate, which is in series with the pad capacitance, thus
the overall input capacitance is reduced.
Finally, mention that all these rules do not apply to the ground pads
where, as explained before, a big parasitic capacitance is desired. These pads
are usually implemented with the union of all the available layers.
4.1.2 Interport coupling
The interport coupling is also an important matter, since to measure a
DUT with accuracy we need that the transmitted power from one port to the
other, when the DUT is present, must be at least 20dB higher than the
transmitted power when the DUT is not present [Ko100].
The interport coupling will mainly depend on four factors:
Distance between ports of the test-fixture.
Parasitic input capacitance of the signal pads.
Characteristics of the substrate (substrate resistivity, ...).
Substrate grounding.
Figure 3-36 shows the interport coupling of different test-fixtures with
different distances between ports and different types of substrate.
As shown by Figure 3-36 low resistivity substrates, like Epi/Si from
digital CMOS processes, present higher interport coupling than high
resistivity substrates, like Bulk/Si from BiCMOS processes. Usually, as
designers, we are not allowed to change process characteristics, thus we will
not be able to reduce the interport coupling by modifying the substrate
resistivity. We may only reduce the interport coupling by increasing the
distance between ports, or by reducing the parasitic input capacitance of the
signal pads or by heavily grounding the substrate.
The way to reduce the parasitic input capacitance was explained in the
preceding section. Thus in the following sections we will only analyze the
influence of the distance between ports and the grounding of the substrate.
Figure 3-37 shows the cross sectional view of two test-fixtures with and
without ground contacts.
Substrate grounding
As we can see on Figure 3-37, with a heavily grounded substrate any
signal coupled from the signal pad to substrate will go to ground through a
low resistivity path. This way the signal will not reach the other port and the
interport coupling is drastically reduced.
Figure 3-38 shows the interport coupling measurement of two test-
fixtures with and without ground contacts. The test-fixtures are implemented
using a BiCMOS process with two metal layers. The distance
between the pads of the two ports is
As shown in Figure 3-38 an improvement of 30dB can be achieved with
the proper grounding of the substrate. Thus wherever is possible grounding
of the substrate is highly recommended, but before applying it, it should be
checked that the ground contacts introduced do not modify the normal
behaviour of the DUT. In that case, it should be applied with caution.
Distance between pads
The minimum distance between the pads of the two ports is determined
by the size of the DUT. But in order to minimize the interport coupling
through the air, when using Air Coplanar Probes, it should be at
least [Lord99]. The optimal distance between the pads will depend on the
type of substrate. For high resistivity substrates should be enough,
but for low resistivity substrates a longer distance is needed. A compromise
between test-fixture size and interport coupling should be achieved for low
resistivity substrates.
Figure 3-39 shows the interport coupling measurement of different test-
fixtures, where the pads are placed at different distances:
and The test-fixtures are implemented in a BiCMOS process
with two metal layers.
As shown by Figure 3-39, as we increase the distance between pads the
interport coupling is lower, but from a certain distance the main coupling
mechanisms are different than those through the substrate and therefore the
interport coupling do not improve.
For medium or low resistivity substrates, heavily grounded, a distance of
should be enough to minimize the effect of the interport coupling.
4.2 Metallization related issues
As mentioned before, the type of metallization plays an important role
for the measurement reliability and accuracy of a DUT. A good
metallization should:
Provide a stable and consistent contact between the probe and the test-
fixture.
Provide low-loss interconnections to guarantee low parasitic effects
and a good common ground.
To achieve these goals we should consider, the following issues.
4.2.1 Pad material
The pad material contributes significantly to contact effects. Current IC
processes usually employ gold, aluminium and copper, all of which have
very different characteristics.
Gold
It is very soft and does not react to air. Due to these effects, a contact
with gold does not easily degrade. A disadvantage of its softness, is that it is
fragile and is broken easily under large applied skate or when hard probes
are used. This type of pad material is typical of GaAs technologies.
Aluminium
It is a very hard material, which protects itself by developing a very hard
and thin aluminium oxide layer immediately after being exposed to air. A
large contact pressure is needed to break the oxide layer and establish a good
contact. It is widely used on Silicon based technologies.
Copper
It presents a lower resistivity than aluminium, but it reacts to a large
degree with its environment, thus it usually needs of complementary layers
like TiN. Its probing characteristics are similar to those of aluminium.
4.2.2 Probe tip material
As mentioned in section 3.1 of this chapter, there are two probe tip
materials available: BeCu and Tungsten. Tungsten probes are tougher and
can penetrate oxide layers more easily. On the other hand, they are stiffer,
and more susceptible to microscopic variations than BeCu probes. Tungsten
probes are normally used over aluminium pads and BeCu over gold pads.
4.2.3 Probe alignment
To guarantee a consistent metal-metal spot area, it is essential that the
probe touches the pad with a consistent pressure from touch-down to touch-
down. As explained in section 3.1 of this chapter, the pressure can be
adjusted by applying a proper amount of over travel and skate. The parasitic
contact resistance between the probe tip and the pad will depend on the
applied skate. Figure 3-40 shows the measured mean and standard deviation
of the DC contact resistance for different applied skate. As we can see in
Figure 3-40, to guarantee a reliable contact a minimum skate of
should be applied. That is the case when using a Tungsten probe over an
aluminium pad. When using a BeCu or Tungsten probe over a gold pad a
lower skate of should be enough to guarantee a stable contact
[Lord99].
4.2.4 Setup stability
It is important to guarantee that movement and vibrations in the lab do
not degrade the probe-pad transition. Thus it is important, when possible, to
use an anti-vibration table.
4.2.5 Tolerances
In the case where the series parasitics can be made negligible, we do not
need to be concerned with the tolerances. However, for many sensitive
measurements, even low resistivity metallization cannot fulfil this
requirement and we must guarantee that the tolerance of the series parasitic
is low enough to be ignored.
4.2.6 Wear of the probes and the pads
After long-time use of the same probe or pad, the contact properties may
degrade. Figure 3-41 shows how the contact resistance between the probe tip
and the pad degrades after reprobing over the same pad several times. As we
can see after 20 touchdowns over the same pad, the pad wears and the
contact resistance increases.
4.3 General Guidelines
To mitigate the substrate effects, we should follow the following
guidelines:
Effort should be made to make coupling as small as possible for the test-
fixture; both for the interterminal and for the interport coupling. For doing
this we can apply the following techniques:
Minimization of the path to common ground. An aggressive grounding
of the substrate will lead to improved coupling mechanisms, as shown
by Figure 3-38. Caution should be taken when applying this technique
in order to not change the behaviour of the device under test.
Distance between the input and output ports. Increasing the separation
between the ports, the forward coupling is reduced as shown by Figure
3-39. However, with highly dopped substrates the gain is limited and
the required interconnections needed for small devices would still give
coupling. For heavily grounded test-fixtures a separation of
should be enough.
Reduction of the parasitic pad capacitance Pad techniques
include:
Use of small pads.
Use of hexagonal or octagonal shapes, instead of square
shapes for the pads.
Employment of the top metal layers for the signal pads and all
the layers for the ground pads.
Use of n-well or metal shield [Ko100] underneath the pads
(Figure 3-42).
Compare the coupling effects of the test-fixture with the isolation of
the device under test. For the cases where a 20dB margin is not
observed, one should compensate for the coupling effects and use
statistical techniques.
To mitigate the contact effects of aluminium technology, we should:
Reduce vibrations by use of anti-vibration table, relieving cable stress,
and by improving cable flexibility.
Use BeCu probes instead of Tungsten probes for less stable measuring
environments. For stable environments, tungsten probes give longer
probe lifetime and the repeatability appears to be approximately the
same for large skate measurements.
Apply proper probing techniques for better reliability, including
skate and re-probing of the structure every 20 minutes for
critical measurements. Note that a pad starts to wear after 20
touchdowns more o less. It is also convenient to use alignment marks
for high consistency.
5. DE-EMBEDDING TECHNIQUES
Due to the difficulty to build probe tips small enough to directly contact
on the DUT, a dedicated on-wafer test fixture becomes necessary. In the last
section of this chapter we have analyzed how to design the test fixture in
order to reduce its effect on the measurement of the DUT. Now in this
section, we will present a methodology to subtract from the measurement of
the DUT the remaining effects due to the test fixture. This technique is call
de-embedding.
A de-embedding method consists of three elements:
A model for the test fixture where the DUT is mounted.
A mathematical procedure for removing the parasitic effects of the test
fixture.
A method for estimating the parasitics and thus extracting the model
of the test fixture. This method includes a set of in-fixture standards
and a mathematical procedure.
For optimal results, the de-embedding method should be tailored
specifically to the given test-fixture and to the characteristics for the device
under test. However, there exists a lot of widely used general procedures
which exhibit different degree of accuracy [Van01], [Nie01], [Koo91],
[Ko100].
5.1 Test-fixture model
The basic assumption in any de-embedding method is that, the RF test
fixture and the corresponding in-fixture standards can be represented
schematically by scattered parameters circuits. These are parasitic
admittances and and parasitic impedances
and (Figure 3-43).
The admittances and represent the interterminal coupling of
each port of the test fixture, and the admittance the interport coupling.
The admittances and stand for the coupling between the signal tracks
and the ground leads of the test fixture. If the test fixture, to characterize an
integrated inductor, is properly designed, the distance between the signal
tracks and the ground leads is of several microns (Figure 3-44), thus the
coupling between the signal and ground tracks is negligible. Therefore
admittances and can be eliminated from the model.
The impedances and represent the contact resistance between the
probe tip and the pad of the test fixture. represents the series impedance
of the ground leads. If the test fixture is heavily grounded or metal shielded
the impedance is usually negligible. Thus if we apply one of these
techniques to the design of the test fixture, the impedance can be omitted
in the test fixture model. Finally impedances and represent the
interconnection between the pad and the DUT. These impedances, if the test
fixture is properly designed, should be considered as part of the DUT, since
they are also necessary in the final circuit, when we connect the inductor to
the rest of the LNA, VCO, etc.
5.2 In-fixture standards
In the previous section we have modelled the test fixture by scattered
parameters circuits, like admittances and impedances, in this section we
present which are the necessary in-fixture standards in order to accurately
characterize the parasitics introduced by the test fixture and represented by
the scattered parameters circuits.
The necessary in-fixture standards to characterize the ten parameters
and of the test fixture are the
single open, single short, open and short (Figure 3-45). These standards are
based on the de-embedding procedure proposed in [Ko100].
5.3 De-embedding procedure
The objective of the de-embedding procedure is to subtract from the
measurement of the DUT the effect of the parasitics introduced by the test
fixture.
The first step is to convert the measured DUT plus test fixture S-
parameters to Z-parameters. The purpose of this conversion is to facilitate
the subtraction of the series impedances and As shown by Figure 3-
46 the impedances and can be directly obtained from the
measurement of the single short. It is important that after measuring the
single short with one port the chip be rotated before measuring the single
short with the other port.
Then, the influence of the contact series impedances can be removed by
subtracting them from the measured Z-parameters.
The second step is to convert the to Y-parameters in order
to facilitate the subtraction of the parallel pad effects. For consistent
coupling mechanisms the substrate of the single open standard should be
grounded in a manner that resembles the real test fixture.
As shown on Figure 3-47, to isolate the parallel pad effects (Equation
3.25) we should first measure the single open standard and subtract the
contact effects using the Z-parameter. After that we can subtract them from
(Equation 3.26).
The third step is to convert the to Z-parameters in order to
facilitate the subtraction of the series interconnect parasitics. The three basic
interconnect parasitics and can be extracted by using a thru or a
short standard (Figure 3-48). If a short standard is used, it should present as
little loss as possible.
To isolate the series interconnect parasitics we measure the short
standard. After that we subtract the series and the parallel pad effects in the
same way as explained above.
Once we have isolated the series interconnect parasitics we subtract them
from (Equation 3.33).
The last step is to convert the to Y-parameters in order to
facilitate the subtraction of the intrinsic fixture coupling. The two basic
coupling mechanisms and can be extracted by using the open
standard (Figure 3-49). A dummy DUT can be placed in the fixture gap to
simulate more closely the actual test fixture.
In the same way, we should first isolate the intrinsic fixture coupling
parasitics, and afterwards subtract them from (Equation 3.42).
After all this procedure, we obtain the S-parameter of the DUT and we
eliminate the effect of the test fixture parasitics from the measurement.
It is important to note, as mentioned before, that if the test fixture is
properly designed the interconnect parasitics and can be considered
as part of the inductor and the effect of and may be neglected.
Thus only two standards should be necessary to subtract the effect of the test
fixture. These standards are the single open and the single short. In that
case the saved chip area would be quite noticeable.
6. MODEL INDUCTOR CHARACTERIZATION
After the de-embedding procedure presented in the previous section, we
obtain the inductor S-parameters where the effect of the test fixture
parasitics has been subtracted. The next step is to obtain a compact model
which describes the electrical behaviour of the integrated inductor at RF
frequencies. This model is required in order to facilitate hand calculations
and optimization of more complex RF circuits like tuned circuits (LNAs,
VCOs and RF filters).
As explained in chapter 2, the model (Figure 3-50) is the most widely
used by the research community to fit experimental measurements of
integrated inductors [Nguy90], [Ashb96], [Burg96].
In this section we present the followed steps to obtain the parameter
values of the inductor model from the de-embedded S-parameters. We do
it by modelling a balanced inductor (Figure 3-51) which dimensions are
shown in table 3-6.
The first step in order to obtain the compact model of the integrated
inductor is to transform the de-embedded 2-port S-parameters
and into 1-port S-parameters or We perform this
transformation through equations 3.44 and 3.45.
Since balanced inductors are symmetrical, 1-port S-parameters,
and should be equal
Figure 3-52 shows the and of the inductor under test. Figure 3-53
shows the and of the integrated inductor after applying the
previous transformation to the 2-port S-parameters.
The next step is to establish the values of the model parameters
through a combination of parameter identification and fitting with the aid of
a computer-driven optimizer (HP-ICCAPS, HP-ADS, MATLAB,...).
To setup the optimization, limits on the variation of all the parameters
must be established. These limits should be established according to
parameter identification done by hand or inductor simulation software like
ASITIC or MOMENTUM. If no proper limits are established the optimizer
may reach a non physical solution.
The final step in setting up the optimization process is to give the
optimizer the criteria for a good simulation. It needs to be told what the best
solution would look like so that it can determine if a variation in the
parameters improve the situation or make it worse. In the case of a balanced
inductor a good optimization criteria could be to obtain a symmetrical
model.
After optimization, the values of the model of the inductor under test
are shown in table 3-7.
Figure 3-54 shows a comparison between the de-embedded S-parameters
of the integrated inductor and the simulated S-parameters of the obtained
model. As shown by Figure 3-54 the obtained model fits quite well with the
measured data.
To check consistency of the model it is also interesting to compare the
real and imaginary parts of the measured and simulated data. To compare
both parts we should first transform the 1-Port S-parameters into 1-port Z-
parameters through equation 3.46.
Figure 3-55 shows the comparison between the measured and simulated
data of the real part and Figure 3-56 of the imaginary part. As shown they
match pretty well in the frequency range of interest between 1.4 and 1.8
GHz.
The key to obtain an accurate inductor model from the de-embedded S-
parameters is to establish proper limits to the variation of the model
parameters and define good criteria, to the optimizer, in order to find the best
solution. The rest of the effort is done by the computer.
Chapter 4
INFLUENCE OF THE GEOMETRIC
PARAMETERS ON THE INDUCTORS
PERFORMANCE: DESIGN RULES
1. PROBLEM DESCRIPTION
As previously mentioned, the problem of designing an integrated
inductor for RF applications on silicon technologies is its resulting low
quality.
136 Influence of the geometric parameters on the inductors
performance: Design rules
Therefore, to make feasible its use, the quality has to be improved. This
can be done in two ways: First, altering the environment that surrounds the
inductor, e.g., placing a ground shielding below the inductor, etc. Several
possibilities were presented in Chapter 2.
The second and much more effective way is to select correctly the
geometric parameters that define an inductor.
This way, depending on the designers needs, (e.g. exhibit the maximum
quality at a desired frequency, constant inductance over the working
frequency range, etc) the design can be optimized
Figure 4-1 shows the five geometric variables that define the geometry
of an inductor. It is worth to say most of the designers use the number of
metal layers connected in parallel to form the spiral [SKJ98] as an
additional parameter. Therefore, the resistance of the device is lowered, but
also it is the resonance frequency. We will come back to this idea in the
following pages.
Because there are 5 geometric parameters all of them affecting in
different ways the performance of the inductor, the optimization of the
inductor is very difficult. For this reason, it is really important to know how
each of these geometric parameters affects the inductor performance.
For example, when selecting the inductors track width, a designer could
face a problem. It can happen for instance that, once the whole geometry to
meet a desire inductance is selected, he wants to reduce the resistance.
In 2.1.1.1, it was shown the track width does not influence too much the
inductance value, at least between 10 and For this reason, all the
geometric parameters have been fixed to meet a desired inductance, the
width can be increased reducing their resistance. This idea has several
drawbacks,
The skin effect can affect depending on the frequency we are working
on. It can happen then that, although we are reducing the DC resistance
the total resistance does not decrease.
As the width grows, so does the metal area shared by the spiral and the
substrate. This increases the coupling between the inductor and the
substrate and consequently the resonance frequency drops, so the quality
versus frequency curve shifts to lower frequencies, as it is shown in
Figure 4-2. It can happen then, that the inductor could work in a non-
desire range, like close to the resonance frequency.
Design ant test of integrated inductors for RF applications 137
As an example it has been explained the advantages and disadvantages of
increasing an inductors track width. The objective was to show the reader
that a correct knowledge on how each parameter affects the inductors
performance is needed to make an optimum inductor design.
2. ANALYTICAL STUDY AND SIMULATIONS
In this section the geometric parameters that define an integrated
inductor are studied in detail. It is shown that the influence of some of the
parameters can be easily deducted and consequently some design rules can
be formulated. In other cases, it will be demonstrated that the influence
cannot be understood without an empirical analysis.
Some of these studies have been carried out using ASITIC. As it was
mentioned in Chapter 2 section 2.4.1, this software has several limitations
but for these studies and as a starting point for a qualitative analysis is
enough. All the simulations done in the studies presented below have been
carried out based on a standard CMOS 2 metal layer technology.
2.1 Number of sides
This is the easiest parameter to analyze based on an analytical analysis. If
the number of sides is increased maintaining the external radius fixed, the
perimeter of the inductor increases and so does the resistance. Although the
resistance increases, the inductance is also increasing and faster than the
resistance. This leads into an increase of the quality.
This last idea can be evaluated using the inductance (Equation 2.1) and
resistance (Equation 2.8) expressions for a metal track presented in Chapter
2. Naturally, this is an ideal demonstration because some frequency related
effects such as skin or proximity effects are not computed. Nevertheless, it
exhibits enough information to illustrate the previous idea.
Lets take a quarter of a turn of a square and a circular inductor with the
same geometric characteristics as it is shown in Figure 4-3. The results of
applying Equation 2.1 and 2.8 are shown in Table 4-1.
As it can be seen and mentioned before, when the number of sides grows
(square to circular geometry) the inductance grows faster than the
resistance. Clearly, it can be set as a design rule that an optimum inductor
has to be designed with the highest number of sides allowed by the
fabrication technology. This design rule can also be verified with ASITIC.
It has been simulated an inductor with a radius, width, number of turns
and spacing of 75, 12 and respectively. In Figure 4-4 it is shown
how the resistance, inductance and quality varies with the number sides at
1.8 GHz.
It can be seen that the quality of an inductor grows with the number of
sides. This design rule has also been demonstrated in bibliography [Chri99].
2.2 Spacing between tracks
The spacing between tracks is another parameter that can be understood
its influence without the need of an empirical analysis. This topic is also
extensively studied in bibliography [Yue00].
If the spacing is increased by a small percent (to ensure not a great
variation on the length) several issues in the inductors performance
The mutual inductance between tracks decreases (Equation 2.3), so does
it the total inductance. This causes the quality to diminish because the
resistance is maintained and the inductance is reduced.
On the other hand, if the spacing is reduced,
The mutual inductance grows and so does the total inductance. This
provokes the quality to augment because the resistance is maintained and
the inductance is reduced.
Clearly it seems as an interesting idea to design an inductor with the
smallest spacing allowed by the technology. It has to be mentioned that the
validity of this assumption is conditioned by the working frequency. This is
due to the fact that as the spacing is reduced the coupling capacitance
between tracks grows. Depending then on the working frequency, this
capacitance could start affecting the inductors performance.
To study a little bit more in detail this last consideration, several
simulations have been carried out with ASITIC. It has been simulated an
inductor varying the spacing between 2 and The radius, width and
number of turns have been fixed to and 3.5 turns
respectively. The results are shown in Figure 4-5.
The assumption made in the previous paragraphs is corroborated by the
simulation. It can be seen that as the spacing between tracks is reduced the
quality curve is shifted to lower frequencies.
As conclusion it can be said that to maximize the quality of an
inductor the spacing between tracks has to be set to the minimum value
allowed by the technology. Nevertheless, always it has to be taken into
account the coupling capacitance between tracks and the working
frequency.
2.3 External radius and number of turns
In this section, the external radius and number of turns have been
analyzed together because they roughly define the inductors length.
2.3.1 Number of turns
Suppose that the number of turns of an inductor is increased and the rest
of the geometric parameters are fixed,
The inductance and the resistance will grow. In this case it is needed to
evaluate which is the parameter that grows faster (as expected, in this
case it is really important to calculate precisely the resistance taking into
account all the parasitic effects). One of the most important effect is the
proximity effect. It influences all the inductors turns, but as it is studied
in [Cran97], this influence is much stronger in the inner turns. This
means that the number of turns has to be taken into account when
defining the inductors internal radius.
There is the parasitic link between the substrate and the metal. As the
number of turns increases so does the shared metal area and the magnetic
field value. Because of the increase in the area, the capacitance to the
substrate also increases shifting the quality curve to lower frequencies.
Also the magnetically induced looses in the substrate are increased due to
the increase in the magnetic field value.
It has been simulated using ASITIC an inductor varying the number of
turns between 1.5 and 6.5 turns. The radius, width and spacing have been
fixed to and respectively. The results are shown in
Figure 4-6.
As it can be seen, the only conclusion that can be extracted from these
simulations is that, as it was stated before, as the number of turns increases
the quality curve shifts to lower frequencies.
Clearly, from all this study the conclusion is that an analytical analysis
does not provide enough information to set a design rule for the number of
turns.
2.3.2 External radius
As for the number of turns, this is another parameter that can not be
analyzed correctly without an empirical analysis. This is due to the large
number of effects that are linked to the external radius, e.g. magnetically
and electrically induced looses in the substrate.
Based on bibliography it can be said that the external radius has to be
selected in accordance with the condition of not having an small internal
radius [Cran97].
In this chapter it has been evaluated, from an analytical point of view, the
influence of the external radius and number of turns in the inductors
performance. The main output of both analyses is that to formulate robust
design rules for these two parameters an empirical analysis has to be carried
out. This is due basically to the impossibility of simulating or analyzing
analytically all the parasitic effects that appear on an integrated inductor.
2.4 Width
The influence of the width was explained in the introduction of this
chapter as an example. In that analysis it was concluded that, once the
geometry has been fixed, the width should be increased as much as possible.
The increase limit is given by several issues, skin effect, reduction of the
inductance, and the electrical parasitic coupling to the substrate. How these
last two issues are affected by a change in the width can be roughly
evaluated with the inductance expressions presented in Chapter 2 and the
technology design rules. The problem arises with the skin effect.
Therefore to correctly modify the track width the first thing that the
designer should know is the skin depth of the metal track. The big problem
comes from the fact that in bibliography this value is not clear for
rectangular conductors.
In [Epan00] it is presented an equation for the evaluation of the AC
resistance of a rectangular conductor. The drawback is that it has been
extracted empirically and contains fitting coefficients.
Other publications state that Equation 2.9 is valid for rectangular
conductors [Pawl00] or they just give a value for the skin depth [Skin00].
Clearly there is a lack of information in the bibliography regarding on
how the skin effect influences an integrated inductor metal track. A deep
study of this issue is needed then.
Usually the metal tracks of a Si technology are made from aluminum, but
nowadays, in complicated processes with 5 or 6 layers, the last layer is
essentially Copper and much thicker (between 2 and Although this
layer is more and more used to design integrated inductors for RF (less DC
resistance and further from the substrate) the analysis that it is presented
below is for the aluminum layers. Nevertheless, some of the conclusions can
be extrapolated to the Copper layers.
As a starting point, in Table 4.2 it is shown the skin depth for the
aluminum at 1 GHz, extracted from bibliography [Skin00], assuming that
Equation 2.9 is valid for rectangular profiles [Pawl00] and applying the
empirical expression presented in [Epan00].
Suppose that we take [Epan00] (which gives the most restrictive skin
depth) and calculate the influence of the skin effect on the metal layer of a
conventional technology (which usually has a thickness around The
result is that the skin effect will start affecting around 8 GHz (skin depth =
thickness).
In reality this does not occur this way because the resistance is influenced
by the frequency at values much lower than 8 GHz. Therefore there is
another effect affecting the current distribution on rectangular conductors
which we have called corner effect.
Basically this effect takes into account the variation of the current density
in the corners due to the corner geometry (the current lines distribution is
not symmetric), altering the overall current density and therefore increasing
the track resistance as the frequency rises.
To analyze this idea, it has been simulated the resistance of an aluminum
rectangular metal track with two electromagnetic simulators, HP Momentum
[MOME01] and Media Sonnetlite [Sonn01].
A thick metal track has been simulated surrounded by air (the only
objective was to analyze the corner and skin effect) varying the width
between 5 and
Although the results do not match both simulators prove the idea that the
skin effect is not the only effect that affects the resistance of a metal track.
This can be seen in Figure 4-7.
An interesting conclusion that can be derived from the above simulation
is that the influence of the corner effect is much higher on small widths. If
the resistances slopes are calculated for all the simulated cases, it can be
seen that the slope for small widths is much higher than for the high
width
This is consistent with the fact that the corner current density affects in
the same way all the widths because the geometry of the tracks corners is
width independant. Because of this, tracks with lower DC resistance (higher
widths) will be less affected that tracks with high DC resistance (lower
widths).
Clearly, between 1 to 5 GHz, the corner effect is the leading parasitic
effect in rectangular metal tracks with a thickness around instead of the
skin effect.
From the simulations it can be said that it is recommended that an
inductors track width should be set between 10 and On the one
hand, at least at the simulation level, tracks with less than are strongly
affected by the corner effect. On the other hand, widths higher than
exhibit low inductance per unit length so, for a given inductance, it could be
an inconvenience because more metal track length would be needed leading
probably to higher DC resistance and coupling to the substrate.
2.5 Metal layers connected in parallel
The number of layers connected in parallel is another important
parameter to take into account when designing an inductor.
The metal resistivity, width and track length determine primarily the
inductors DC resistance. Taking into account that the metal resistivity is
fixed by the technology and the width and length are fixed mainly by the
desire inductance, the only way to reduce the DC resistance is by changing
the metal thickness.
The only way to increase the inductors thickness is by the connection in
parallel of different metal layers. This way, the DC resistance is lowered and
so the effective resistance.
Sometimes it is a problem to use the closest metal layer to the substrate
due to the increase in the coupling and consequently the shift to lower
frequencies of the quality curve. Nevertheless, in fabrication processes
where there is only available 2 or 3 metal layers it is worth to use all the
layers because the resistance reduction achieved with this technique
overcomes the reduction of the resonance frequency.
On the other hand, if it is available a technology with 4 or metal layers,
designing inductors with all the layers it is not worth it because the
improvement on the quality is indiscernible [Raza01] from using 2 or 3.
It has to be pointed out that this topic has been studied extensively in
bibliography except for the way to connect the metal layers. This is, once a
designer has decided to use 2 or 3 metal layers in parallel, the next question
that he should think of is how to connect them?. In Figure 4-8 are
illustrated several ways to connect in parallel different metal layers.
For instance, the vias can be placed at the inductors connections (L1),
along the whole inductor in a discrete way (L2), along the whole inductor in
a longitudinal way (L3) or various longitudinal in parallel (L4 and L5).
To determine in a qualitative way how the type of via affects the quality
it has been simulated two metal tracks connected in parallel by a via using
the equivalent electric schematic shown in Figure 4-9.
y are the metal 1 and metal 2 resistances. Their resistivities are
respectively.
is the via resistance. Its resistivity has been set to
and are the self inductance of each metal layer.
is the via inductance.
y represent the mutual inductance between metal layers.
C is the parasitic capacitance between layers. The capacitance per unit of
area has been fixed to
Two metal tracks of have been connected by a via with
different lengths (10, 20, 30 y From the AC simulations, the
impedance is extracted at different frequencies.
As an example, the results for the 1.6 GHz case are shown in Table 4-3.
It can be seen the percentage variation of the resistance and inductance in
relation to area of via. Similar results have been obtained for 13 other
frequencies between 1 and 2.2 GHz.
In general lines it can be said that, as the area of via increases the total
resistance and inductance decrease. But the latter property diminishes slowly
than the resistance so the quality will improve.
As a conclusion, it is advisable in technologies with up to three metal
layers to design an inductor with all the metal layers connected in
parallel with a longitudinal via as width as possible.
In this chapter it has been analyzed analytically the impact of an
integrated inductors geometric parameters on its performance. In some
cases, like the spacing and number of sides, the influence can be easily
understood from an analytical study. This is not the case for other
parameters, such as the width, number of turns and external radius. The
influence of these parameters on the inductors performance is very
complex, due to the fact that various parasitic effects come into play, such
as, electric and magnetically induced looses in the substrate, coupling
between tracks and substrate, etc. A clear need for an empirical analysis is
clear to evaluate the impact of these parameters.
In the bibliography happens the same, the spacing and number of sides is
extensively studied but not the rest of parameters. Nevertheless, there is an
study [Cran97] in which is concluded that an inductor should be designed as
a hollow spiral. This way it will be avoided the influence of proximity
effects in the internal turns which do not contribute too much to the overall
inductance. This rule is extensively used in the design community so it will
be analyzed in detail in the empirical study presented below.
3. EMPIRICAL STUDY
3.1 Inductor selection
75 inductors have been fabricated in a 2 metal CMOS
technology. The fabricated inductors are,
72 inductors with an inductance between 0.5 and 5 nH with track widths
over to analyze the impact of high track widths.
45 inductors to study the influence of the internal radius on the
inductors performance.
10 inductors to complete the via geometry analytical study.
All of them have been laid out taking into account the design rules
extracted in the previous study, specifically,
Maximum number of sides allowed by the process, 20.
Minimum spacing between turns,
2 metal layers connected in parallel by a longitudinal via with the
maximum width allowed by the process.
To determine the fabricated geometries we have used ASIT1C. It has
been simulated at 0.86, 1.6, 1.8, 2.4, and 5.6 GHz all the possible geometries
arising from varying the following parameters,
External radius, between 50 and with a step to
Number of turns, between 1.5 and 15.5 with a step of 1 turn.
Track width, between 5 and with a step of
For each frequency, 22417 possible geometries where simulated.
Afterwards, the geometries where divided into groups with the same
inductance sorted by quality. The ones with highest qualities were selected.
Dimensions of the fabricated inductors are shown in the appendix.
3.2 Fabrication and measurement
A microphotograph of some of the fabricated inductors with their
respective measurement structures is shown in Figure 4-10.
For the de-embedding it has been used the Four Step de-embedding
method explained in Chapter 3. The Single Short, Single Open, Open and
Short needed for the correct de-embedding have also been fabricated.
The measurement structures have been designed following the steps
presented in Chapter 3. In Figure 4-11 it is shown half of one of these
structures.
The ground pads have been designed with all the metal and poly layers
available in the technology whereas the signal pads only with the metal
layers. It can be noticed also that the ground plane has been designed with
both metal layers connected in parallel.
The measurements have been carried out between 0.5 to 10 GHz.
3.3 Analysis of the empirical data
We start the chapter analyzing the measured curves of an inductor
(quality, inductance and resistance). This will allow the reader to further
understand the studies presented below.
In Figure 4-12 and 4-13 are shown the measured curves of one of the
fabricated inductors over the 0.5 to 10 GHz range.
Point A sets approximately the point at which the quality ceases
increasing steeply with the frequency.
The area at the left of point A, which we call low frequency, is an area
where the quality is determined mainly by the DC resistance, skin, corner
and proximity effects and magnetically induced losses. The reasons for this
are,
The resistances slope increases softly with the frequency (Figure 4-13).
This performance also is similar to the simulated resistance at low
frequencies of a metal track presented in Figure 4-7.
The inductance does not change with the frequency. This is, the
imaginary part of the inductors impedance is not affected by parasitic
effects. This implies then that the parasitic coupling to the substrate still
exhibits at these frequencies high impedance.
The area at the right of point A, which we call high frequency, is an are
where the quality is affected, besides the effects in the low frequency, by the
electrically substrate coupling to the substrate. The reasons for this are,
The resistances slope starts to change abruptly with the frequency. This
change has to be motivated by an additional effect to the skin, corner and
proximity effects and magnetically induced losses which were affecting
at low frequencies. Clearly, the electrically induced losses in the
substrate come into play.
The inductance increases with the frequency. This implies that imaginary
part of the inductors impedance is changing with the frequency. In
contrast to the low frequency performance, in this case, the capacitance
impedance becomes of the same order of magnitude as the inductances
impedance.
Dividing this way the measured curves and associating each section to
the effects that appear on an inductor will make much easier for the reader to
follow the analysis presented below.
3.3.1 External radius and number of turns
In this chapter, the influence of the radius and number of turns on the
inductors performance is analyzed. The objective is to obtain some design
rules to be used by designers.
Two main issues arc studied,
Verify if a small internal radius (proximity effect) affects negatively the
inductors quality [Cran97]. If this was the case, which is the relation
that the external and internal radius should have to minimize this
negative influence.
Afterwards, the influence of the proximity effect in all the turns is
studied.
3.3.1.1 Influence of the proximity effect on the internal turns
As it has been already said several times, the bibliography suggests that
an integrated inductor should be designed hollow to reduce the influence of
the proximity effect on the internal turns [Cran97].
Several design rules regarding this issue can be found in the
bibliography. For instance, [Burg98] states that the internal radius should be
at least 5 times the track width. What it is not considered in this study is that
the magnetic field penetration radius depends, not only on the internal radius
but also on the external radius.
For this reason, for the study of the internal radius it is needed to define a
parameter that relates the external and internal radius of the inductor. We
have defined this parameter as CM, and it is define as,
To isolate the influence of the internal radius and CM, inductors with the
same track width have been analyzed. This way, the influence of the skin
and corner effect on the selected inductors will be the same because these
effects depend only on the tracks width and working frequency.
To make easier the analysis, it has only been studied the low frequency
performance. This way, as it was stated in section 3.3, the parasitic influence
of the electric coupling between inductor and substrate is also excluded from
the analysis.
In Figure 4-14 it is shown the measured resistance far left from point A
(section 3.3) for several inductors with a track width of The initial
slope for each curve is calculated in Table 4-4.
It can be noticed easily that, as the inductors inductance increases, the
resistance slope also increases. This leads into an interesting statement and
is that at frequencies far from the maximum quality, the losses
(resistances slope) are dominated by the magnetically induced losses in
the substrate and by the proximity effects. If this were not the case, all
the slopes presented in Table 4-4 should be almost the same because the
influence of the skin and corner effects (the other two effects besides the
magnetical coupling to the substrate and proximity effect that determine the
losses in the low frequency performance of an inductor) are the same for all
the analyzed inductors. This leads us to a second study.
Analyzing then,
Inductors with the same width, (skin and corner effects influence the
same way)
Inductors with the inductance (magnetically induced losses in the
substrate are the same)
Implies that any variation in the slopes losses at low frequency is caused
by the inductors CM and internal radius. This way it will be possible to
analyze the influence of these two geometric characteristics or better to say,
the proximity effect.
In Figure 4-15 the resistance curves (low frequency range) of two pair of
inductors which meet the above needs are shown. This is, the same width,
and the same inductance at low frequency, b_13 and b_9 with 1.6 nH,
b_20 and Bo_10 with 2.7 nH. In Table 4-5 the most interesting
characteristics needed for the analysis of the CM and internal radius are
shown.
The first issue that should be noticed is that the resistances slopes for
each case are analogous but the CM and internal radius are not.
This implies that, once the inductors track width has been selected,
the internal radius and CM should not be selected based on the
proximity effect because its influence is not linked to these two
geometric parameters, at least for a CM between 39 and 79 % and an
internal radius between 30.9 and This statement clearly differs
from [Cran97] and [Burg98] studies regarding the benefit of designing
inductors with large internal radius.
Applying this consideration will lead to more aggressive designs, higher
quality factors and a considerable saving of the silicon area occupied by the
inductor.
3.3.1.2 Link between the track width and proximity effect
The following analysis is based on the assumption that, in the low
frequency range, the influence of the skin and corner effect on the
inductors performance is small compared to the rest of the parasitic effects.
Also, it is based on the fact that once the track width has been fixed, there is
no link between the proximity effect and the CM and internal radius.
Analyzing then two inductors with,
the same inductance so the magnetically induced losses in the substrate
are the same.
different widths.
any variation in their resistances slope would only be caused by the
proximity effect.
In Figure 4-16 it is shown the resistance of two inductors with the same
inductance, 2.8 nH, and with different tracks width, (b_20) and
(Bo_20).
As it can be seen the resistances slope for the case is different
than the case. This demonstrates that the influence of the proximity
effect is linked to the track width. It is interesting to notice that the slope
increases with the track width. This is consistent with the fact that, as the
track width increases, so does the metal area that is crossed by the magnetic
field, increasing then the losses induced in the metal.
Some readers could think that the previous conclusion is inconsistent
with the conclusions presented in [Yue00]. In this study two things were
concluded,
that the proximity effect is negligible in metal tracks situated in the
same layer, at least with an spacing between them of at least
that the proximity effect is high between two metal tracks placed in
parallel and its influence increases as the spacing between then
decreases.
The fact is that in this work, all the inductors have been fabricated with
two metal layers connected in parallel by a longitudinal via. Because of the
high resistance of the via compared to the metal track resistivity most of the
current density flows through the metal tracks. This causes that the magnetic
field generated by each metal track affects the other metal track inducing
some losses, as it is shown in Figure 4-17.
It can be set then as a design consideration that the proximity effect is
linked to the track width but not to the CM and internal radius of an
inductor.
3.3.2 Skin and corner effects
In this chapter it is going to be analyzed the corner and skin effect in an
inductors metal track. The main objective is to ratify the assumption made
in the previous analysis about the negligible influence of the skin and corner
effect in relation to the proximity effects on an inductor.
8 inductors have been used in this study. The relevant characteristics for
this study are shown in Table 4-6.
Each pair of inductors has the same inductance. This implies that the
losses induced magnetically in the substrate will be of the same order. Any
variation then in the resistances slope has to be caused by the skin, corner
and proximity effect.
As it can be seen in Figure 4-18 and Table 4-7, the slope of b_14 and b_7
are similar, but as the inductance grows so does the difference between the
slopes for each pair of inductors with the same inductance. In all the cases,
the slope corresponding to the case is higher than for the case.
If the difference between slopes were caused by the skin and corner
effects, these would be almost the same for the four pair of inductors
analyzed. This is not the case and the difference in the slopes is clearly
related to the inductors inductance.
It can be concluded then that the influence of the skin and corner
effects is negligible in comparison to the losses induced by the proximity
effect, at least up to 4 GHz.
This conclusion leads to another issue. As it can be seen in the previous
Figure, inductors with the same inductance but different track width,
exhibit different resistance but with a slope dependant on the proximity
effect.
Because this slope is higher for the than for the case, as the
frequency grows, the difference between the resistances of each inductor is
reduced. It could happen then, that for a certain frequency, it is better to
design an inductor with a width of than with To illustrate this
consideration, in Figure 4-19 is zoomed out the resistance curves for b_5,
Bo_21, Bo_24 and Bo_62 inductors.
It can be observed clearly that the curves intersect at a certain frequency.
In this chapter the influence of the internal radius and CM in the
inductors performance has been analyzed. These geometric characteristics
have been linked to the proximity, skin and corner effects. Some of the
conclusions will be summarized as design rules at the end of this Chapter
and applied in Chapter 5.
3.3.3 Geometry of the via
As it was concluded in point 2.5 it is recommended to design inductors
with several metal layers connected in parallel by a longitudinal via. This
statement was made based on an analytical study. To address the correctness
of this conclusion it has been also analyzed empirically.
As it was shown in Figure 4-8 there are 5 ways to interconnect two metal
layers. Based on these possibilities, 10 inductors were fabricated and
measured. Their most interesting characteristics are shown in Table 4-8.
The study has been done on two different geometries to ensure that the
conclusions are geometry independent.
In Figure 4-20 the measured quality and inductance of the first group of
inductors (L1-L5) are shown. It can be clearly seen that the analytical study
agrees with the empirical data. This is, L1 exhibits the highest inductance
but less quality and vice versa for inductor L5.
It can be then stated as a design rule that, if an inductor is laid out with
several metal layers in parallel, they must be connected by a
longitudinal via. In the case that the technology does not allow this kind of
vias, discrete vias should be laid out along the whole metal track.
3.3.4 Track width higher than
Along this work it has been set as the maximum track width This
decision was taken based on two considerations,
There can only be found in the bibliography few designs on Silicon
technologies with 2 or 3 metal layers that use tracks width higher than
Designing inductors on Silicon technologies with 2 or 3 metal layers with
tracks width higher than leads to high coupling capacitance to
the substrate. Consequently, the resonance frequency of these devices is
very low, limiting their application to very low frequencies or
inductances.
Nevertheless, to analyze this possibility, 22 inductors have been
fabricated with a track width oscillating between 20 and
Some of the measured inductors main characteristics are shown in Table
4-9. As it can be seen, the design of inductors with high track widths is
feasible.
Although this is not a recommended technique due to the high Silicon
area that these devices can occupy, in some cases the designer can think it is
interesting to design them this way. If this were the case some considerations
have to be taken into account,
The tracks width suffers from proximity effect, but only between metal
layers connected in parallel.
As the CM of an inductor decreases, the coupling capacitance to the
substrate increases. This leads to a reduction of the resonance frequency
of the inductor.
These two considerations clearly indicate that when an inductor wants to
be designed with high quality and high track width, their inductance and
working frequency have to be low.
DESIGN CONSIDERATIONS 4.
Several design rules are presented below as a summary of the analytical
and empirical analysis done along this work. It has to be pointed out that not
all the rules have been summarized but the ones valid for all conventional
Silicon technologies. Nevertheless, all the conclusions presented along the
Chapter can be used by designers as a starting point.
The inductor has to be designed with the maximum number of sides
allowed by the technology.
The spacing between tracks should be minimized but always taking into
account that the coupling between tracks diminishes and could affect
depending on the working frequency.
The internal radius and CM, once the track width has been fixed, due not
have to be selected based on the proximity effect, at least for internal
radius higher than and CM between 39 and 79 %.
The losses due to proximity effect depend on the track width. This has to
be taking into account when evaluating the magnetically induced losses
in the metal tracks, but not between those situated in the same layer but
connected in parallel.
The losses due to the proximity effect prevail over the skin and corner
effect in the metal tracks, at least up to 4-5 GHz.
An inductor should be designed with several metal layers connected in
parallel by a longitudinal via.
It is feasible to design inductors with track widths over whenever
the inductance and working frequency are low.
In this Chapter, it has been analyzed the influence of geometric
parameters that define an inductor on its performance.
These considerations have been obtained from analytical and empirical
studies. Effective designs, high quality and low area consuming designs
would result following these rules and considerations.
Chapter 5
INDUCTORS DESIGN FLOW
In the previous Chapter, some design rules on how to select the geometry
of an integrated inductor on Silicon technologies for RF applications have
been presented. This is really helpful for designers with some experience in
the design of integrated inductors.
In this Chapter, we want to make accessible these rules for designers with
no experience at all. For that reason all the steps that should be taken to
design an inductor are presented.
Clearly, the presented design flow is orientative and it is up to the
designer to change some of the steps. This flow is based on the model,
basically due to the fact that, from the geometric parameters of the inductor
and the technology data, the parameters of the model can be estimated at a
certain frequency.
In Figure 5-1, the proposed design flow is presented. As it can be seen,
along the flow, there are several breakpoints in which, if the specifications
are not met, the designer should go back some steps in the flow. Next, every
step is analyzed in detail.
166 Inductors design flow
1. GENERATION PHASE
The first step that the designer should give is to determine a list of
geometries that meet the desired inductance. The problem that arises is how
to calculate the inductance itself. In the bibliography several methods can be
found,
Solve Maxwell equations. Using 3D or 2.5D electromagnetic simulators
this task can be accomplished. The major drawback of this approach is
that it is costly from the computation time point of view. For that, this
approach is highly recommended for the verification phase.
Use Greenhouse method [Gree74]. This method is valid for geometries
with 4 sides and the designer should develop a new algorithm for
geometries with more sides.
Use the self and mutual inductance expressions between conductors
presented in [Ashb96]. The committed error is usually over 20 %
[Hers99].
In [Sund99] three different methods on how to calculate the inductance
of an integrated inductor are presented. The first one is based on
Wheelers method [Whee28]. The second one is based on
electromagnetic principles and the third approach is based on a
monomial equation obtained from measurement fitting. The biggest
drawback of these methods is that they include some constant based on
the used technology.
Another possibility is the use of ASITIC. It is a fast method and the error
that is incurred is not so high. This method is the recommended for the
generation phase.
Once the designer has selected which method to use, he should sweep
through all the possible geometries looking for those that meet the desire
inductance.
Some of the design rules presented in the previous Chapter should be
used in order to make much easier and effective the geometry sweep. Taking
them into account the designer should fix,
The number of sides to the maximum allowed by the technology.
The spacing between tracks to the minimum allowed by the technology.
Nevertheless, it is interesting always to verify that the coupling between
tracks is low enough.
The number of metal layers that are going to be connected in parallel.
Once these variables are fixed the designer should set the sweep range
for the other geometric parameters, these are, external radius, number of
turns and track width. Based on Chapters 4 study and our experience, these
limits should be set to,
Width between 5 and
External radius between 40 and
Number of turns between 1.5 and 4.5.
Once the parameters have been set, all the possible combinations should
be sweep and the inductance calculated at the desire working frequency. As
it was stated before, the recommended method to do this is using ASITIC
due to the fact that, in some cases, up to 200.000 possible geometries are
analyzed.
2. FILTERING PHASE
The filtering phase can be divided into two steps, inductance and CM
and internal radius filtering. As it was said before, the designer could
consider some other possibilities of filtering such as merging the two steps
into one, etc. Nevertheless, we have completed successful designs following
these rules so we encourage the reader to follow them.
2.1 Inductance filtering
The first filtering should be based on the inductance. Those geometries
that do not have an inductance value close to the desired one (around
15 %) should be deleted from the generated list.
In the case that ASITIC has been used to generate the list, the filtering
could be narrowed due to the fact that the inductance calculated by this
software is always lower than the real inductance.
2.2 CM and internal radius
As it was previously demonstrated, a high internal radius does not add a
significant benefit to the inductors performance. Furthermore, it has a major
drawback which is the occupied area by the inductor.
Therefore, the list could be filtered again taking into account the rules
regarding to the CM and internal radius. The list could be narrowed then to
inductors with an internal radius around and a CM between 39 and
79%.
3. PERFORMANCE ESTIMATION PHASE
The next step in is to ensure that the selected geometries exhibit, around
the working frequency, the maximum quality and the desired inductance.
For that purpose, the geometries have to be modeled around the desired
working frequency and simulated. The easiest way of modeling these
geometries is using the model explained in Chapter 2 due to its
simplicity.
As the reader can imagine, this is the most difficult point on the design of
an inductor, due mainly to the fact that some of the models parameters can
only be estimated.
There are three ways to estimate the models parameters for a certain
frequency,
In the bibliography can be found several equations to calculate all the
model parameters [Hers99], [Chri99] as a function of the geometry. The
biggest drawback is that most of these expressions are related to the
technology used empirical parameters.
Calculate all the parameters analytically. This task is extremely difficult
for some of the parameters, specifically and
Use ASITIC. Although there is an error made in the quality value the
estimation of the frequency at which the quality is maximum is accurate
enough.
Applying one of the above methods mainly depends on the designers
experience. For the case of an experienced person, it is recommended to
calculate all the parameters analytically and estimate and based on
their experience. For a non-experienced designer, it is recommended to use
ASITIC, so a group of inductors that exhibit the highest quality at the desire
working frequency can be identified.
Once the designer has modeled all the geometries these should be
simulated. The objective is to ensure that at the desire working frequency the
geometry exhibits the correct inductance and the maximum quality.
After having all this information, the designer should filter again the list,
narrowing it to a maximum of 5 or 6 geometries based on the designers
need, for instance, maximum quality, occupied area, etc.
VERIFICATION PHASE 4.
Once the designer has a list of 5 or 6 possible geometries, he should
remodel the inductors but in a more precise way.
This is, for the calculation of and it is recommended to use an
electromagnetic simulator. and can be calculated analytically from the
geometry of the inductor and some technology parameters.
The biggest problem arises when calculating and could be
calculated supposing that the currents induced electrically in the substrate
cross an area similar to the occupied geometry. is the only parameter that
can not be estimated analytically because is technology dependant.
To give at least an order of magnitude on how these two parameters vary
with the inductors area, in Figure 5-2 and 5-3, are shown the and of
some of the measured and fitted inductors to a model. Although these
values correspond to a CMOS technology, they are extrapolable to other
technologies.
After building the model this way, the designer will have a more
feasible representation of the performance of the selected geometry. After
simulating them it should be selected those that fit the designers need, e.g,
quality factor, occupied area, relation between inductance and frequency,
etc.
In this Chapter, it has been proposed a design flow that will enable
designers to design high quality integrated inductors on Silicon
technologies. It has to be pointed out that this flow has been applied
successfully to the design of inductors with an inductance between 1 to 6
nH.
This method reduces the design cycle by optimizing the design on a
previous stage to fabrication and consequently it will lead to a reduction of
the cost and time development.
Appendix
Table A-1. Geometrical characteristics of the fabricated inductors.
Reference
Bob_12
Bobi_5
Bobi_2
Bo_40
Bob_6
Bob_14
b_10
Bo_39
b_24
b_21
Bo_67
b_2
b_14
b_27
b_9
b_5
Bo_10
b_13
b_25
b_20
Bo_24
Bo_32
b_11
External radius
224
250
270
148
180
206
82
156
84
90
130
106
54,5
69,5
84,5
99,5
114, 5
66,3
81,3
96,3
111,3
126,3
78,1
Width
5
5
5
5
6
6
6
7
7
8
9
9
10
10
10
10
10
10
10
10
10
10
10
Turns
1,5
1,5
1,5
2,5
1,5
1,5
6,5
1,5
6,5
5,5
1,5
5,5
2,5
2,5
2,5
2,5
2,5
3,5
3,5
3,5
3,5
3,5
4,5
174
Reference
b_6
b_16
Bo_8
Bo_41
Bo_48
b_28
Bo_47
Bo_69
b_1
Bo_68
b_26
Bo_46
Bo_54
b_12
b_8
b_4
Bo_57
Bo_54bis
b_22
b_8
Bo_9
Bo_6
Bo_63
b_17
Bo_45
Bo_17
Bo_15
Bo_26
Bo_43
Bo_33
Bo_70
Bo_29
Bo_36
Bo_56
Bo_58
b_23
b_15
b_19
Bo_22
Bo_28
External radius
93,1
108,1
123,1
138,1
112
60
114
118
110
122
76
116
134
72
87
102
117
132
88,8
103,8
118, 8
133,8
148,8
105,6
120,6
135,6
150,6
165,6
132
120
130
136
112
122
114
86
110
100
116
144
Width
10
10
10
10
11
12
12
12
12
12
13
13
14
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
16
16
17
17
18
18
19
19
19
19
19
Turns
4,5
4,5
4,5
4,5
5,5
1,5
3,5
4,5
4,5
5,5
2,5
4,5
4,5
2,5
2,5
2,5
2,5
2,5
3,5
3,5
3,5
3,5
3,5
4,5
4,5
4,5
4,5
4,5
4,5
3,5
4,5
3,5
3,5
2,5
3,5
2,5
2,5
2,5
2,5
3,5
175
Reference
Bo_11
Bo_70
Bo_35
Bo_71
Bo_65
Bo_59
Bo_42
b_7
b_3
Bo_21
Bo_5
Bo_3
Bo_19
Bo_53
Bo_27
Bo_50
Bob_7
Bo_44
Bo_18
Bo_30
Bo_12
Bo_20
Bo_41
Bo_62
Bob_9
Bo_38
Bob_8
Bo_66
Bo_52
Bo_14
Bob_16
Bob_5
Bo_31
Bo_23
Bob_15
Bo_16
Bob_18
Bob_10
Bo_34
Bo_51
External radius
112
114
114
112
134
112
134
89,5
104,5
119,5
134,5
149,5
130
142
154
166
176
128
134
134
111,3
126,3
141,3
156,3
171,3
166
172
133,1
148,1
163,1
178,1
193,1
132
158
182
144
172
238
116
156
Width
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
25
26
27
29
31
31
32
34
Turns
1,5
1,5
1,5
2,5
2,5
2,5
2,5
2,5
2,5
2,5
2,5
2,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
3,5
4,5
4,5
4,5
4,5
4,5
4,5
4,5
2,5
2,5
2,5
1,5
2,5
3,5
1,5
2,5
176
Reference
Bob_1
Bob_11
Bo_61
Bo_23
Bob_3
Bo_64
Bobi_3
Bobi_1
Bob_2
Bob_17
Bo_55
Bob_13
Bob_4
Bobi_4
External radius
236
234
168
112
220
142
266
248
230
176
128
216
210
252
Width
34
37
40
41
41
41
41
42
43
45
47
47
50
50
Turns
3,5
3,5
1,5
1,5
1,5
1,5
2,5
2,5
2,5
1,5
1,5
2,5
1,5
1,5
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Index
1
1-port configuration 67, 90
2
2-port configuration 67, 90
A
AC resistance 147
accuracy67, 68, 70, 76, 79, 82, 86,
88, 89, 106, 110, 116
architecture
low IF 4
super heterodyne 4
ASITIC 53, 141, 143, 144, 146,
153, 173, 174, 175
B
balanced geometry 27
C
cables 70, 81, 82, 87
cleaning 72, 75, 76
CM 174, 175
connectors 81, 82, 87
coplanar probes 65, 115
coupling
capacitive 15, 58, 59
coupling 140, 144, 147, 149,
152, 157, 159, 167, 168, 174
direct 15
inductive 15
interport 107, 112, 114, 116,
122
interterminal 107, 108, 122
D
DC resistance 140, 148, 149, 156
de-embedding 106, 121, 124, 130,
154
design flow 171, 178
E
effects
electromagnetic 31
parasitic 40, 53, 55, 62, 145,
147, 152, 157, 161
186 Contents
proximity 21, 142, 152, 156,
159, 163
skin 21, 38, 39, 46, 140, 142,
147, 148, 156, 159, 161, 163,
165, 169
electric field 26, 32, 62
electromagnetic simulators 173
electromigration 22
equation
Maxwell 173
monomial 173
errors
random 80
systematic 80, 81, 83
F
FILTER
bandpass 19
lowpass 19
RF 8, 11, 17, 22
G
gain 11, 13
geometric variables 140
geometry 140, 143, 148, 153, 166
GMD 34
guard ring 56
guidelines 107, 119
H
HBT 5, 6, 7
impedance standard substrate 78,
85
implementation 111
inductance
mutual 28, 32, 33, 35, 36, 144,
151, 173
self 32, 33, 36, 173
I
inductive degeneration 17, 18
inductor
integrated 139, 141, 147, 152,
158, 171, 173, 178
multilevel 28
in-fixture standards 121, 123
inner turns 146
L
LC parallel tank 8, 9, 10, 11, 13,
16
LNA4, 5, 8, 11, 12, 13, 14, 17, 18,
22, 49
load resistance 13
losses
metal 22
ohmic 32, 41, 44, 47, 57, 59, 60
M
matching network 17
measuring
equipment 82
errors 79
MESFET 4, 5, 7
metallization issues 106, 116
method
Greenhouse 173
Wheelers 173
model
model 43, 45, 46, 47, 49, 50,
52, 54, 56, 60, 68, 90, 94, 96,
99, 105, 130, 134, 137, 171,
175, 176, 177
transformer 43, 46
wideband model 22, 43, 47
N
noise figure 4, 11, 17, 19
number of
sides 142, 143, 152, 168, 173
Contents 187
turns 143, 144, 146, 152, 157,
174
N-well 58, 59
O
on wafer 68, 82, 85
P
pad
dimension 110
material 116
shape 110, 119
parallel conductors 34
passive 25
perimeter 142
phase noise 6, 14, 15, 16
planarization 72, 87
power
amplifier 5, 19, 22
consumption 14, 17
probe
alignment 88, 117
station 66, 67, 76, 77
Q
quality factor 31, 49, 51, 52, 53,
55, 56, 57, 58, 62, 139, 140,
142, 143, 145, 146, 150, 151,
153, 156, 157, 159, 166, 168,
169, 175, 176, 178
R
radio frequency 25, 49, 50, 52
radius
external 142, 145, 147, 152,
153, 158, 174
internal146, 147, 153, 157, 160,
163, 165, 168, 174, 175
rectangular profiles 148
repeatability 67, 80, 88, 89, 120
resistance 140, 142, 143, 145, 148,
151, 155, 158, 159, 161, 164,
165
resonance frequency 9, 16, 140
S
sensitivity analysis 90, 99
setup stability 118
skating 71, 74, 111
slope 149, 157, 159, 161, 164
solenoidal 29, 30
SOLT calibration 78, 85
spacing 143, 145, 152, 162, 168,
174
spectrum analyzer 67
spiral 25, 26, 27, 28, 30, 31, 32,
35, 36, 37, 39, 40, 42, 44, 45,
47, 51, 52, 53, 55, 56, 57, 58,
59, 60, 61, 62, 140, 152
standard
load 85, 87, 88
open 85, 87, 125, 128
short 85, 86, 89, 127
single open 123, 125, 130
single short 123, 124, 130
thru 85, 87
substrate
grounding 112, 113
issues 106, 107, 109, 112
losses 22
shielding 60
T
test equipment 66, 67, 68, 70, 79,
84, 105
test fixture 65, 67, 105, 106, 107,
111, 121, 122, 123, 124, 125,
128, 130
thickness 148, 150
tolerances 106, 109, 118
toroidal 29, 30
188 Contents
track width 140, 141, 147, 149,
153, 158, 161, 162, 163, 165,
167, 169, 174
transconductance 13
via 151, 152, 153, 162, 166, 167
VNA 67, 69, 70, 75, 78, 80, 81,
82, 88, 90
V
wear
VCO 4, 8, 14, 16, 22, 27, 49
W
71, 118, 121

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