Alex Robertson Graphene-Boron Nitride Nanostructures
Graphene-Boron Nitride Nanostructures:
Properties, Fabrication, and Applications
Alex Robertson December 2013
Graphene's characteristic physical and electrical properties have earned the one-dimensional carbon structure a reputation amongst researchers as our next potential wonder material in the tradition of steel, glass, and plastic. Significant obstacles remain, however, before graphene may be implemented in ways that enable micro- and macro-scale innovation while improving upon the efficiency of existing technologies. Among them: the absence of an inherent band gap, the lack of a reliable method for growing pristine large-area sheets, and the environmental vulnerability resulting from the fact that each and every atom in a given single-layer sample is exposed to its surroundings. Another key hurdle is that many of graphene's spectacular electrical behaviors necessitate an atomically flat, distortion-free surface, which proves difficult to maintain with traditional silicon wafer processing techniques and substrates. Boron nitride, a material whose lattice approximately mirrors that of graphene, appears to present a promising solution for both the substrate and environmental susceptibility issues. Interfacing hexagonal Boron Nitride (hBN) with graphene also entails a streamlined device fabrication procedure and allows for 1-D electrical contacts. This paper investigates physical principles underlying the graphene-hBN (G-hBN) relationship, manufacturing approaches involved in growth of hBN and graphene, experimentally measured attributes of G-hBN devices, and applications in which G- hBN could become especially valuable.
Hexagonal Boron Nitride: The Ideal Substrate for Graphene?
Silicon dioxide is a ubiquitous substrate in the microchip industry, meeting demands set by the conventional fabrication of microstructures and electrical pathways. It can be thermally grown or deposited with ease, is resistant to high-temperature treatments, and is suitable as a sacrificial layer for certain types of surface micromachining. When used in conjunction with polysilicon (or other materials?) structural layers, SiO 2 substrates do not compromise a given device's sensitivity and consistency of performance. The same cannot be said for SiO 2 -supported graphene devices. SiO 2 's relative roughness, charge impurities, and surface phonons induce scattering that causes graphene's carrier mobility to fall far below its expected value. These factors disturb charge neutrality of our "2D electron gas", transforming it into a mishmash of electron and hole regions instead of the homogeneous state required for unadulterated high- performance graphene. Suspending graphene over chip surfaces was found to alleviate some of these drawbacks, but such approaches came with their own set of complications involving design composition and robustness. The substrate problem frustrated research teams for a number of Alex Robertson Graphene-Boron Nitride Nanostructures Figure 2. Samples used in (#). Dashed lines indicate the Raman-tested areas. At left is a graphene flake spanning both BN and SiO2, and at right is the G-hBN sandwich. Figure 1. Graphene and hBN share correlative roughness values, while SiO 2 's surface is generally more than twice as irregular. years after Geim and Novoselov opened the graphene floodgates with their 2004 study of the quantum Hall effect in single- and bi-layer samples. A 2010 paper written here at Columbia first identified boron nitride as a marked improvement over SiO 2 and other oxides, as it allows for overlaid graphene sheets to remain essentially undisturbed in terms of electrical and structural attributes. Boron nitride shares a lattice mismatch of only 1.7% percent with graphene, with its boron and nitrogen atoms residing at locations effectively equivalent to the A and B carbon sublattices in graphene. Because of this mirroring, hBN is similarly planar down to the atomic level. Graphene flakes placed on hBN, then, retain the true 1-D flatness that is a prerequisite for achieving maximal electron transport speeds. In addition to being a favorable match on a purely physical level, hBN electrically complements graphene as well. Whereas graphene is a zero-bandgap semiconductor susceptible to chemical contamination, hBN's energy distribution generates a sizable 5.97 eV bandgap, and its stable ionic bonding ensures the absence of dangling bonds or charge traps that would mar the condition of adjacent graphene samples. Electrical performance of G-BN devices will be discussed in-depth later in this paper.
Raman spectroscopy is a highly useful tool in assessing the condition of material samples, and it has been widely used by researchers to measure the extent of distortion present in graphene samples on various substrates. By generating a plot of Raman shifts against intensity and then comparing the resulting characteristics of the 2D and G peaks to those arising from samples known to be pristine, the relative quality of a tested sample can be determined. A 2012 Alex Robertson Graphene-Boron Nitride Nanostructures Figure 3. Raman curves before annealing, after annealing, and in vacuum. (a) = graphene on SiO 2 (b) = graphene on h-BN (c) = graphene sandwiched within h-BN study headed by Columbia's Lei Wang and overseen by Dr. Hone compared the Raman fingerprints of three types of structures on SiO 2 : a standalone graphene sheet, a graphene-BN stack with the graphene's top surface exposed to air, and a BN-graphene-BN sandwich that fully encases the graphene. Along with the position and width of the 2D and G peaks, the ratio of their peak intensities (I 2D /I G) provides valuable insight into the state of tested samples. Using high-quality suspended graphene as a benchmark, the Raman results prove that, in terms of allowing the natural state of graphene to persist, hBN is a vast improvement over silicon dioxide. Whether simply resting on hBN or encased within two sheets of it, graphene in these cases generated Raman peaks whose positions, widths, and I 2D /I G values are significantly closer to those of pristine suspended graphene than are the peak characteristics of the graphene-on-SiO 2
sample.
These tests also confirmed that after annealing, despite the presumed removal of PMMA and tape residue, the quality of graphene transferred directly onto SiO 2 actually falls off, an observation made previously by other researchers. The reason for this is that annealing causes the graphene flake to become more atmospherically sensitive and to conform more closely to the peaks and valleys of the SiO 2 , which increases the amount of interaction with local charge impurities and surface phonons. Also, water and oxygen trapped between the SiO 2 are able to more easily carry out an oxidation/reduction reaction with graphene's electrons (#), Thus, the amount of effective p-doping rises, which in turn shifts the 2D and G peak positions and decreases the I 2D /I G value. Positioning a layer of h-BN between the graphene and SiO 2
counteracts this effect to some extent by protecting the graphene from SiO 2 doping, but I 2D /I G
falls off by forty percent from the ideal pristine graphene condition. By comparing the 2D peak positions and taking upshifts to be representative of hole doping, Wang et. al conclude that the h- BN interface reduces doping by almost ninety percent relative to SiO 2 . While h-BN shields graphene from destructive SiO 2 electric fields, a relatively small but significant amount of doping still results from the graphene surface's interaction with air. In an attempt to eliminate Alex Robertson Graphene-Boron Nitride Nanostructures Figure 4. Comparisons of the salient Raman findings in (3), which show that the BN-G-BN sandwich is a near-ideal structure, both retaining the intrinsic properties of graphene and protecting it from environmental perturbations. this, L. Wang et al. add a second layer of hBN on top of graphene so that the flake is completely sandwiched. The results are promising--although the 2D peak upshifts somewhat and decreases in width, the other Raman data features all compare favorably with pristine suspended graphene. The hBN-graphene-hBN sandwich 's G peak is located at 1581 cm -1 with width 16 cm -1 , and I 2D /I G ends up being about 11, similar to the pristine case. In addition to preserving graphene's innate properties at room temperature, the sandwich structure protects the inner flake during high- temperature annealing processes. This feature may prove invaluable if hBN-G-hBN sandwiches are to be implemented on an industrial scale, as electrical microstructures often must be able to withstand exposure to high temperatures during manufacturing and commercial use. Before discussing the electronic properties of graphene-BN heterodevices and addressing potential future roles in field-effect transistors, let's take a look at how graphene and boron nitride samples are produced and how G-BN stacks are assembled.
Manufacturing Graphene and Boron Nitride: Approaches and Challenges
Graphene exhibits extraordinary electronic qualities and boron nitride has been verified as a highly suitable substrate for graphene devices; why, then, don't we see such devices being applied in any sort of practical way? One explanation: manufacturing high-quality graphene and boron nitride sheets on a prolific level is extremely difficult. This problem holds us back in two ways. One, it limits the rate at which graphene researchers can carry out novel experiments and find more efficient, useful approaches. And two, if and when we develop a paradigm-shifting G- BN device, the amount of graphene and boron nitride available will not meet demand. Mechanical exfoliation, one of the methods of choice for isolating single-layer graphene and for stripping usable samples from BN crystals, is a painstaking process that is not amenable to automation and produces samples that are only on the order of hundreds of square microns. Chemical vapor deposition, meanwhile, offers the advantage of enabling the production of much larger graphene sheets, but grain boundaries, bilayer patches, and other structural impurities are often present. The mass manufacturing challenge is a daunting one, but let's take a look at the bright side. Boron nitride, in what is yet another clear advantage over SiO 2 , shares a strong Van der Waals attraction with graphene. We can use this VDW interaction to firmly stack successive Alex Robertson Graphene-Boron Nitride Nanostructures Figure 6. Graphics and STEM images showing the fabrication process and 1-D contacts developed for use in (#). Virtually no leaking of metal into the hBN-G-hBN sandwich occurs.
Figure 5. Illustration of the stacking technique used in (#) to assemble together hBN and graphene layers through VDW attraction. This process is residue-free and relatively user-friendly.
layers of graphene and BN upon each other without introducing any contaminating polymers or residues. Completed stacks can then be transferred to a wafer surface and subjected to e-beam lithography, etching, and metal deposition according to the type of device desired. Further research will be necessary to develop ways of ensuring initial BN pick-up by PPC and controlling the resultant lattice alignments, but for now this process meets the needs of researchers and allows for novel types of fabrication and experimentation that will be discussed in the subsequent section.
Electrical Performance of G-hBN Devices
As addressed earlier, Raman spectroscopy results establish that sandwiching graphene between layers of boron nitride allows the encapsulated graphene to remain in a near-pristine state. Does electrical experimentation verify that such structures allow for the perpetuation of graphene's intrinsic properties? Recent publications suggest as much. It is demonstrated in L. Wang et al. that hBN-G-hBN sandwiches represent an improvement over other types of graphene devices for two reasons. First, as has already been discussed: sandwiched graphene retains atomic flatness while being sheltered from environmental factors. Second, and just as importantly: contact resistance in sandwich devices can be reduced to a previously-unachievable level through the utilization of a new fabrication process made possible by these types of stacks. Demonstrated in Figure 6, metal can be deposited upon the etched, slanted sidewalls of a hBN- G-hBN sandwich to create a one-dimensional contact surface between the metal and graphene. Other Alex Robertson Graphene-Boron Nitride Nanostructures Figure 7. Plot of channel length vs. total resistance for one of the devices tested in (#). Contact resistance was determined by extracting the y-intercept value of a linear fit to the data, and resistivity by calculating the slope.
Figure 8. Two devices tested in (#) showed slight differences but similar trends, with peaks near the respective CNPs and assymetry between n-type and p-type gating. graphene device designs rely on two-dimensional electrical contacts, which will always generate resistances that exceed what is possible with a 1-D interface. This can be attributed to the absence of bond-friendly sites on the graphene surface and the disturbance of graphene's in-plane sp-2 hybridization by applied surface contacts. Though this new method of creating a metal- graphene connection has room for improvement (margins of error arising from the equipment used during fabrication necessitates the metal's overlap onto the top sandwich surface; removing this overlap could further enhance device performance), its implementation in two-terminal and four-terminal testing yielded transport characteristics never before seen in devices based on graphene or any other 2-D material.
Using the transfer-length method, L. Wang et al. varied the backgate voltage applied to the device shown in Fig. 7, whose contacts were dispersed over a two-micron wide hBN-G-hBN sandwich. In doing so, the carrier density present in the graphene was modulated, and the channels, each with a pair of edge-contacts, were subjected to voltage-current tests from which the effective resistances could be extracted. Then plotting channel length and resistance against each other, the contact resistances at different carrier densities were inferred from the plot's y-intercepts (where channel length=0). These resistances end up being as much as a 25% improvement over those associated with the highest quality surface contacts, with an R c value of approximately 150 m in the case of high density n-type carriers. After accounting for the channels' quantum resistance, it can be determined that the edge contacts are responsible for about 100 m. Figure 8 exhibits the relationship between carrier density and contact resistance; the peak occurs near the charge neutrality point due to the low density of states present in graphene, and the resistance begins to flatten out at a higher level with negative carrier density (p-type) than with positive density (n-type). This characteristic arises from the details of the metal deposition process. A chromium layer is what actually bonds to the sandwiched graphene layer, with palladium and gold then deposited on top. Chromium's Fermi energy is Alex Robertson Graphene-Boron Nitride Nanostructures Figure 9. The relationship between carrier density and electron mobility in the device tested in (#). hBN-G-hBN sandwiches with edge-contacts outperform a variety of 2-D semiconductor materials. .16 eV greater than graphene's. Thus, the minimum energy required to remove an electron from Cr is .16 eV less than it is for graphene, which can be determined by comparing the differences in energy between electrons at the upper cusp of Cr and graphene's valence bands and electrons in a vacuum without electric fields. Wang et al. carried out an ab initio analysis of the Cr- graphene edge-contact design that showed a shorter bonding distance and greater orbital overlap than is observed with two-dimensional contacts. This closer proximity improves the ease of electron transmission between the materials, thereby lowering the inherent resistance. Even tighter bonding is made possible by the presence of oxygen in conjunction with Cr and graphene. The amount of oxygen exposure was not closely monitored during the fabrication of the tested devices, but it is theorized that O 2 was incidentally introduced to the edge-contacts during etching. Additional computational simulations, which were carried out assuming a Cr-O- graphene complex, matched up well with data collected during device testing. Going back to the .16 eV difference in ionization energy between Cr and graphene: simulations predicted a minimum in contact resistance at E-E CNP = .16 eV, which correlates with a carrier density of 2.2 x 10 12 cm -2 . The rightmost side of Figure 8's curve is in accordance with this prediction, while the leftmost portion shows that the device's contact resistance cannot approach this minimum when graphene's Fermi level is pushed below the Dirac point (p-type gating). N-type gating can align the Fermi energies of graphene and chromium, thereby allowing for maximum ease of electron transmission between the two.
In regards to total device performance, what implications arise from the low resistances associated with edge-contact geometry? The results of four-terminal testing at room temperature prove that hBN-G-hBN sandwiches with 1-D edge-contacts are able to maintain high electron mobility even with elevated carrier densities. Falling off from a peak value of over 140,000 cm 2 /Vs, the mobility hovers near 40,000 cm 2 /Vs at carrier densities up to 4.5 x 10 12 cm -2 . Figure 9 shows that this performance trumps the properties of even the most cutting-edge 2-D semiconductor materials and that the upper bound established by acoustic phonon scattering is approximately realized. Some of the plotted semiconductors are widely used in field-effect transistors, and in the next section we will address specific applications in which hBN-G Alex Robertson Graphene-Boron Nitride Nanostructures heterostructures could eventually render them obsolete. One more note about this four-terminal device: negative resistances were observed during testing at 1.7 K, which means that incoming electrons breached the ballistic regime and travelled diagonally between contact points rather than along an edge. With the device's dimensions being 15 m 15 m, the electrons must have had a mean free path of 21 m or greater, suggesting a mobility value of over 1,000,000 cm 2 /Vs. The mean free path and mobility scale with device size, so even greater values can be expected in larger hBN-graphene-hBN stacks.
G-hBN Technology: Applications, Limitations, and Future Directions
Having established that the use of boron nitride substrates and 1-D edge-contacts can allow for graphene's intrinsic qualities to persist throughout fabrication treatments and environmental variations, let's look at how these heterostructures may be applicable in real-world technologies with a focus on field-effect transistors. Until a method of introducing a bandgap in graphene is discovered, edge-contacted hBN-G-hBN sandwiches will not be useful as an on/off switch in digital logic systems, but their immense carrier mobility, scalability, and minute resistance could propel them to a leading role in high-frequency analog FETs. The difference between an analog transistor and a digital transistor is simple: analog transistors carry a level of DC bias between source and drain and are often used to power some sort of physical motion or output, while digital transistors act purely as signal processors with dual on and off modes in which there is a clearly discernible presence or lack of current in the channel. In both cases, the transistor's output is controlled by way of the applied gate voltage, which in turn controls the channel resistance.
The bottom-line goal of high-frequency analog transistors is to take a small input signal and generate an output at the same frequency but with a larger amplitude. To paraphrase an example used by Dr. Nicholas Petrone in a discussion about the fundamentals of graphene FETs, we want to be able to receive a weak input like the radiofrequency representation of someone's voice, originating from a distant antenna, and turn it into a loud and clear stream of sound emitted from the earpiece speaker of a telephone on the receiving end. The graphene FET equivalent of this process is transform a high-frequency, low-amplitude gate voltage oscillation into a high- amplitude channel current oscillation of equal frequency.
Yet another way in which graphene distinguishes itself is that it can transmit charge on an ambipolar basis. This trait is critically important to high-frequency graphene FETs and is responsible for the flattened-out regions of the V d vs. I d plots on the following pages. Ambipolarity comes into play as source-drain voltage changes while in the presence of a constant gate voltage. As an exercise, let's assume that our drain is fixed at a potential of 0 V, that our backgate is initially set to 0 V, and that the CNP of our graphene sample occurs at a 1 V gate voltage. With 2 V then applied to our source, the relative potential difference between the Alex Robertson Graphene-Boron Nitride Nanostructures Figure 10. Resistivity-V g and I-V characteristics of devices tested in (#). By holding V d constant and varying the gate-voltage, the channel current can be induced into jumping from curve to curve. source and gate becomes 2 V, and the graphene encompassed in this region is effectively n- doped, comparable to being shifted to the right of the peak observed in an R vs. V g curve. On the other hand, the relative voltage between our drain and gate is still zero, which would place the influenced graphene to the left of the V g -R peak (the peak occurs at 1 V, where DOS is at its minimum and the resistance at its maximum). Thus, the graphene channel is p-type at its drain end and n-type at its source end, and somewhere in between the two we can imagine an n-type/p- type meeting point, which is the charge neutrality point. This junction shifts along the length of the channel as we increase the drain voltage and will near the drain itself as we pass a V d of 1 (at this point the source-gate region is still n-type and the drain-gate region hits the resistance peak occurring at 1 V). At drain voltages beyond 1, the graphene channel is fully n-type.
So how does this example relate to graphene's ambipolarity and to experimental data? Whenever the n-type/p-type junction is present in the channel, our FET is operating in the ambipolar regime. Whereas the relation between voltage, current, and resistance is typically described by V=IR, the ambipolar junction introduces a whole new ballgame: for as long as it exists within the channel, increasing voltage does not result in a similarly elevated current (there is a subtle increase, but the direct relationship between I and V is clearly abandoned). Once the ambipolar junction/CNP makes its exit and the channel is once again either entirely n-type or entirely p- type, the normal I-V interaction reemerges.
When the CNP enters our graphene channel, current is said to have been saturated. Figure 10's plots assist in visualization--I sat occurs where the curves begin to flatten out. Current saturation is important because it leads to high transconductance values. Transconductance, or g m , is defined as( dI sd /dV g )| Vsd and has a direct impact on the achievable f T and f max values. A large g m
value generates a large proportional change in channel current relative to a given change in gate voltage; this type of behavior is highly desirable for analog transistors designed to amplify an input signal represented by gate voltage oscillation. As can be seen in Figure 10, the curves Alex Robertson Graphene-Boron Nitride Nanostructures Figure 11. I. Meric et al. manufactured a high- performance grapheme-based FET with BN on only one side of the grapheme flake; this will likely be improved upon by instead using a hBN-G-hBN sandwich structure. corresponding to different gate voltages are bunched together in the non-current-saturated zone. Here, an applied change in gate voltage will generate a very small change in channel current that is exactly what we do not want to happen.
fT and fmax give the maximum oscillation frequencies at which current gain and power gain, respectively, retain values greater than one. A device operating with gain below one is useless because no signal amplification occurs. If the creation of graphene-based high-frequency analog FETs is our goal, then fT and fmax are our central parameterswe want to push them as high as possible and also keep their ratio close to unity. Though they are directly interrelated, fmax is the more important of the two because it takes into account external factors such as the gate and output resistances. 3 As shown in Figure 11, I. Meric et al. presented G-hBN FETs with fT and fmax values on the order of 40 GHz, which had never before been accomplished with a graphene-based system. The data collected in (3) came from top-gated G-hBN devices; fully sandwiched graphene-based FETs have not yet been tested, but we can expect them to display even higher fT and fmax values both because the graphene will be of a finer quality and because the lower resistances associated with edge-contacts will boost the transconductance. One last note regarding ambipolarity: it is additionally advantageous to operate a graphene FET with our CNP inside the channel because any parasitics affecting Vsd will have less of an impact on channel current.
How exactly do graphene-based FETs represent an improvement over existing devices? Their size is an obvious upsidescaling FETs down to the nanometer scale allows for more rapid channel transport and a greater density of transistors on a surface. Meanwhile, very large f T and f max values improve the resolution at which an input signal can be processed. Radar and other sensing technologies would be made more precise by this feature, and the clarity of long-distance radiofrequency-dependent communication systems could be improved. Another major advantage is that high-level performance is achievable at low saturation voltages, which means that devices incorporating G-hBN FETs will have to supply only a small amount of power to enable their sustained operation; in the process, battery lifethat great empowerer and bane of contemporary human behaviorwill be extended. The intriguing potential of incorporating G- hBN structures into next-generation high-frequency transistors has been well demonstrated, and Alex Robertson Graphene-Boron Nitride Nanostructures imminent experimentation with hBN-G-hBN sandwiches will likely further expand the realm of performance possibilities.
Conclusion
The use of hexagonal boron nitride as a substrate in graphene-based devices has allowed us to more fully harness graphenes exceptional properties than ever before. hBNs structural and electrical properties are a near-perfect complement to those of graphene, and by fabricating tri-layer hBN-G-hBN stacks, graphene flakes can be fully protected from environmental contamination. The assembly process entailed by these stacks is relatively straightforward and does not require the introduction of polymers or other residues to graphenes surface. Field-effect transistors incorporating two-layer hBN-G stacks have exhibited outstanding high-frequency characteristics. Testing of FETs that implement hBN-G-hBN sandwiches and their accompanying low-resistance edge-contacts should reveal further enhanced performance; these devices may represent the future of high-frequency analog transistors and flexible electronics. The challenge of mass-producing pristine samples is still a major one, but the recent application of boron nitride to graphene-based structures may one day be looked back upon as a critical development in graphenes leap from the lab to the streets.
Alex Robertson Graphene-Boron Nitride Nanostructures References
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