IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO.

1, JANUARY 2011

allows higher level of reconfiguration compared to blurred images for

same quality [Fig. 6(d)].

165

A Low-Jitter ADPLL via a Suppressive Digital Filter and

an Interpolation-Based Locking Scheme
Hsuan-Jung Hsu and Shi-Yu Huang

V. CONCLUSION
We have presented a reconfigurable SRAM architecture for
low-power mobile multimedia applications. The proposed architecture
uses spatial voltage scaling where cells storing lower-order bits of
an image pixel are operated at a lower voltage, and the higher-order
cells are operated at nominal voltage. The results demonstrate that
45% power savings can be obtained with marginal image quality
degradation.

AbstractIn this brief, we present a low-jitter and wide-range all-digital

phase-locked loop (ADPLL). This ADPLL achieves low output clock jitter
by a number of schemes. First, the phase is locked quickly through a predictive phase-locking scheme. Then, the jitter is further reduced by a suppressive digital loop filter. Finally, an interpolation-based locking scheme is utilized to enhance the resolution of the digitally controlled oscillator (DCO)
so as to further reduce the phase error and jitter. Simulation results show
that the jitter performance is very close to that of the free-running DCO.
and jitter
are 56
Measurement results show that the jitter
and 7.28 ps, respectively, when the output clock of the ADPLL is running
at 600 MHz.

REFERENCES

Index TermsAll-digital phase-locked loop (ADPLL), digital filter, digitally controlled oscillator (DCO), frequency interpolation, locking algorithm.

[1] S. Yang et al., Power and performance analysis of motion estimation

based on hardware and software realizations, IEEE Trans. Computers,
vol. 54, no. 6, pp. 714716, Jun. 2005.
[2] G. Chen and M. Kandemir, Optimizing address code generation for
array-intensive DSP applications, in Proc. Int. Symp. Code Generation
Optimization, 2005, pp. 141152.
[3] S. Mukhopadhyay et al., Modeling of failure probability and statistical
design of SRAM array for yield enhancement in nano-scaled CMOS,
IEEE Trans. Comput.-Aided Design, vol. 24, no. 5, pp. 18591880,
Dec. 2005.
[4] F. Kurdahi et al., Error aware design, in Proc. 10th Eur. Conf. Digital
System Design Architectures, Aug. 2007, pp. 815.
[5] A. K. Djahromi et al., Cross layer error exploitation for aggressive
voltage scaling, in Proc. IEEE Int. Symp. Quality Electronic Design,
Mar. 2007, pp. 192197.
[6] J. George, B. Marr, B. E. S. Akgul, and K. V. Palem, Probabilistic
arithmetic and energy efficient embedded signal processing, in Proc.
CASES, Oct. 2006, pp. 168198.
[7] K. Yi, S. Y. Cheng, F. Kurdahi, and A. Ettawil, A partial memory
protection scheme for higher effective yield of embedded memory for
video data, in Proc. ACSAC, 2008, pp. 273278.
[8] M. Cho, J. Schlessman, W. Wolf, and S. Mukhopadhyay, Accuracyaware SRAM: A reconfigurable low power SRAM architecture for mobile multimedia applications, in Proc. ASPDAC, 2009, pp. 823828.
[9] K. Zhang, V. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N.
Vallepalli, Y. Wang, B. Zheng, and M. Bohr, A 3-GHz 70 MB SRAM
in 65 nm CMOS technology with integrated column-based dynamic
power supply, in Proc. ISSCC 2005, pp. 474611.
[10] [Online]. Available: http://www.imageprocessingplace.com/
[11] Z. Wang, A. C. Bovik, H. R. Sheikh, and E. P. Simoncelli, Image
quality assessment: From error visibility to structural similarity, IEEE
Trans. Image Process., vol. 13, no. 4, pp. 600612, Apr. 2004.
[12] T. Liu, T. Lin, S. Wang, W. Lee, J. Yang, K. Hou, and C. Lee, A 125
uW, fully scalable MPEG-2 and H.264/AVC video decoder for mobile
applications, IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 161169,
Jan. 2007.

I. INTRODUCTION
In a system-on-chip (SOC) era, it is common that a chip is embedded
with its own clock generator. Phase-locked loop (PLL) is an important
clocking device for these digital systems. Traditionally, a PLL is partly
made of some analog components. However, an analog control signal
is often subject to digital switching noise so that more design efforts are
needed when operating in a noisy digital environment. Moreover, the
loop filter in traditional analog PLLs is usually composed of passive
devices, such as resistors and capacitances, leading to not only large
area but also low portability to different processes. On the contrary, an
all-digital phase-locked loop (ADPLL) has not only higher noise immunity but also a number of other attractive features, including better
testability, programmability, and ease of integration into digital systems. With the aid of digital filtering techniques, the passive devices
could be avoided to save the cost and increase the portability of the
ADPLLs.
Numerous works on ADPLL have been presented in the past [1][4],
[6], [9][12], in which the digitally controlled oscillator (DCO) is at
the heart. Unlike the traditional analog voltage controlled oscillator
(VCO), the oscillator in ADPLL is digitally controlled so that some
quantization error exists. High-resolution design of DCO is thus pursued to catch up with the performance of analog VCO where the resolution can be defined as the minimum delay difference between the
clock periods of two adjacent frequencies a DCO can generate. How to
design the fine-resolution delay cell becomes the early challenge of the
DCO design. Several types of DCOs have been analyzed and summarized in [12]. In [8], the average resolution of DCO could be enhanced
to as fine as 1 ps with the insertion of more delay cells and control lines,
implying that the performance bottleneck of ADPLL is now shifting to
the other components such as the phase detectors (PDs) and/or the loop
filters.
In addition to the DCO, the resolution of an ADPLL is also dictated
by the phase-frequency detector (PFD), or simply PD in some ADPLLs. Recently, the design of a high-resolution PD that is able to distinguish a minute phase difference is becoming more desirable. Sheng
Manuscript received January 15, 2009; revised May 18, 2009. First published
October 13, 2009; current version published December 27, 2010.
The authors are with the Department of Electrical Engineering, National
Tsing-Hua University, Hsin-Chu 30013, Taiwan (e-mail: hjhsu00@larc.ee.
nthu.edu.tw; syhuang@ee.nthu.edu.tw).
Digital Object Identifier 10.1109/TVLSI.2009.2030410

1063-8210/$26.00 2009 IEEE

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Fig. 2. Locking procedure of the ADPLL.

Fig. 1. Architecture of the ADPLL.

et al. [6] used pulse amplifier and signal extender to amplify the small
phase difference, i.e., 5 ps, to be detected. Tierno et al. [11] inserted a
meta-stability filter to enhance the resolution of proposed PFD. In [12],
we discovered that a latch-based sense amplifier could be modified to
serve as a good PD in which the minimum resolvable phase difference
is as small as 1 ps.
Since the two critical components, i.e., the PD and the DCO, have
performed almost as well as their analog counterparts, the digital loop
filter or called controller in the ADPLL turns into a new focal point. The
digital loop filter, in some sense, seems like the bridge between the PD
and the DCO. It converts the phase information received from the PD
into a digital code sequence that directs the increase or the decrease
of the frequency of the DCO. This is especially difficult for ADPLLs
since most PDs only provide the phase polarity, not the exact phase
magnitude. Whether the frequency of DCO can adequately react to the
phase polarity has a large influence on performance parameters such as
jitter and phase noise.
In this brief, we present an ADPLL that reuses the high-resolution
DCO and the PD proposed in [12]. We further improve its jitter performance by a four-step frequency/phase locking procedure: 1) frequency
locking, 2) preliminary phase locking, 3) jitter reduction by a suppressive filter, and finally 4) phase error reduction by frequency interpolation. Experimental results show that the proposed scheme can reduce
the jitter to a level as small as 7.28 ps, which is only 3% away from the
ideal jitter amount (7.06 ps) of a free-running DCO, when the output
clock is operating at 600 MHz.
The rest of this paper is organized as follows. Section II provides the
overview of our ADPLL architecture and the designs of the DCO and
the PD. Section III discusses the details of the four-step locking procedure. Section IV presents our experimental results. Finally, Section V
concludes.
II. THE ADPLL ARCHITECTURE
A. Overall Architecture

Fig. 1 shows the architecture of the proposed ADPLL. In integerADPLL, the frequency of the output clock signal generated by the DCO
is divided by times to produce a divided clock signal. The parameter
will be referred to as the frequency multiplicative factor in the sequel. When the frequency of an ADPLL is locked (i.e., the frequency
of divided clock has the same frequency as the reference clock), the
output clock frequency is times the reference clock frequency.
The DCO is often regarded as the most critical part among these
components because it dictates the frequency range and the resolution
that an ADPLL can synthesize. It is controlled by 12 b in our design,
dividing into two parts: a 6-b coarse control code and a 6-b fine control code. The PD is to compare the phase polarity between the divided

Fig. 3. Relationship between phase error and control code.

Fig. 4. Quick phase-locking approach.

clock signal and the reference clock signal. It generates two mutually
exclusive signals: lead and lag to show whose edge is leading. Since
the bandwidth of the DCO is quite large, the frequency detector is to
compare the divided clock with the reference clock so as to make the
frequency of DCO gradually approach the target frequency. Once the
frequency of DCO has been tuned as close as possible to the target frequency, signal frequency_lock is asserted and the phase-locking process
begins. The controller performs a phase-locking algorithm, mimicking
the function of loop filter in an analog PLL. In a number of reference
clock cycles, the control code will gradually converge to a small range,
indicating that the phase has also been locked to the reference clock
and the target frequency has been synthesized.
B. Digitally Controlled Oscillator
The DCO architecture we use in this design follows the one discussed in [12]. The fine-tuning delay cell comprises an array of tunable
metaloxidesemiconductor (MOS) capacitance, resulting in a highresolution, uniform, and monotonic delay profile of DCO. Such properties are contributive to the frequency detection and phase locking and
simplify the design of the digital loop filter. The average resolution of
one coarse step and one fine step is summarized in Table I. It is notable
that the delay range of the fine-tuning delay cell can always cover a

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Fig. 5. Operation flow of the suppressive filter.

TABLE I
MEASURED CHARACTERISTICS OF THE DCO

coarse-tuning step even after manufacturing so that the DCO does not
have any uncovered region within the supported frequency range.
C. Phase Detector
We adopt the sense-amplifier-based PD proposed in [12] since it can
almost eliminate the dead zone, (which is the minute range of phase
difference a PD cannot properly react). The phase polarity of two input
clocks is sent to both frequency detector and phase-locking controller.
Experimental results show that the performance will not be affected
even when there is severe process variation.
III. LOCKING PROCEDURE OF THE ADPLL
The locking procedure is the most contributive part in this work as
compared to previous ADPLL designs. It is composed of four steps
shown as Fig. 2. In step 1, the frequency tuning range of DCO should be
narrowed down to the proximity of the target frequency so as to facilitate the subsequent phase locking. This is achieved by tuning the coarse
control code of DCO under the guidance of the frequency detector. In
step 2, we start the preliminary phase locking with the reference clock.
The phase will be locked quickly but roughly, implying that the jitter
could still be large. Next, a suppressive digital filter is adopted in step
3 to further reduce the jitter. Finally, an interpolation-based locking algorithm is used to make the phase error as small as possible. In the
following sections, we will introduce the detail of each step. In the sequel, the reference clock signal in our ADPLL is denoted as ref_clk,
and the divided clock signal is denoted as div_clk. We will mention
these two signals frequently in the rest of our discussion.
A. Frequency Detector
Since the initial frequency of the DCO could be far from the target
frequency, we should draw it to closer to the target one first. This is
done by a binary search process to select an adequate coarse control
code so that the phase locking in the following steps can be achieved by

tuning fine control code only. In the frequency detector, the most critical operation is the frequency comparisonan operation that checks if
ref_clk or div_clk has a higher frequency. The one with a larger number
of edges within a preset period is assumed to have a higher frequency.
Since the accuracy of the edge counting is limited to the setup/hold
time constraint of a flip-flop, we further use the information derived
by our 1-ps-resolution PD to achieve a higher accuracy [12]. The frequency_lock signal will be triggered once the binary search process is
completed. In other words, we have found the two neighboring coarse
control codes surrounding the target frequency. Therefore, the delay
difference between the current clock period and the target one is within
the delay of one coarse step, said about 230 ps by the measurement results in TSMC18 process.
B. Preliminary Phase-Locking Scheme
Before starting phase locking, the DCO is reset first to align the phase
of div_clk with the ref_clk. Fig. 3 shows an example relationship between the phase error (which relates to the amount of time difference
between the two rising edges of signals div_clk and ref_clk) and the
control code. It is notable that if div_clk leads ref_clk, then the phase
error polarity is defined as positive. Under such a condition, the DCOs
frequency will be decreased until the phase error eventually becomes
negative. Very often, the frequency of the DCO is now underestimated
and another cycle of catching up is started. In that cycle, the DCOs
frequency is increased gradually until the phase error turns positive
again. If such an oscillation pattern appears, we can say that the phase
of div_clk is locked to that of ref_clk at least roughly. It can be seen
from the illustration that the target frequency is approximately located
at the middle value of the maximal and minimal control codes.
In light of the previous observation, we can quicken the
phase-locking process by a forward prediction on the control code.
The idea is that the maximal and minimal control codes always occur
when the polarity changes. To take advantage of this phenomenon,
we record one previous control code at all times. Whenever there is a
polarity change, the next control code will be set to be the average of
the current control code and the previous recorded one. Fig. 4 shows
an example, the phase polarity changes at point B so that the next
control code, which is #3, will be set to the average of current control
code, which is #2, and the previous recorded control code, which is
#1. The recorded control code is then updated as the control code #3.
As we can see, the phase is quickly locked and the fluctuations of
the phase error and the control code are limited to a narrower range,
implying that the resulting ADPLL would have a lower jitter. Then we

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Fig. 7. Block diagram of frequency interpolation scheme.

Fig. 6. Concept of frequency interpolation.

stop preliminary phase locking to avoid adding extra cycle-to-cycle

jitter.
C. Jitter Reduction By a Suppressive Filter
After the preliminary phase-locking step, the sensitivity of the loop
filter can be lowered to reduce the jitter of the output clock. In other
words, we do not need to tune the control code every ref_clk cycle but
only tune it in some situations instead. This is done by a so-called suppressive digital loop filter. As the name suggests, the aim of the digital
filter is to further suppress the magnitude of the control code range
after the preliminary phase locking. The operation flow is depicted as
Fig. 5. We use a counting signal, named peat in the figure, to record the
number of successive lead signal or the number of successive lag signal
produced by the PD when the phase polarity is unchanged. The control code will be changed only in two situations. One is when polarity
changes in two successive phase comparisons, i.e., either from lead to
lag, or vice versa, then the control code changes and the threshold resets to a preset value. The other is when the counter value is larger than
the threshold. Then we take two actions whenever the counter value
exceeds the threshold value: 1) we reset the counter value, and 2) we
double the threshold value. In the other situations, we do nothing to our
control code. In this way, the ADPLL is more stable and will not overreact to spontaneous noise. After the control code has been limited to
within a certain range, we will stop the suppressive filtering process and
start the phase error reduction by the frequency interpolation scheme.
D. Phase Error Reduction By Frequency Interpolation
In general, the ADPLL performs one phase comparison at each rising
edge of ref_clk and the control code is adjusted accordingly. When the
divided number is larger, too many cycles of dco_clk (i.e., the clock
signal at the DCOs output) may have elapsed between two phase comparisons, thus leading to a large tracking jitter due to phase error accumulation. To alleviate this problem, we need a DCO with an even
higher resolution. We discovered that this can be achieved by a frequency-interpolation scheme, by which the DCO could produce almost
any frequency within its output range, or, in some sense, it can possess
an almost continuous frequency profile like an analog DCO.
The concept is depicted in Fig. 6, assuming that and +1 are two
successive fine control codes and the delay difference between them is
regarded as the original minimum resolution of the DCO. Our scheme
creates some virtual frequencies between the two frequencies defined
and
+ 1. In this exby the two successive fine control codes
ample, we aim to create 15 virtual frequency points. Effectively, the
resolution of the DCO will be improved by 16 times. These virtual frequency points are realized by allowing the DCO to operate alternatively
between the frequency points defined by and + 1. For example,
assume that the frequency of dco_clk is denoted as fN when the control code to the DCO is N , and fN +1 when the control code is N + 1.
If we wish to generate a clock with frequency of 0:5 3 (fN + fN +1 ),
then we can simply alternate the control codes between N and N + 1.
The above discussion can be further generalized to derive the formula
of the frequencies of the 15 virtual frequency points. Let us denote the
index of these virtual frequency points as , ranging from 1 to 15 (from

Fig. 8. Simulation results of the phase error after locked.

Fig. 9. Die photo of the test chip.

the frequency point N towards the frequency point N + 1) as shown

in Fig. 6. Then, we can infer the following formula for a virtual frequency:


3 fN + 1 0
3 fN +1 :
f =

16

16

For example, if  equals 3, then it becomes

f=3

= 163

3 fN

+ 13
16

3 fN +1 :

It means that in 3 out of 16 occurrences, the control code of the DCO

should be set to N , while it should be set to N + 1 for the rest 13
occurrences. In other words, by changing the probability of the control
code, we can realize each desired virtual frequency.
The hardware used to implement the above formula is not expensive.
Fig. 7 shows the block diagram. To generate a virtual frequency, we
simply take its corresponding alpha value as a threshold. For each clock
cycle of dco_clk, we toss a random number in [0; 15] by a modified
simple linear feedback shift register (LFSR). If the random number is
larger or equal to the target alpha value, then we set the fine control
code to N . Otherwise, we set the fine control code to N + 1.
By frequency interpolation, we are now able to produce a dco_clk
with the frequency even closer to a desired frequency so that the phase
error can be reduced. Still, this technique needs to be applied inside the
phase-locking scheme. The suppressive filtering technique used in step
3 can be applied again. Instead of adjusting the fine control code as we
did in step 3, we now adjust the alpha value after each phase comparison. Since alpha value is an even finer adjustment than the fine control
code, the phase error as well as the jitter can be reduced furthermore.

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TABLE II
PERFORMANCE COMPARISON

IV. EXPERIMENTAL RESULTS

In order to setup the experimental environment of the proposed
ADPLL, the PD and DCO are precharacterized by postlayout transistor-level simulation to their abstract models. Then, we simulate our
ADPLL using postlayout gate-level simulation to save the simulation
time in the design phase. After the design phase is completed, we
verify the whole circuit and derive the characteristics from quick
SPICE simulation using NanoSim.
Fig. 8 shows the simulated phase error after phase locking of three
different configurations. In this simulation, the reference clock is an
ideal clock source without jitter. The one without frequency interpolation, i.e., the one skipping step 4 in our locking procedure, is selected
as the baseline approach for comparison. As we have mentioned, the
number of virtual frequency points created influences the effective resolution. In the other two configurations, we create 3 and 15 frequency
points, respectively, so that the DCOs resolution is thereby improved
to 1/4 and 1/16 of original one equivalently. It can be seen that the phase
error can be reduced further. Generally speaking, the more the virtual
frequency points are created, the smaller the phase error becomes. In
this case, where reference clock is 1 MHz and the multiplicative factor
is 128, the magnitude of the phase error can be substantially reduced
from 558 ps to only 21 ps in the 1/16 resolution configuration.
The test chip has been fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-m CMOS technology. Fig. 9 shows
the die photo.
Fig. 10(a) shows the waveform of ref_clk and div_clk after the phase
is locked where the reference clock frequency is 1 MHz and the multiplicative factor N is 600. The div_clk is perfectly locked to the ref_clk
in phase where the 180 phase difference is because div_clk is inverted
when passing through the output pad. Fig. 10(b) shows the jitter performance of the ADPLL. In this case, the interpolation-based locking
scheme is adopted to enhance the DCOs resolution by 16 times. The
jitterPk-Pk and the jitterRMS of the ADPLL are 56 and 7.28 ps, which
are only 3.36% and 0.43%, respectively, of the output clock period.
We compare the jitter performance with that of the free-running DCO
operated at 600 MHz. Measurement results show that jitterPk-Pk and
jitterRMS of the free-running DCO are 56 and 7.06 ps, respectively.
This indicates that our jitter performance is very close to that of a
free-running DCO, which can be regarded as the lowest jitter one could
possibly achieve.

Fig. 10. (a) Phase alignment after phase locked. (b) Jitter measurement of the
ADPLL (@600 MHz).

Fig. 11. Jitter performance under different output frequencies (reference clock
frequency fixed at 1 MHz).

Measurement results of jitter performance under different output frequencies are presented in Fig. 11. The reference clock frequency is
fixed and the output frequency is changed by tuning the multiplicative number N . It is found that the interpolation-based locking scheme
can not only reduce the phase error but also further reduce the jitter.
The jitterPk-Pk and the jitterRMS of ADPLL are 72 and 10.1 ps at
100 MHz and 68 and 8.81 ps, respectively, in our free-running DCO.
The jitterRMS is small than 0.44%UI even when the output frequency
varies from 100 to 600 MHz, indicating that the ADPLL can achieve
low-jitter performance all over its operation range. Experimental results reveal that the jitter of our ADPLL is very close to that of free
running DCO no matter what output frequency is synthesized.
Table II shows the characteristics of our ADPLL and its comparison with some previous works. All of them can provide a wide range

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of multiplicative numbers for frequency multiplication or clock generation. Measurement results show that our ADPLL can correctly function under varying input reference clock frequencies and multiplicative
numbers. In general, our measured jitter is comparable to the analog
PLL and clearly outperforms the previous ADPLLs.
V. CONCLUSION
ADPLL has been regarded inferior to its analog counterpart from
the performance point of view. More recently, ADPLL design has progressed significantly. However, problems such as inadequate DCOs
resolution and large jitter remain to be solved. In this brief, we presented an ADPLL with an ultralow-jitter characteristic. There are three
major contributions we made in this paper. 1) We use a predictive
scheme to expedite the preliminary phase-locking procedure. 2) We
further successfully reduce the jitter amount by a simple and inexpensive suppressive digital loop filter, which incorporates only counting
and thresholding to reduce the sensitivity of a PLL during the second
phase-locking stage. 3) We propose to use frequency interpolation to
virtually improve the resolution of a DCO beyond its physical limitation. Better jitter performance and phase error can thus be achieved.
Measurement results of a test chip show that the root mean square
(RMS) jitter is less then 0.44%UI when the output clock frequency
varies from 100 to 600 MHz. Operated at 600 MHz, the jitter is only
7.28 ps, which is only 3% away from that of the free-running DCO
(7.06 ps).

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