SRI RAMAKRISHNA INSTITUTE OF TECHNOLOGY

COIMBATORE-10
(Approved by AICTE, New Delhi & Affiliated to Anna University)
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

Course Code
& Title
CS2071 & COMPUTER ARCHITECTURE
L P T C
3 0 0 3



Class

FOURTH Year EEE Semester 07
Regulation
R 2008 (Academic year 2014-15)

Course
Prerequisite

Basic computer knowledge
Microprocessor & microcontrollers

Course
Outcomes


CO1: Students will understand the basic structure and instruction set, procedures of a
digital computer.

CO2: Students will understand in detail the operation of the arithmetic unit including
the algorithms & implementation of fixed-point and floating-point addition, subtraction,
multiplication & division.

CO3: Students will understand in detail the steps in instruction execution, control
synthesis and the concept of pipelining.

CO4: Students will understand the hierarchical memory system concepts, cache
memories and virtual memory, paging.

CO5: Students will understand the different ways of communicating with I/O devices
and standard I/O interfaces.

Programme
Outcomes

.
PO1: An ability to apply knowledge of Mathematics, Science and Engineering.

PO2: An ability to design and conduct experiments as well as to analyze and interpret
data.

PO4: An ability to function on multidisciplinary teams

PO5: An ability to identify, formulate and solve engineering problems.

PO10: An ability to use the techniques, skills and modern engineering tools necessary
for engineering practice


Relationship
of course to
programme
Educational
objectives

PEO1: To excel in professional career and/or higher education by acquiring knowledge
in mathematical, scientific and engineering principles.

PEO2: To analyze real life problems, design electrical systems appropriate to its
solutions that are technically sound, economically feasible and socially acceptable.


References


TEXT BOOKS:
1. B. Parhami, Computer Architecture, Oxford University Press, 2005.
2. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, Computer Organization, Fifth
Edition, Tata McGraw Hill, 2002.

REFERENCES:
1. David A. Patterson and John L. Hennessy, Computer Organization and Design:
The Hardware/Software interface, Third Edition, Elsevier, 2004.
2. William Stallings, Computer Organization and Architecture Designing for
Performance, Seventh Edition, Pearson Education, 2006.
3. Miles Murdocca Computers Architecture and Organization An Integrated approach,
Wiley India pvt Ltd, 2007
4. John D. Carpinelli, Computer systems organization and Architecture,
Pearson Education, 2001.

Mode of
Evaluation


1. Internal Assessment (20)
Internal Assessment Test 1 will be conducted for 50 Marks.
(5*2=10 & 2*20=40)
Internal Assessment Test 2 will be conducted for 50 Marks.
(5*2=10 & 2*20=40)
Internal Assessment Test 3 will be conducted for 50 Marks.
(5*2=10 & 2*20=40)
Internal Test Performance is considered for assessment out of 15.
Course Attendance
Assessment out of 5
(Attendance percentage
96-100: 5; 91-95: 4; 86-90: 3; 81-85: 2; 76-80: 1)
2. External Assessment (80)

University will conduct end semester examination for 100 marks (10*2=20 &
5*16=80)
Performance will be considered for assessment out of 80.

Course
Instructor

R.N.DEVENDRA KUMAR, AP/CSE




COURSE PLAN - I

Unit Topics to be covered as per curriculum Reference Period
I
UNIT I INSTRUCTION SET ARCHITECTURE
Introduction to computer architecture T1 2
Review of digital design T1 1
Instructions and addressing ,procedures and data
T1 3
Assembly language programs , instruction set variations T1 3
Total Hours: 9
II
UNIT II ARITHMETIC/LOGIC UNIT
Number representation

T1 2
Design of adders T1 2
Design of simple ALUs T1 2
Design of Multipliers and dividers
T1 1
Design of floating point arithmetic unit T1 2
Total Hours: 9
III
UNIT III DATA PATH AND CONTROL
Instruction execution steps T1 2
Control unit synthesis T1 2
Microprogramming pipelining T1 3
Pipeline performance
T1 2
Total Hours: 9
IV
UNIT IV MEMORY SYSTEM
Main Memory concepts T1 1
Types of memory T1 2
Cache memory organization T1 2
Secondary storage T1 2
Virtual memory paging T1 2
Total Hours: 9
V
UNIT V I/O AND INTERFACES
I/O devices, I/O programming T1 2
Polling interrupts DMA T1 3
Buses links interfacing T1 2
Context switching threads and multithreading
T1 2
Total Hours: 9
Total Hours: 60 Hours (Theory 45 Hours + Tutorial 15 Hours)



Course Instructor HOD/EEE PRINCIPAL
Bridging the Curriculum Gap
Processor families, Hazards & Memory.
Description
Overview of embedded processor families
Handling Data hazards & Control hazards.
Measuring and improving cache performance