UNIT -1 VLSI DESIGN METHODOLOGIES

1. What are the entities to be optimized in VLSI?

Area, power dissipation, speed, design time, Testability.

2. Define Hierarchy.
Hierarchy shows the structure of a design at different levels of description.

3. What are the analysis tools?
Analysis tools are the tools which provide data on the quality of the design
and hints to optimize the design

4. What are the optimization tools?
Optimization tools are the tools used to improve the quality of a design
without necessarily making a transition to other level of abstraction.

5. What is mean by Computational complexity?
Computational complexity refers to the time and memory required by a
certain algorithm as function of the size of the algorithms input.

6. What are the types of Computational complexity?
There are two types of Computational complexity,
Time complexity: which is a measure for the time necessary to accomplish a
computation.
Space complexity : is a measure of amount of memory required for
computation .
7. What is mean by Tractable and intractable problems?
A problem that can be solved in polynomial time is called Tractable
problem.
A problem that cant be solved in polynomial time is called Intractable
problems.
8. What is mean by Hardware & software co simulation?
A simulator that is able to cope simultaneously with descriptions of
hardware and software.

9. What is mean by Integer Linear programming?
It is a specific way of casting a combinatorial optimization problem in a
mathematical format.

10. What is mean by Dynamic programming?
It is a technique that systematically constructs the optimal solution of some
problem instance by defining the optimal solution in terms of optimal
solution of smaller size instances.















UNIT-2 DESIGN RULES
1. Define Layout compaction?
An optimization technique that can be used to remove redundant space is
called Layout compaction.

2. What is mean by Design rules?
The mask patterns that are used for the fabrication in an integrated circuit
have to obey certain restrictions on their shapes and sizes. These restrictions
are called design rules

3. What are the most common types of Design rules?
a. Minimum width
b. Minimum Separation
c. Minimum overlap.

4. What is mean by Placement Problem?
The Placement Problem is used to determine the location of the symbolic
layout on the chip such that the total resulting chip area is minimal.

5. What is mean by Partioning Problem?
Partioning Problem deals with splitting a network into two or more parts by
cutting connections.

6. What are the types of placement problem?
There are two types, they are Standard cell placement and building block
placement problem

7. What are the various wire length estimation techniques available ?
a.Half perimeter
b.Minimum rectilinear steiner tree
c.Aquared Euclidean distance

8. What are the types of placement algorithms ?
a.Constructive placement
b.Iterative placement

9. What is mean by min-cut placement?
min-cut placement is a top-down method: one starts with the whole circuit
and ends with small sub circuits
10. What is mean by a shape function?
The minimal height given as a function of its width is called shape function.
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UNIT-3 FLOOR PLANNING
1. What are the optimization problems in floor planning ?
a. Mapping of a Structural description to a floorplan
b. Floorplan sizing
c. Generation of flexible cells.

2. What is mean by Functions break point?
A piecewise linear function is characterized by a portioning of its input
domain into intervals and a distinct linear behavior in each of these intervals
the points delimiting the intervals are called Functions break point.

3. What are the steps in Sizing algorithm?
a. Construct the shape function of the top-most composite cell in a bottom
up fashion starting with the lowest level and combining shape functions
while moving upwards.
b. Choose the optimal shape of the top-level cell.
c. Propagate the consequences of the choice for the optimal shape down the
slicing tree until the shapes of all the leaf cells are fixed.

4. What is mean by Routing problem?
Given a placement, and a fixed number of metal layers, find a valid pattern
of horizontal and vertical wires that connect the terminals of the nets
5. What are the levels of routing?
Levels of abstraction:
i. Global routing or loose routing: it determines through which
wiring channels a connection will run
ii. Detailed routing or local routing : fixes the precise path that a
wire will take

6. What are the objectives of routing?
Cost components:
i. Area (channel width) min congestion
ii. Wire delays timing minimization
iii. Number of layers (fewer layers less expensive)
iv. Additional cost components: number of bends, vias

7. What is mean by Area routing?
Routing problems in which terminals are allowed anywhere in the area
available for routing are normally classified as Area routing .

8. What are the three steps in area routing?
a. Wave propagation,
b. Backtracking,
c. Clean up
9. What are the types of local routing problems?
a. Area routing
b. Channel routing

10. What is mean by Channel routing ?
a channel-routing problem by specifying two lists of nets: one for the top
edge of the channel and one for the bottom edge. The position of the net
number in the list gives the column position.

11. What are the objectives of channel routing?
The main objectives :
1.minimize the height
2.minimize total wire length and number of vias

12. What is mean by vertical constraint graph ?
In any solution of the problem, the endpoint of the segment coming from the
top has to finish at a higher position than the endpoint of the bottom segment
(otherwise there would be a short ckt).This restriction is called vertical
constraint graph.

13. What is mean by The Left-Edge Algorithm?
Step 1: Build the Vertical Constraint Graph (VCG) for the input channel
routing problem
Step 2: Place horizontal segments (choose nets (1) that do not have
ancestors in the VCG and (2) whose horizontal segments do not overlap) and
update the VCG
Step 3: Repeat Step 2 until all the horizontal segments have been placed































UNIT-IV SIMULATION
1. What is mean by simulation?
Simulation is used for the purpose of design verification, as it is extremely
costly to repair design errors after the fabrication of the IC, so simulation is
performed before fabrication.

2. What are the various abstract levels of simulation ?
a) Device level simulation
b) Circuit level simulation
c) Timing level level simulation
d) Switch level simulation
e) Gate level simualtion
f) Register level simulation
g) System level simulation

3. What are the software modules in a Simulator?
a) Simulator kernel
b) The processing of input description
c) The processing of the stimuli
d) The presentation of results

4. What is mean by gate level modeling?
gate mainly refers to elements to be found in a component library
NAND, NOR, MULTIPLEXER, D-FLIPFLOP, LATCH.
Signal modelling : Signal values are, of course, discrete. The
minimum set consists of 0, 1 and Z. Z means unknown.
Function modelling : Logic function of small sub-circuits (nand, nor,
invert).

5. What is mean by signal modeling ?
Discrete Signal values
Gate models should deal with multiple-valued logic.
Gate behavior can be represented by truth tables or compiled code.

6. What is mean by Delay modeling ?
inertial delay: a change to an input signal has to last at least a certain
time before it can trigger any reaction.
propagation (or transport) delay: some time passes between the start
of a signal change at the gate input and the start of a signal change at
its output.
rise/fall delay: due to capacitances that have to be loaded or unloaded,
there is a time difference between the moment an output starts to
change and the moment the output has reached its final value

7. What is mean by Compiler driven simulation?
A simulator that executes a compiled code model (e.g. RTL) is
referred to as a compiler-code simulator.
Based on making an executable-code model of circuit;
Efficient simulation mechanism (few machine instructions per gate);
Applicable to few delay models in synchronous circuits

8. What is Main flow of Event driven simulation?




9. What is mean by switch level modeling?
There are two types of nets:
storage nets: they have a capacitance value; often the set of values is
discrete.
input nets: they act as sources of fixed value and can supply unlimited
current.

10. What is mean by logic synthesis?
Process of converting a high-level description of the design into an
optimized gate-level representation given a standard-cell library and certain
design constraints.

11. What are the categories of LOGIC Synthesis?
Two level combinational LOGIC Synthesis
Multilevel combinational LOGIC Synthesis
Sequential LOGIC Synthesis

12. What are the Design Goals of LOGIC Synthesis?
a) Minimize number of levels (delay)
b) Minimize number of gates (area)
c) Minimize signal activity (power)

13. What is mean by CUBE?
A cube is a product of the input variables or their negations.








UNIT V MODELLING AND SYNTHESIS
1. What is mean by High-Level Synthesis ?
The process of mapping a behavioral description at the algorithmic level to
a structural description in terms of functional units, memory elements and
inter connections .

2. What is mean by Layout Synthesis ?
The process of mapping a structural description to a Physical description

3. What are The Hardware Models For High-Level Synthesis ?
a) functional units: they can perform one or more computations, e.g.
addition, multiplication, comparison, ALU
b) registers: they store inputs, intermediate results and outputs;
sometimes several registers are taken together to form a register file.
c) multiplexers: from several inputs, one is passed to the output.
d) busses: a connection shared between several hardware elements, such
that only one element can write data at a specific time.
e) Three-state (tri-state buffer) drivers control the exclusive writing on
the bus.
4. How hardware models are partitioned?
Hardware is normally partitioned into two parts:
The Data Path: a network of functional units, registers, multiplexers and
buses. The actual computation takes place in the data path.
Control: the part of the hardware that takes care of having the data present
at the right place at a specific time, of presenting the right instructions to a
programmable unit, etc.

5. Draw the conditional Data Flow Graph ?

6. What are the High level transformations?
a) Scheduling
b) Allocation
c) Assignment
7. What is mean by Scheduling?
To determine for each operation the time at which it should be performed
such that no precedence constraint is violated

8. What is mean by Allocation?
To specify the hardware resources that will be necessary.

9. What is mean by Assignment?
To provide a mapping from each operation to a specific functional unit and
from each variable to a register.

10. What are the types of Scheduling ?
Without resource constraint
a. Unconstrained Scheduling: ASAP
b. Latency-constrained scheduling :ALAP
c. Scheduling under timing constraint
With resource constraint
- List scheduling, force-directed scheduling.

11. What is mean by ASAP Scheduling Algorithm?
As Soon as Possible scheduling
a. Unconstrained minimum latency scheduling
b. Uses topological sorting of the sequencing graph (polynomial time)
c. Gives optimum solution to scheduling problem
d. Schedule first the first node n
o
T1 until last node n
v
is scheduled
e. C
i
= completion time (delay) of predecessor i of node j

12. What is mean by ALAP Scheduling Algorithm?
As late as Possible scheduling
a. Latency-constrained scheduling (latency is fixed)
b. Uses reversed topological sorting of the sequencing graph
c. If over-constrained (latency too small), solution may not exist
d. Schedule first the last node n
v
T, until first node n
0
is scheduled
e. C
i
= completion time (delay) of predecessor i of node j

13. What is mean by Force-Directed Scheduling?
The Force-Directed Scheduling algorithm consists of 3 steps:
a. Determine a time frame of each operation
b. Create a distribution graph
c. Calculate the force (a new metric

14. What are the advantages of Force-Directed Scheduling?
The Force-Directed Scheduling approach reduces the amount of:
a. Functional Units
b. Registers
c. Interconnect
This is achieved by balancing the concurrency of operations to ensure a high
utilization of each unit.