Review of Microelectronics&

Introduction to MOS technology

Moore's first law: Transistors Integrated on a single chip
(commercial products).
Moores Law
Intel co-founder Gordon Moore is a visionary.
His bold prediction, popularly known as Moore's Law, states
that the number of transistors on a chip will double
approximately every two years.
Intel, uses this golden rule as both a guiding principle and a
springboard for technological advancement, driving the
expansion of functions on a chip at a lower cost per function
and lower power per transistor, by shrinking feature sizes
while introducing new materials and transistor structures.
The announcement of the historic Intel 22nm 3-D tri-gate
transistor technology assures us that the promise of Moores
Law will continue to be fulfilled.
Tri-Gate Transistor
Tri-gate transistor, in which the transistor channel is
raised into the 3rd dimension.
Current flow is controlled on 3 sides of the channel
(top, left and right) rather than just from the top, as in
conventional, planar transistors.
The net result is much better control of the transistor,
maximizing current flow (for best performance) when
it is on, and minimizing it (reducing leakage) when it is
off.
FUN FACTS: EXACTLY HOW SMALL (AND COOL) IS 22
NANOMETERS?
The original transistor built by Bell Labs in 1947 was large
enough that it was pieced together by hand. By contrast, more
than 100 million 22nm tri-gate transistors could fit onto
the head of a pin.
More than 6 million 22nm tri-gate transistors could fit in the
period at the end of this sentence.
A 22nm tri-gate transistors gates that are so small, you could
fit more than 4000 of them across the width of a human hair.
If a typical house shrunk as transistors have, you would not be
able to see a house without a microscope. To see a 22nm
feature with the naked eye, you would have to enlarge a chip
to be larger than a house.
Cont
Compared to Intels first microprocessor, the
4004, introduced in 1971, a 22nm CPU runs
over 4000 times as fast and each transistor
uses about 5000 times less energy. The price
per transistor has dropped by a factor of about
50,000.
A 22nm transistor can switch on and off well
over 100 billion times in one second. It would
take you around 2000 years to flick a light
switch on and off that many times
Digital IC technologies and logic-circuit families.
Comparison of BJT and CMOS
Technology
Speed/power performance of available
technologies.
Speed Power Product: Product of Gate switching delay in nanoseconds and gate
power dissipation in mW
Microelectronics evolution
nMOS enhancement mode transistor
nMOS depletion mode transistor
pMOS enhancement mode transistor
Drain to source Voltage Zero
Non-Saturated
Saturated
Transistor Symbols
nMOS Fabrication Process
Cont
Cont
Summary of nMOS Process
Processing takes place on a p-doped silicon crystal wafer on which is grown a
'thick layer of Si02.
Mask 1-Pattern Si02 to expose the silicon surface in areas where paths in the
diffusion layer or gate areas of transistors are required. Deposit thin oxide over
all For this reason, this mask is often known as the 'thinox' mask but some
texts refer to it as the diffusion mask.
Mask 2-Pattern the ion implantation within the thinox region where depletion
mode devices are to be produced-self-aligning.
Mask 3-Deposit poly silicon over all (I _5 Jlm thick typically), then pattern using
Mask 3. Using the same mask, remove thin oxide layer where it is not covered
by polysilicon.
Diffuse n + regions into areas where thin oxide has been removed. Transistor
drains and sources are thus self-aligning with respect to the gate structure&.
Mask 4--Grow thick oxide over all and then etch for contact cuts.
Mask 5-Deposit metal and pattern with Mask 5!
Mask 6-Would be required for the overglassing process step.
CMOS Fabrication-P well Process
Cont
n-well process
n-well cmos inverter
BiCMOS-n-well
Cross Sectional View
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