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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 2, MARCH 2000

A Comprehensive Study of Neutral-Point

Voltage Balancing Problem in Three-Level
Neutral-Point-Clamped Voltage Source PWM
Inverters
Nikola Celanovic, Student Member, IEEE, and Dushan Boroyevich, Member, IEEE

AbstractThis paper explores the fundamental limitations of

neutral-point voltage balancing problem for different loading conditions of three-level voltage source inverters. A new model in DQ
coordinate frame utilizing current switching functions is developed
as a means to investigate theoretical limitations and to offer a more
intuitive insight into the problem. The low-frequency ripple of the
neutral point caused by certain loading conditions is reported and
quantified.
Index TermsNeutral-point voltage balancing, space vector
modulation, three-level converter.

I. INTRODUCTION

INCE its introduction in 1981 [1], the three-level neutralpoint-clamped (NPC) voltage source inverter (VSI), Fig. 1,
has been shown to provide significant advantages over the conventional two-level VSI for high-power applications.
The main advantages are as follows.
1) Voltage across the switches is only half the dc bus voltage.
This feature effectively doubles the power rating of VSIs
for a given power semiconductor device. Moreover, this
is achieved without additional, often cumbersome, hardware for voltage and current sharing.
2) The first group of voltage harmonics is centered around
twice the switching frequency [1], [7]. This feature enables further reduction in size, weight, and cost of passive
components while at the same time improving the quality
of output waveforms.
On the other hand this topology also has its disadvantages.
1) Three-level VSIs require a high number of devices.
2) The complexity of the controller is significantly increased.
3) The balance of the neutral-point has to be assured.
The three-level VSI was first considered with respect to highcapacity high-performance ac drive applications [1]. To this day,
it remains the area where this topology is most widely used
[2][4], [7][9], [15], and [16]. Other interesting applications of

Manuscript received March 10, 1999; revised September 22, 1999. Recommended by Associate Editor, F. Z. Peng.
The authors are with the Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA,
24061-0111 USA.
Publisher Item Identifier S 0885-8993(00)02327-9.

Fig. 1. Circuit schematic of a three-level VSI.

this technology include static VAR compensation systems [11],

[12], HVDC transmission systems [18], active filtering applications, as well as applications in power conditioning systems for
superconductive magnetic energy storage (SMES) [13].
The neutral-point (NP) voltage balancing problem of
three-level NPC VSIs has been widely recognized in literature. Various strategies have been presented, and successful
operation has been demonstrated with a dc-link voltage balance
maintained. In addition, some of the proposed algorithms avoid
the narrow pulse problem [5], [9], minimize losses by not
switching the highest current [10], or share the balancing task
with front-end converters as in [2].
NP control for the carrier-based PWM has been studied
in [15][17]. In [15], the switching frequency optimal PWM
method is introduced. This method controls the NP by, essentially, adding the zero sequence voltage to the inverter output.
This work was extended in [16], where the authors propose an
analytical method for analysis of the NP potential variation,
show some limitations of the NP control, and also deal with the
dc-link capacitors design issues. In [17], the authors analyze
the stability of the NP control based on an insightful dynamic
model of the NP control they developed.
This paper discusses the issues of NP control from the space
vector modulation (SVM) point of view. In addition, the broader
range of inverter operating conditions is addressed, and a new
mathematical formulation of NP balancing problem is given.
Furthermore, low-frequency NP voltage ripple, normalized with
the output current and the size of the dc-link capacitors, is given
for all operating conditions.

0885-8993/00$10.00 2000 IEEE

CELANOVIC AND BOROYEVICH: COMPREHENSIVE STUDY OF NEUTRAL-POINT VOLTAGE BALANCING PROBLEM

243

II. PRINCIPLE OF OPERATION

All available voltage space vectors for three-level VSIs are
shown in Fig. 2. These vectors, called switching-state vectors,
represent inverter output line voltages in two-dimensional ( ,
,
) plane, and are produced by switching different states
, or can
of the inverter, also shown in Fig. 2. Each phase
be connected to either the positive ( ), negative ( ), or neutral
( ) point of the dc link. Shown in Fig. 2, switching state pon,
and
for example, is producing line voltages
. In this case, the phase output is connected to the
neutral point, which results in the current disturbing the NP
voltage balance.
Not all the vectors affect the NP balance. The ones that do are
summarized in Table I. Large vectors do not affect the NP balance because they connect the phase currents to either the positive or negative dc rail, and the NP remains unaffected. Medium
vectors connect one of the phase currents to the NP making the
NP potential dependent in part on the loading conditions. They
are the most important source of the NP potential unbalance.
Small vectors come in pairs. Each vector in a pair generates
the same line-to-line voltages. A small vector that connects a
phase current to NP point without changing the sign of the current will be referred to as a positive small vector. The other
one, connecting the phase current with the negative sign, will be
called a negative small vector. The majority of the NP voltage
balancing schemes used in SVM relies on some form of manipulation of small vectors in a pair, where the relative duration of
positive and negative small vectors in a pair is usually adjusted
in order to compensate for the error in NP.

Fig. 2.

Switching state vectors of three-level VSI.

TABLE I
NEUTRAL POINT CURRENT i
DIFFERENT SPACE VECTORS

FOR

III. NEUTRAL POINT CURRENT MODULATION

Generally, the task of three-level VSIs is to synthesize the
desired output phase voltages , , , represented by the reference voltage space vector

(1)
where the modulation index is the ratio between the desired
, and the maximum
amplitude of the output phase voltages,
possible amplitude of undistorted sinusoidal phase voltages that
. In this paper, only the case
can be generated,
will be considered. Due to circular symmetry of the three-phase
, as
system, it is sufficient to consider only the case
shown in Fig. 3. The reference vector may be synthesized using
the space vector modulation (SVM) of the three switching state
vectors that are nearest to the reference vector at every sampling
instant. The nearest three vectors are selected by locating the
reference vector in one of the four small triangles illustrated in
Fig. 3.
For the outer small triangle shaded in Fig. 3, the reference
vector is synthesized as
(2)
(3)

Fig. 3. Synthesis of V

in outer small triangle region.

where
duty cycle of the small switching state vector;
duty cycle of the medium switching state vector;
duty cycle of the large switching state vector.
From (2) and (3), the duty cycles are
(4)
(5)
(6)
The NP current in outer small triangle has two components,
the noncontrollable component from the medium vector, and the
controllable component from the small vectors. The controllable
component of the NP current can be selected by adjusting the

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 2, MARCH 2000

relative duration of the positive (

) and negative ( ) small
. In further text, the relative duration of posivectors within
tive and negative small vectors will be called current modulation
.
index
(
) is
In other words, the duty cycle of the vector
, and the duty cycle of the vector
( ) is
. The NP-current can be found from Table I as
(7)
The expressions for the other outer small triangle (2)(7) are
symmetric. From (7) it is obvious that the NP current consists of
, from the application of
the noncontrollable component,
the medium switching vector, and the controllable component,
, from small voltage switching vector. Note that NP
current produced by the small vectors depends not only on the
, but also on the load current and small vector
control input
duty cycle. These additional constraints significantly limit the
control authority over the NP current in this small triangle region.
The middle small triangle region, shown in Fig. 4, is more
favorable for balancing the NP voltage since two small vectors
are available. The reference vector is synthesized in the region
as
(8)
(9)
(10)
(11)
(12)
The NP current for this small triangle is given by
(13)
and
are the NP-current modulation indexes for
where
,
, respectively. This is clearly a more
the small vectors
favorable situation compared with (7), since two small vectors
increase the control authority over the NP current.
The SVM in the inner triangle region shown in Fig. 5 is defined by
(14)
(15)

Fig. 4.

Synthesis of V

in middle small triangle region.

Fig. 5.

Synthesis of V

in inner small triangle.

IV. LOW FREQUENCY RIPPLE IN NEUTRAL POINT CURRENT

Steady-state low-frequency ripple in the NP-current is caused
by periodic variation of the components in (7), (13), and (18)
over the output voltage line cycle. In a steady state, the voltage
and
reference vector (1) has constant amplitude,
. As the refrotates with a constant angular speed,
sectors, the duty
erence vector sweeps through successive
,
,
, and
become periodic functions of time.
cycles
Due to the selected SVM strategy, these functions have discontinuous first derivatives at the boundaries of the small triangles
and waveshape dependent on the modulation index, , as shown
in Fig. 6.
Although the duty cycle functions in Fig. 6. are continuous,
they are the duty cycles of different switching state vectors
sectors. One way to represent how different
in different
switching state vectors, used in different sectors, affect the NP
current, is to introduce current switching functions. Current
switching functions define a mapping between the duty cycle
of the vectors, and the NP current that those vectors produce.
For example, using this representation the NP current produced
by medium vectors can be represented as
(19)

(16)
(17)
(18)
The inner small triangle region is the most advantageous for
the NP voltage balancing because only the small vectors, those
that allow full control of the NP current (18), are used. Unfortunately, in this region the dc-link voltage is poorly utilized, and
it is reasonable to expect inverter to operate in this region only
during startup and/or transients.

,
is the duty
It can be seen from Fig. 2. that for
,
cycle of the medium vector pon, and for
is the duty cycle of the medium vector opn. The contribution of
for
,
the medium vector to the NP current is
for
. Therefore, for
,
and
the neutral point current contribution from the medium vector is
. For
, the medium
. The full set of
vector NP current is
mapping functions for the medium vectors is given in Table II.

CELANOVIC AND BOROYEVICH: COMPREHENSIVE STUDY OF NEUTRAL-POINT VOLTAGE BALANCING PROBLEM

245

Fig. 6. Duty cycles of SVM for modulation index m = 0:8.

TABLE II
CURRENT SWITCHING FUNCTION FOR MEDIUM VECTORS

TABLE III
CURRENT SWITCHING FUNCTION FOR S SMALL VECTORS

TABLE IV
CURRENT SWITCHING FUNCTION FOR S SMALL VECTORS

By extending this reasoning to small vectors and all six

sectors a set of current switching functions can be defined for
small vectors as well. Small vectors switching functions are
shown in Tables III and IV. Finally, all these pieces can be combined into a single expression valid for the NP current over the
entire line cycle
a synchronously rotating, , reference frame. This can by
done by transforming the phase currents
(20)

In order to simplify the analysis of the NP current under different loading conditions, it is convenient to transform (20) into

(21)

where the -axis is aligned with the voltage reference vector,

. In a steady state,
and
are constant and represent

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 2, MARCH 2000

Fig. 7. Weighing factors for medium vectors for m = 0:8.

active and reactive components of the load current, respectively.

By substituting (21) into (20), the NP current can be expressed
as

(22)
where
, and so on.
Note that (22) is essentially the composite expression combining (7), (13), and (18) into one matrix equation valid over
the full line cycle of the output voltage. The NP current in this
formulation still consists of noncontrollable current produced
by the application of the medium vector, and the controllable
current produced by the small vectors.
NP current, resulting from application of medium vectors,
can be found by multiplying the direct current by the direct
, and the quadrature current , by the
weighing factor
quadrature weighing factor. These factors are given in Fig. 7,
. It is apparent
for the case when the modulation index
that quadrature component of the current will be weighed much
more heavily, and will produce much larger low-frequency (LF)
ripple than the direct component current.
Similarly, NP current resulting from application of small vectors depends on controllable direct and quadrature weighing
factors multiplying the direct, , and quadrature, , load cur.
rent. These factors are given in Fig. 8 for
These four weighing factors depend not only on small vectors duty cycles and the current switching functions that are determined by particular type of SVM used, but also on the conand
as defined earlier. Two distinct sets of
trol inputs
weighing factors are given in Fig. 8. One set of weighing factors
when only positive small vectors are used (i.e.,
) is indicated by a solid line. The other set of weighing factors
when only negative small vectors are used (i.e.,

) is indicated by a dashed line. Between these two extreme

cases the weighing factors can be controlled by adjusting current modulation indexes.
The weighing factors for medium vectors are periodic functions with zero average value over a line cycle. This means that
in the ideal steady-state case, and currents are constant and
the NP current from medium vectors naturally balances over a
line cycle. Finding the size of the LF ripple under these conditions will be used to help determine the size of the dc-link
capacitor for a given NP voltage ripple.
Note that the ratio of active and reactive weighing factors is
opposite for medium and small vectors. Large means large
control authority over the NP current through the manipulation of current modulation indexes of small vectors, and small
means small disturbance from middle vectors. On the other
hand, large means large disturbance from middle vectors, and
small means small control authority over NP from small vectors. This confirms the fact that it is much easier to suppress the
LF ripple in the NP when the load has a high power factor.
V. NP BALANCE CONTROL
There seems to be equivalence in the NP balance control
mechanism between carrier-based, and SVM-based PWM
schemes. For carrier-based PWM modulation, all the control
schemes appear to be based on the same concept: they all use
some form of manipulation of output zero sequence voltage.
Similarly, all the NP control schemes for SVM-based PWM
schemes appear to use some form of manipulation of the
redundant small vectors. Note that the difference between the
phase voltages of two small vectors in a pair is, in fact, the zero
sequence voltage. This seems to be another proof of the duality
of the two PWM methods.
Regarding NP balancing control for SVM, and with the restriction to NTV, three distinctive approaches to the control of
NP might be as follows.
1) Passive control, where the positive and negative small
vector is selected alternatively in each new switching

CELANOVIC AND BOROYEVICH: COMPREHENSIVE STUDY OF NEUTRAL-POINT VOLTAGE BALANCING PROBLEM

Fig. 8.

247

Weighing factors for small vectors for m = 0:8.

cycle. This method can work only in the case of perfectly

balanced load and perfectly balanced PWM scheme,
which is unlikely to happen in practice. This method
would have difficulties to recover from line or load
transients [15]. Still, this control method can be used
to establish a benchmark for NP controller performance.
This benchmark can then be used to evaluate the performance of other NP control methods.
2) Hysteresis type control is perhaps the simplest and most
popular closed loop NP control scheme. This method
requires the knowledge of the current direction in each
phase. Based on that information, the small vectors that
will move the NP voltage in the direction opposite from
the direction of unbalance can be selected. The downside
of this method is the current ripple at half the switching
frequency.
3) Active control schemes that control the current modulation indexes m and m . In general, these schemes require measurement of the voltage unbalance in the NP,
and often require measurement of the amplitudes of the
phase currents as well. The benefits of these schemes
is that they do not have the ripple at half the switching
frequency, and some variations of these control schemes
can balance the NP exactly. Unfortunately, they all in-

Fig. 9.

Region where LF ripple can be suppressed.

crease the switching losses due to introduction of additional switching states, and may be less robust than the
hysteresis type control schemes.

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Fig. 10.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 2, MARCH 2000

Normalized amplitude of the LF charge ripple.

The size of the dc-link capacitors required for given

NP voltage ripple and the amplitude of the phase current can be computed from (22). The essential parameter in this computation is the normalized charge ripple,
given in Fig. 10, for every
modulation index , and load power factor
(23)

Fig. 11.

Capacitor sizes for specified NP ripple with and without NP control.

From the analysis in the previous section, it should be obvious that, regardless of control scheme, the control authority
over the NP current is limited, and the region where exact balancing can be achieved in each switching cycle must exist. This
region is given as a shaded area in Fig. 9. Note that the graph is
symmetrical, and that the unity power factor load represents the
most favorable case. For that case, the NP voltage can be balanced in every switching cycle for a modulation index as high
.
as
If the converter happens to operate outside the shaded region,
LF ripple current flows into the NP, producing LF voltage ripple
in the NP. The size of that ripple is determined mostly by the size
of the dc-link capacitors, amplitude of the phase currents, and
the output power factor.
Peak-to-peak value of low frequency charge ripple in the NP
divided by the amplitude of output phase current is given in
Fig. 10. The first graph shows the normalized NP charge ripple
for the passive control of NP voltage balance. The second graph
shows the best that can be done using hysteretic and/or control
of current modulation indexes. The shaded region represents the
same ripple-free area as the one given in Fig. 9.

This should provide sufficient guidelines to size the dc link

capacitors for any expected operation mode and desired neutral
point voltage ripple value.
Consider an example with 1800 V dc-link voltage and
A, peak phase current, and allow 1% voltage ripple
V) in the NP. For modulation index
,
(
the comparison of capacitor sizes for the feedback NP control
and the case with passive NP control is summarized in Fig. 11.
The greatest savings in the size of capacitor can be achieved
when the inverter is predominantly supplying active power,
while for the operation with purely reactive power the benefits
of feedback NP control diminish.
VI. CONCLUSION
In this paper, NP balancing was investigated for all possible
operating conditions of a three-level VSI. A new and general
model in the DQ coordinate frame was introduced as a way to
investigate the theoretical and practical limitations of NP balancing problem regardless of the type of SVM used. Additionally, the low-frequency ripple of the neutral point voltage caused
by all possible loading conditions was reported and quantified.
Results presented in this study should clarify the tradeoffs between the size of the dc-link capacitor, size of the NP voltage
ripple, and the NP balancing method.

CELANOVIC AND BOROYEVICH: COMPREHENSIVE STUDY OF NEUTRAL-POINT VOLTAGE BALANCING PROBLEM

Based on the investigations reported in this paper and the results reported by other researchers, it can be concluded that the
NP balancing problem in three-level NPC VSI topology does
not limit the usefulness of this topology for practical applications. This problem can be solved in a satisfactory way using
various techniques, depending on the particular system, and its
operating point constraints.
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Nikola Celanovic (S95) received the B.S. degree

in electrical engineering from the University of
Novi Sad, Yugoslavia, in 1994, the M.S. degree in
mechanical engineering from Vanderbilt University,
Nashville, TN, in 1996, and is currently pursuing
the Ph.D. degree at the Virginia Polytechnic Institute
and State University (Virginia Tech), Blacksburg.
He is a Graduate Research Assistant with the
Center for Power Electronics Systems, Virginia
Tech. During the summer of 1999, he was a summer
intern with the General Electric CR&D Center,
Schenectady, NY, where he was working on modeling and control of multilevel
three-phase drive systems. His research interests include modeling, control
design, and applications of high-power, high-frequency power electronics
systems.

Dushan Boroyevich (M99) received the B.S. degree

from the University of Belgrade, Yugoslavia, in 1976,
the M.S. degree from the University of Novi Sad, Yugoslavia, in 1982, and the Ph.D. degree from the Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, in 1986.
From 1986 to 1990, he was an Assistant Professor
and Director of the Power and Industrial Electronics
Research Program, Institute for Power and Electronic Engineering, University of Novi Sad, and
later, Acting Head of the Institute. In 1990, he joined
the Bradley Department of Electrical and Computer Engineering, Virginia
Tech, as an Associate Professor. From 1996 to 1998, he was an Associate
Director with the Virginia Power Electronics Center, and since 1998, has
been the Deputy Director of the NSF Engineering Research Center for Power
Electronics Systems, where he is now a Full Professor. His research interests
include multiphase power conversion, high-power PWM converters, modeling
and control of power converters, applied digital control, and electrical drives.
He has published over 100 technical papers, has three patents, and has been
involved in numerous government and industry-sponsored projects in the areas
of power and industrial electronics.
Dr. Boroyevich is a member of the IEEE Power Electronics Society AdCom,
IEEE Industry Applications Society Industrial Power Converter Committees,
and Phi Kappa Phi.