CISC Processor Design

Performance Enhancement
Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org
Lecture 9
SE-273: Processor Design
Feb 8, 2008
SE-273@SERC 2
Per f or manc e
Enhanc ement
1. Reduce number of cycles
2. Reduce cycle time
3. Do more task in parallel
Fetch
Decode
Execution
Feb 8, 2008
SE-273@SERC 3
ADD I nst r uc t i on Ex ec ut i on
5A R1 B2
Displacement (D2)
ADD R1, D2(B2)
Feb 8, 2008
SE-273@SERC 4
Ex ec ut i on St eps
1. Fetch the remaining instruction word
2. Calculate the operand address
3. Fetch the operand
4. Add
5. Store the result
6. Update the program counter
7. Fetch the first half word for the next instruction
8. Find the address of the next instructions control word
sequence
9. Branch to the next instructions control word
Feb 8, 2008
SE-273@SERC 5
ADD I nst r uc t i on Ex ec ut i on
State Execution Unit Decoder External Bus
1. Read instruction half-word
2. ALU = D2 + (B2)
3. Read operand half-word
4. ALU = (DI) + (R1)
5. R1 = (ALU)
6. ALU = (PC) + 2
7. PC = (ALU)
8. Read instruction half-word
9. IR
Feb 8, 2008
SE-273@SERC 6
ADD I nst r uc t i on Ex ec ut i on
State Execution Unit Decoder External Bus
1. ALU = D2 + (B2) Read instruction half-word
2. Read operand half-word
3. ALU = (DI) + (R1)
4. R1 = (ALU)
5. ALU = (PC) + 2
6. PC = (ALU) IR Read instruction half-word
Feb 8, 2008
SE-273@SERC 7
MI N Dat apat h
AO PC T2 R0 R1 Rn T1 ALU
DO
DI
IRF IRE
k
Internal A Bus
Internal B Bus
External Address
Bus (EAB)
External Data
Bus (EDB)
Feb 8, 2008
SE-273@SERC 8
Fl ow c har t s - ADD
alu

t1
b2

a

alu
di

b

alu
alu

a

alu, ao
edb

irf
+2

alu
alu

*

ao
edb

di
t1

*

pc
ADD1
ADD2
ADD3
Increment PC
Read next instruction half word
The sum is stored in a register in ALU
Save the ALU (update PC)
B2 reg. to internal A bus to ALU
Displacement D2 from DI to B to ALU
The sum is stored in a register in ALU
Send the operand address to the pads
Read the operand into DI from pads
Save the updated PC
Feb 8, 2008
SE-273@SERC 9
Fl ow c har t s - ADD
di

a

alu
r1

b

alu
alu

*

r1
edb

di, irf
irf

ire
pc

*

alu, ao
+2

alu
ADD4
ADD5
Store the result
Read second instruction halfword
Decode the next instruction
Update PC & read instruction halfword
Add the operand
Feb 8, 2008
SE-273@SERC 10
I nt er nal Cl oc k i ng
Four phase clocking
P1 source register is gated to internal bus
P2 the signal on internal bus is amplified and
broadcast the length of bus
P3 the signal on internal bus is gated to the
destination
P4 the bus is returned to the neutral state
Feb 8, 2008
SE-273@SERC 11
I nt er nal Cl oc k i ng
The clocking on chip has to allow for delay from the
external bus
Add new clock phase P4 prime
Split cycle (2 internal state in one external bus
cycle)
Feb 8, 2008
SE-273@SERC 12
Fl ow c har t s - ADD
alu

t1
b2

a

alu
di

b

alu
edb

irf
alu

a

alu, ao
+2

alu
alu

*

ao
edb

di
t1

*

pc
ADD1
ADD2
ADD3
Increment PC/ initiate instr. read
The sum is stored in a register in ALU
Save the ALU (update PC)
B2 reg. to internal A bus to ALU
Displacement D2 from DI to B to ALU
Read next instr. from external bus
Send the operand address to the pads
Read the operand into DI from pads
Save the updated PC
Feb 8, 2008
SE-273@SERC 13
Fl ow c har t s
di

a

alu
t1

b

alu
alu

*

t1
edb

di, irf
irf

ire
pc

*

alu, ao
+2

alu
ADD4
ADD5
Store the result
Read second instruction half-word
Decode the next instruction
Update PC & read instr. half-word
Add the operand
The sum is stored in the ALU O/P reg.
Feb 8, 2008
SE-273@SERC 14
MI N Dat apat h
AO PC T2 R0 R1 Rn T1 ALU
DO
DI
IRF IRE
k
Internal A Bus
Internal B Bus
External Address
Bus (EAB)
External Data
Bus (EDB)
Feb 8, 2008
SE-273@SERC 15
Segment ed Bus
AO PC T2 R0 R1 Rn T1 ALU
DO
DI
IRF IRE
k
Internal A Bus
Internal B Bus
External Address
Bus (EAB)
External Data
Bus (EDB)
AP
AD
Feb 8, 2008
SE-273@SERC 16
Pr oc essor - Bl oc k Di agr am
Clock-Phase
Generator
Control Word Decoder
PC R0 R1 Rn Shifter ALU
Datapath
Data
Reg.
Address
Out Reg.
Internal A Bus
Internal B Bus
Control
Store
Next State
Control
IR
Decoder
IRD
Encoded Control Word Fields
Decoded Datapath Control
Branch Control
unit
Reset & Power-On Logic Interrupt Logic
Bus Controller
IRD IRD
Feb 8, 2008
SE-273@SERC 17
I nt er nal Ti mi ng
Control Store
Address latch
Control Store
(Half a micro-cycle)
State
Sequencer
Instruction
Decoder
(one micro-
cycle)
Control Word Latch
Control Word Decoders
(Half a micro-cycle)
Datapath Control Latch
Datapath
(One micro-cycle Phase 1 to 4)
IRD
IRE IRF
P1
P1
P3
P3
P4
P1
Feb 8, 2008
SE-273@SERC 18
Fl ow c har t s - ADD
alu

t1
b2

a

alu
di

b

alu
edb

irf
alu

a

alu, ao
+2

alu
alu

*

ao
edb

di
t1

*

pc
ADD1
ADD2
ADD3
Increment PC/ initiate instr. read
The sum is stored in a register in ALU
Save the ALU (update PC)
B2 reg. to internal A bus to ALU
Displacement D2 from DI to B to ALU
Read next instr. from external bus
Send the operand address to the pads
Read the operand into DI from pads
Save the updated PC
Feb 8, 2008
SE-273@SERC 19
Fl ow c har t s - ADD
di

ad

alu
pc

ap

ao
r1

b

alu
alu

*

r1
edb

di, irf
irf

ire
pc

*

alu
+2

alu
ADD4
ADD5
Store the result
Read second instruction half-word
Decode the next instruction
Update PC & read instr. half-word
Add the operand
Initiate read for next instr. half-word
The sum is stored in the ALU o/p reg.
Feb 8, 2008
SE-273@SERC 20
Pr oc essor Bl oc k Di agr am
IB
Datapath
Control
Store
Next
State
Control
Branch
Control
Instruction
Decoder
IRE
IRF
Control word
Decoders
Control Fields
(Static)
OP TY NA
SB
BC
DB
Condition
Codes
Control lines
Control Fields (dynamic)
Control Word
Register
Feb 8, 2008
SE-273@SERC 21
Thank You