DC-DC Switching Boost Converter

ABSTRACT
The switching power supply market is flourishing quickly in todays high-tech world. esign
engineers arent always supplied with the desired amount of !oltage they need in order to
make their design work. Adding an additional !oltage supply to a design is not always cost
efficient. This report is intended to pro!ide the designer with a method of "oosting C
!oltage from # $olts to %& $olts' "y using a C-C switching "oost con!erter designed
specifically for this task. All goals' design procedures' tests' data' conclusions' and costs ha!e
"een documented within this report. Results of e(periments show that the switching
con!erter will "oost !oltage from # !olts to %& !olts with power con!ersion efficiency of )*
percent.
ii
TAB+, -. C-/T,/TS
%. 0ntroduction 11111111111111111111111111111%
%.% 2urpose of the 2ro3ect.11111111111111111111111%
%.& Block iagram11111111111111111111111111%
%.* Specifications11111111111111111111111111..%
&. esign 2rocedures 1111..1111111111111111111111..&
&.% 4eneral Boost Con!erter Configuration1111111111111111.&
&.& Component .unctions11111111111111111111111.*
*. esign etails11111111111111111111111111111*
*.% etailed Circuit escription and .unction..111111111111111*
*.& Component Calculations111111111111111111111.15
*.* Simulation 2rocedure11111111111111111111111..6
5. esign $erification1111111111111111111111111116
5.% Test Setup 11111...11111111111111111111116
5.& esign 7odifications11..111111111111111111111)
5.* Test Results111111111111111111111111111.)
#. Costs11111111111111111111111111111111.%%
#.% 2arts Cost ,stimate111111111111111111111111%%
#.& +a"or Cost ,stimate11111111111111111111111..%%
6. Conclusions11111111111111111111111111111..%%
). Appendi( %8 ata Sheet for 7C**96*1111111111111111111%&
:. Appendi( &8 Simulation results111111111111111111111...%6
;. Appendi( *8 Complete schematic1..1111111111111111111..%:
%9. Appendi( 58 References...111111111111111111111111%;
iii
1. Introduction
1.1 Purpose of the Project
,fficiency' si<e' and cost are the primary ad!antages of switching power con!erters
when compared to linear con!erters. Switching power con!erter efficiencies can run
"etween )9-:9=' whereas linear con!erters are usually *9= efficient. The C-C
Switching Boost Con!erter is designed to pro!ide an efficient method of taking a
gi!en C !oltage supply and "oosting it to a desired !alue.
1.2 Block Diagra
The "asic "uilding "locks of a "oost con!erter circuit are shown in .ig. %.
.ig. % Block diagram
The !oltage source pro!ides the input C !oltage to the switch control' and to the
magnetic field storage element. The switch control directs the action of the
switching element' while the output rectifier and filter deli!er an accepta"le C
!oltage to the output.
1.! Specifications
esign engineers working in todays high tech en!ironment ha!e to deal with a
rapidly changing market of electronic products and components. As new technology
de!elops' integrated circuits function faster and are smaller in si<e. >owe!er' many
integrated circuits still require a !oltage of %& !olts in order to function. The C-C
$oltage
Source
7agnetic
.ield Storage
,lement
Switch
Control
Switching
,lement
-utput
Rectifier and
.ilter
%
Switching Boost Con!erter will take a # $olt C !oltage supply with %9 =
tolerance and deli!er %& $olts across the load. The ma(imum output ripple will "e
&= of the output !oltage' while the ma(imum current deli!ered to the load will "e
%99 mA. The circuit will operate with a minimum efficiency of )9=.
2. Design Procedures
2.1 "eneral Boost Converter Configuration
Se!eral different "oost con!erter designs ha!e "een de!eloped in the past. 0n order
to achie!e the results specified for this pro3ect' the output !oltage of the con!erter
?hen the transistor is conducting' current is "eing drawn through the inductor. At
this time energy is "eing stored in the inductor. ?hen the transistor stops conducting
the inductor !oltage flies "ack or re!erses "ecause the current through the inductor
cannot change instantaneously. The !oltage across the inductor increases to a !alue
that is higher than the com"ined !oltage across the diode and the output capacitor.
As soon as this !alue is reached' the diode starts conducting and the !oltage that
needs to "e higher than the input !oltage. This type of con!erter operates in the
fly"ack-mode. The fly"ack-mode "oost con!erter is shown "elow' in .ig. &.
.ig. & .ly"ack-mode "oost con!erter
&
appears across the output capacitor' is higher than the input !oltage.
2.2 Coponent #unctions
The inductor shown in .ig. & acts as the magnetic field storage element shown in
.ig. %. 0t stores energy in its core material. The ideal 2?7 functions as the switch
control and the transistor acts as the switch element. A diode and an output capacitor
are used to perform the function of the output rectifier and filter "lock.
!. Design Details
!.1 Detailed Circuit Description and #unction
The 7C**96* control chip manufactured "y 7otorola was used for the switch
control. Appendi( % shows the data sheet for this control chip. This particular chip
was chosen "ecause of the minimum num"er of e(ternal components required to
implement the design. The transistor shown in .ig. & is internal to the control chip.
Therefore' an e(ternal switch will not "e required. This de!ice also consists of a
%.&# $ reference regulator' a comparator' and a controlled duty cycle oscillator. The
oscillator charges and discharges an e(ternal timing capacitor. The upper threshold
of the timing capacitor is equal to the reference regulator !oltage of %.&# $.
The !alue of the timing capacitor sets the frequency of the entire circuit and controls
the rate of operation of the oscillator. ?hen the capacitor is charging the !oltage at
the lower input of the A/ gate is high. The comparator in!erting input is
connected to two e(ternal resistors' which control the duty cycle of the circuit. ?hen
the output !oltage of the con!erter falls "elow the required !alue' the in!erted input
of the comparator will fall "elow %.&# $. Then the comparator will output a +ogic
@% and the SR latch will set' ena"ling the transistor to conduct until %.&# $ is again
present at "oth inputs of the comparator. The timing capacitor will then discharge. A
*
+ogic @9 will "e present at the lower input of the A/ gate and the transistor will
stop conducting.
!.2 Coponent Calculations
0n order for the circuit to function properly' the e(ternal components need to "e
calculated carefully. ?hen the switch is on' the !oltage across the inductor is
and the current is gi!en "y
?hen the switch is off' the !oltage across the inductor is gi!en "y
and the current is gi!en "y
$. is the forward !oltage drop of the output rectifier and $sat is the saturation !oltage
of the output switch. Since 0+onA 0+off' ,qs.B&C and B5C can "e set equal to each other.
This operation gi!es a ratio for the on time o!er the off time. This ratio is gi!en "y
The !alues of $inBmiuC' $.' $out' and $sat are 5.# $' 9.: $' %&$' and 9.* $ respecti!ely.
The in!erse of the frequency of operation yields the on time plus the off time.
The frequency of operation for this "oost con!erter was chosen to "e 6&.# k><.
Therefore'
on
LPK
L
t
I
L
dt
di
L V = =
B%C

= =
off
LPK L
L
t
I I
L
dt
di
L V
min
B*C
on
sat in
Lon t
L
V V
I

=
B&C
B5C
off
in F out
Lpk Loff t
L
V V V
I I

+
=
B#C
sat in
in F out
off
on
V V
V V V
t
t

+
=
BminC
BminC
5
,quations B#C and B6C yield an on time of ;.:*5s and an off time of 6.%66s. The
duty cycle is gi!en "y
The calculated duty cycle of this circuit is 6%.#=. The !alue of the e(ternal timing
capacitor is calculated using
The !alue of the timing capacitor is *;9 p.. The peak current through the switch is
gi!en "y
and the minimum required inductance is gi!en "y
The calculated !alue of the minimum inductance is :9 >. The resistance required
for the current sense resister is gi!en "y
The calculated !alue for the current sense resistor is 9.# . The !alue of the output
capacitor is gi!en "y
Dsing a 9.6 $ for $ripple' Cout is equal to %.6: .. The !alues of the resistors used to
control the duty cycle are gi!en "y
B6C
s
f
t t off on %6
%
= = +
B)C
off on
on
t t
t
D
+
=
B:C
on T t C E CF # B G %9 E 9 . 5 H =
B;C

+ = % E &
off
on
out pkswitch
t
t
I I
B%9C

=
pkswitch
sat in
I
V V
L
BminC
min
B%%C
pkswitch
sc
I
R
* . 9
=
B%&C on
ripple
out
out t
V
I
C =
B%*C ( )

+ =
%
&
% &# . %
R
R
Vout
#
R% and R& were chosen to "e &.5 k and &9.65 k' respecti!ely.
!.! Siulation Procedure
.igure 5 shows the e(act circuit that was used in the 2S20C, simulation.
.ig. 5 2S20C, simulation
A pulse was used to mimic the operation of the control chip. An on time of ;.:*us
and an off time of 6.%6us were entered into the attri"utes of the pulse. The circuit
was simulated with a %&9 resister connected across the output capacitor. The
results of the simulation ha!e "een included in Appendi( &. .igure A&.% shows the
wa!eform of the !oltage at the switching node of the con!erter. .igure A&.& shows
the wa!eform of the output !oltage. The output !oltage le!els are at %& $.
$. Design %erification
$.1 &est Setup
The "oost con!erter was "uilt on a standard "read"oard. The # $C input !oltage
6
was supplied "y a >ewlett 2ackard power supply. All C measurements were taken
using .luke multimeters' and all wa!eforms were o"tained !ia an oscilloscope.
$.2 Design 'odifications
To o"tain the necessary "oosting action' the :9u> inductor was increased to a %&9u>
inductor with a thicker gauge wire' manufactured "y Coil Craft. 0n order to
eliminate noise at the output' all wire lengths were shortened. To eliminate noise
from the ground plane' 9.% u. capacitors were added to the input and the output of
the circuit. The %.6:u. capacitor was increased to #6 u.' in order to decrease the
output ripple. The resulting circuit schematic has "een inserted into Appendi( *.
$.! &est (esults
The first wa!eform shown in .ig. # is a picture of the !oltage at the switching node.
)
The frequency of operation is 6%.**k><. The circuit is operating with a 6*.&= duty
Cycle. The second wa!eform shows the !oltage across the timing capacitor. The
upper threshold of the timing capacitor can "e seen to "e %.&#$.
As shown in .ig. 6' the output ripple is %;9m$' or %.6=' when a %&9 resistor is
used as the load.
.igure ) shows the output ripple with no load connected across the output. Dnder
this condition' the output ripple is 9.95= of the output !oltage.
.ig. # $oltage across the switching node and timing capacitor
.ig. 6 -utput Ripple with a %&9 load resistor.
:
The output ripple wa!eform shown in .igure :' was taken with a %5#
load resistor. 0n this case' the output ripple is also %.6=.
.ig. ) -utput ripple with no load
;
Ta"le % shows the input and output !oltages' input and output currents' ripple
percentage' and power efficiencies with three different load conditions.
TAB+, %. T,ST R,SD+TS
%&9 -hms /o +oad %5# -hms
0nput $oltage 5.;;* $ 5.;;* $ 5.;;* $
0nput Current 9.*%: A 9.995# A 9.&)) A
-utput $oltage %&.%%9 $ %&.95) $ %&.9%& $
-utput Current 9.9;#5 A 9 A 9.9:9& A
.ig. : -utput ripple with %5# ohm load resistor
%9
-utput Ripple %.6 = 9.95 = %.6 =
,fficiency )*= /ot Applica"le )%=
The circuit was also tested to make sure it would function properly with a #$C
supply that had %9= tolerance. An input !oltage was 5.# $ corresponded to an
output !oltage of %&.%. An input !oltage of #.# $' ga!e %&.%$ at the output.
). Costs
).1 Parts Cost *stiate
The part num"ers and !alues of all components ha!e "een listed in Ta"le &.
Ta"le & C-72-/,/T C-STS
2art esignation escription Iuantity 2rice
7C**96*A Con!erter Control % J%.&&
2C>5#%&5 %&9u> 0nductor % J%.*)
%/#:%; Schottky iode % J9.:%
-------------------- Su+total ----------- ,!.$-
9.%u. Capacitor & J9.%9
%99 u. ,lectrolytic Capacitor % J9.%;
#9 u. ,lectrolytic Capacitor % J9.%#
CT *;9 p. Capacitor % J9.9)
-------------------- *stiated Capacitor &otal ------------ ,-.)1
Rsc % K ?att Resistor & J9.%9
Rcurrent +imit ** K ?att Resistor % J9.9#
R% &.5 k K ?att Resistor % J9.9#
R& &9.6 k K ?att Resistor % J9.9#
R
+ #9 %9? 2ower Resistor 5 J&.9:
-------------------- *stiated (esistor &otal ------------ ,2.!!
-------------------- Coponent &otal Cost ,).$!
).2 .a+or Cost *stiate
The la"or cost was calculated using an hourly wage of J&#.99. The a!erage num"er
of hours spent on this pro3ect were : hours per week' for %& weeks.
Total +a"or Cost A:E%&E&.#E&#AJ5#99 B%5C
4rand Total A J#.5* LJ6999AJ699#.5* B%#C
/. Conclusions
%%
All of the specifications stated pre!iously ha!e "een met "y this "oost con!erter design.
The output !oltage across the output capacitor is %&$ with a ma(imum output ripple of
%.6=. The power efficiency of the circuit e(ceeds )9 = for the load range of %&9-%5#.
>owe!er an additional constraint needs to "e put on the load. The load must not e(ceed %#9
. This will cause the efficiency to fall "elow the specified !alue of )9=.
%&
A22,/0M 5. R,.,R,/C,S
7arty Brown' Practical Switching Power Supply Design' /ew Nork8 Academic 2ress' 0nc.'
%;;9' pp. #-&6.
0r!ing 7. 4ottlie"' Power Supplies Switching Regulators In!erters " Con!erters' /ew
Nork8 7c4raw->ill' %;;*' pp. %*&-%5%.
. 7. 7itchell' DC#DC Switching Regulator $nalysis' /ew Nork8 7c4raw->ill' %;::'
pp. %#*-%#;.
4. Seguier' Power %lectronic Con!erters& DC#DC Con!ersion /ew Nork' Springer-$erlag'
0nc.' %;;*' pp. &9%-&%).
%;