This document contains example code for the tut sheet/ list of lab experiments given to you.

The purpose is to help you pass the exam. However, if you wish to become a programmer,
please try to understand the problem and write and compile your own code. The exercise
will help you gain confidence and learn enough for a graduate level vhdl course, although
you need to program for at least a few weeks to get some level of mastery over the subject.
All code given here has been compiled to test if it works. However, may not be able to test
all code for sample waveforms due to lack of time. !ou are encouraged to do so yourself.
And by no means do claim to be perfect. f any logical/human errors have crept in, please
be kind enough to point them out to me.
f there is any code you are not sure of, mail it to me at anumehra"##$%yahoo.com
And will get back to you with comments in about two days. All the best and &ood luck'
1. ()*+ +,A-./+ 0 A1* &AT+ 223)45+* 61+
library +++7
use +++.8T*9/)&(9::;$.all7
entity test is
port<
A, = > in 8T*9/)&(7
( > out 8T*9/)&(
?7
end test7
architecture test: of test is
begin
(@A A and =7
end test:7
222222222)4222222222
architecture test" of test is 223)45+* 61+
begin
process <A, =?
variable (*> std9logic7
begin
(*>A A and =7
( @A (*7
end process7
end test"7
1ote> constants and variables can be declared in processes and functions, but not
signals. However, procedures and architectures can take signal declarations as well. The
assignment operator should be noted carefully in both cases.
2. ()*+ +,A-./+ 0 HA/6 A**+4 22()*+ 3)45+* 61+
library +++7
use +++.8T*9/)&(9::;$.all7
entity ha is
port<
A, = > in 8T*9/)&(7
8B-, (A44! > out 8T*9/)&(
?7
end ha7
architecture dataflow of ha is
begin
(A44!@A A and =7
8B- @A A xor =7
end dataflow7
;. -ultiplexer <behavioral and dataflow style for $ to : multiplexer?, structural left for
the reader after understanding configurations.
+,A-./+ :>
1)T+> some books use these statements as part of behavioral modeling. However, in my
opinion, the distinction of conseCuent and seCuential modeling is most appropriate as is
given in our text book and so we will follow it.
library +++7 223)451& 61+
use +++.8T*9/)&(9::;$.all7 228T4B(TB4A/ ()*+ A**+* AT TH+ +1* )6
22TH8 .A&+
entity mux$9: is
port<
#, :, ", D > in 8T*9/)&(7
8#, 8: > in 8T*9/)&(7
! > out 8T*9/)&(
?7
end mux$9:7

architecture mux$9dataflow: of mux$9: is
signal sel> integer7
begin
with sel select
!@A # when #,
: when :,
" when ",
D when D,
E,E when others7
sel @A # when 8: AE#E and 8# AE#E else
: when 8: AE#E and 8# AE:E else
" when 8: AE:E and 8# AE#E else
D when 8: AE:E and 8# AE:E else
$7
end mux$9dataflow:7
222222222)422222222222 dataflow style using a single vector for select signal.
22()*+ 3)45+* 61+ A1* 8 +A8! 34T /A8T )1+
22TH+ /A8T )1+ 3A8 51*)6 (B-=+48)-+
226)4 -+
library +++7
use +++.8T*9/)&(9::;$.all7
entity mux$9" is
port< 8 > in 8T*9/)&(9F+(T)4<: downto #?7
#, :, ", D > in 8T*9/)&(7
! > out 8T*9/)&(
?7
end mux$9"7
architecture mux$9dataflow" of mux$9" is
begin
with 8 select
!@A # when G##G,
: when G#:G,
" when G:#G,
D when G::G,
E,E when others7
end mux$9dataflow"7
222222222)422222222222
An example showing modification of the above code where the input and output signals are
vectors themselves.
library +++7 2261+
use +++.8T*9/)&(9::;$.all7
entity mux$9" is
port< 8 > in 8T*9/)&(9F+(T)4<: downto #?7
#, :, ", D > in 8T*9/)&(9F+(T)4 <# to :H?7
! > out 8T*9/)&(9F+(T)4 <# to :H?
?7
end mux$9"7
architecture mux$9dataflow" of mux$9" is
begin
with 8 select
!@A # when G##G,
: when G#:G,
" when G:#G,
D when G::G,
<others AI E,E? when others7
22this statement is the same as
22J,,,,,,,,,,,,,,,,K when others7 but looks a lot nicer.
end mux$9dataflow"7
222222222)422222222222
behavioral style for the same enity as above>
architecture mux$9behavioral of mux$9" is
begin
process<8, #, :, ", D?
begin
case 8 is
when G##K AI !@A #7
when G#:K AI !@A :7
when G:#K AI !@A "7
when G::K AI !@A D7
when others AI !@A<others AI L,M?7
end case7
end process7
22this statement is the same as
22J,,,,,,,,,,,,,,,,K when others7 but looks a lot nicer.
end mux$9behavioral7
222222)4222222
library +++7 2261+
use +++.8T*9/)&(9::;$.all7
entity mux$9: is
port<
#, :, ", D > in 8T*9/)&(7
8#, 8: > in 8T*9/)&(7
! > out 8T*9/)&(
?7
end mux$9:7
architecture mux$9behav of mux$9: is
begin
process<8#, 8:, #, :, ", D?
variable sel>integer7
begin
if 8:AE#E and 8#AE#E then
sel>A#7
end if7
if 8:AE#E and 8#AE:E then
sel>A:7
end if7
if 8:AE:E and 8#AE#E then
sel>A"7
end if7
if 8:AE:E and 8#AE:E then
sel>AD7
end if7
if <8# /A E#E and 8#/A E:E? or <8: /A E#E and 8:/A E:E? then
sel>A$7
end if7
case sel is
when # AI !@A #7
when : AI !@A :7
when " AI !@A "7
when D AI !@A D7
when others AI !@AE,E7
end case7
end process7
end mux$9behav7
.erhaps there is a better way of doing this. 3hat do you thinkN
6rom now on we will prefer to write shorter codes by choosing std9logic9vectors wherever
possible.
H. *ecoder <" to $?
library +++7
use +++.8T*9/)&(9::;$.all7
entity decoder",$ is
port<
A > in 8T*9/)&(9F+(T)4<: downto #?7
+n > in 8T*9/)&(7
!> out 8T*9/)&(9F+(T)4<D downto #?
?7
end decoder",$7
architecture dataflow of decoder",$ is
signal !9store > 8T*9/)&(9F+(T)4<D downto #?7
begin
with A select
!9store @A G###:G when G##G,
G##:#G when G#:G,
G#:##G when G:#G,
G:###G when G::G,
G,,,,G when others7

! @A!9store when en AE:E else G####G7
end dataflow7
2222222222222222)4222222222222222
=ehavioral model for the same entity
architecture behav of decoder",$ is
signal !9store > 8T*9/)&(9F+(T)4<D downto #?7
begin
process<A, en?
begin
case A is
when G##GAI !9store @A G###:G 7
when G#:GAI !9store @A G##:#G 7
when G:#GAI !9store @A G#:##G7
when G::GAI !9store @A G:###G7
when others AI !9store @AG,,,,G 7
end case7
if en AE:E then
! @A!9store 7
else ! @A G####G7
end if7
end process7
end behav7
222222222)422222222
you can rewrite the same code as>
architecture behav of decoder",$ is
begin
process<A, en?
variable !9store > 8T*9/)&(9F+(T)4<D downto #?7
begin
case A is
when G##GAI !9store >A G###:G 7
when G#:GAI !9store >A G##:#G 7
when G:#GAI !9store >A G#:##G7
when G::GAI !9store >A G:###G7
when others AI !9store >AG,,,,G 7
end case7
if en AE:E then
! @A!9store 7
else ! @A G####G7
end if7
end process7
end behav7
1)T+> The advantage of declaring signals is that they are visible in the waveform analysis,
thus you can analyOe your program for mid values to see where it is going wrong if you do
not get results.
P. .riority +ncoder $ to " <do " to : and P to D yourself?
library +++7
use +++.8T*9/)&(9::;$.all7
entity priority is
port< *> in std9logic9vector <D downto #?7
Any> out std9logic7
A> out std9logic9vector< : downto #??7
end priority7
architecture behav of priority is
begin
process<*?
variable j>integer range D downto #7
begin
A @AG##G7
Any @A E#E7
for i in D downto # loop
if *<i?AE:E then
Any @A E:E7
j>Ai7
exit7
end if7
end loop7

case j is
when D AI A @AG::G7
when " AI A @AG:#G7
when : AI A @AG#:G7
when # AI A @AG##G7
end case7
if *AK####K then
A@AK##K
+nd if7
end process7
end behav7
Q. code for a : bit three state driver
library +++7
use +++.8T*9/)&(9::;$.all7
entity three9state is
port<
+ > in 8T*9/)&(7
* > in 8T*9/)&(7
! > out 8T*9/)&(
?7
end three9state7
architecture three9state of three9state is
begin
process <*, +?
begin
case + is
when E:EAI ! @A *7
when othersAI ! @A ERE7

end case7
end process7
end three9state7
222222222)42222222222
library +++7
use +++.8T*9/)&(9::;$.all7
entity three9state is
port<
+ > in 8T*9/)&(7
* > in 8T*9/)&(9F+(T)4 <# to S?7
! > out 8T*9/)&(9F+(T)4 <# to S?
?7
end three9state7
architecture three9state of three9state is
begin
process <*, +?
begin
case + is
when E:EAI ! @A *7
when othersAI ! @A <others AI ERE?7
end case7
end process7
end three9state7
22222222)422222222
Three state drivers, P bit, four buses
library +++7
use +++.8T*9/)&(9::;$.all7 221)T &F1& -+ .4).+4 )BT.BT
22=BT # +44)48 1 ()-./AT)1
entity three9state is 22me not getting the logic to work
port<
8+/ > in 8T*9/)&(9F+(T)4<: downto #?7
*#, *:, *", *D > in 8T*9/)&(9F+(T)4 <# to S?7
! > out 8T*9/)&(9F+(T)4 <# to S?
?7
end three9state7
architecture three9state of three9state is
begin
process <8+/, *#?
begin
if 8+/ AG##G then !@A *#7
else !@A <others AI ERE?7
end if7
end process7

process <8+/, *:?
begin
if 8+/ AG#:G then !@A *:7
else !@A <others AI ERE?7
end if7
end process7
process <8+/, *"?
begin
if 8+/ AG:#G then !@A *"7
else !@A <others AI ERE?7
end if7
end process7
process <8+/, *#?
begin
if 8+/ AG::G then !@A *D7
else !@A <others AI ERE?7
end if7
end process7
end three9state7
:#. .A4T! (H+(5+4
library +++7
use +++.8T*9/)&(9::;$.all7
entity parity9checker is
port<
> in 8T*9/)&(9F+(T)4<# to P?7
+F+1 > out 8T*9/)&(7
)** > out 8T*9/)&(
?7
end parity9checker7
architecture parity9checker of parity9checker is
begin
process<?
variable p> 8T*9/)&(7
begin
p>A <#?7
for j in : to P loop
if <j? AE:E then p>Anot<p?7
end if7
end loop7
)** @A p7
+F+1 @A not p7

end process7

end parity9checker7
"#. *esign examples of functions
8ubprograms consist of procedures and functions. A procedure can return more than one
argument or none, a function always returns one argument. n a function all parameters are
input parameters, in a procedure parameters can be input, output or inout. A function or
procedure can be conseCuent or seCuential. All statements in subprogram are seCuential.
library +++7
use +++.8T*9/)&(9::;$.all7
entity convert is
port<
:> n std9logic9vector <# to D?7
):> out integer
?7
end convert7
architecture behav of convert is
function vector9to9int <8> std9logic9vector <# to D??
return integer is
variable result> integer >A#7
begin
6or i in # to D loop
result >AresultT"7
if s<i? AE:E then
result>A result U :7
end if7
end loop7
return result7
end vector9to9int7
begin
): @A vector9to9int <:?7
end behav 7
999999999999999999999999999
library +++7
use +++.8T*9/)&(9::;$.all7
entity dff is
port<
d > in 8T*9/)&(7
clk > in 8T*9/)&(7
C > out 8T*9/)&(
?7
function rising9edge <signal ck> std9logic?
return boolean is
begin
if <ckEevent? and <ck AE:E? and <ckMlast valueAE#E? then
return true7
else
returnfalse 7
end if7
end rising9edge7

end dff7
architecture behav of dff is
begin
process<clk?
begin
if rising9edge <clk?then
C @Ad7
end if7
end process7
end behav7
999999999999999999
1)T+> ckEstable is a signal and can be used in the sensitivity list of
a process or a block.. ckEevent is a function attribute to a signal. and
should be used as an example in an if statement. To use it in a process
sensitivity list use not ckE stable. for more on attributes see ch :# bhasker
:Q. ()16&B4AT)18
(onfigurations are used for binding. The simplest configuration is none at all in which the
last architecture compiled is used for a given entity by default. Another way is to use
specific configurations and then call a specific configuration.
+xample>
library +++7
use +++.8T*9/)&(9::;$.all7
entity conf9test is
port<
A > in 8T*9/)&(7
= > in 8T*9/)&(7
(9)BT > out 8T*9/)&(
?7
end conf9test7
architecture conf9: of conf9test is
begin
(9)BT @A A and =7
end conf9:7
architecture conf9" of conf9test is
begin
(9)BT @A A or =7
end conf9"7
configuration no: of conf9test is
for conf9:
end for7
end no:7
configuration no" of conf9test is
for conf9"
end for7
end no"7
choose appropriate configuration to run the relevant architecture.
Architecture structural for decoder is given below
6/+:.vhd in a single design file
entity inv is
port<
, > in 8T*9/)&(7
! > out 8T*9/)&(
?7
end inv7
architecture one9line of inv is
begin
! @A not<,?7
end one9line7
optional configuration>
configuration invcon of inv is
for one9line
end for7
end invcon7
6/+".vhd in a single design file
library +++7
use +++.8T*9/)&(9::;$.all7
entity andD is
port<
A:, A", AD > in 8T*9/)&(7
): > out 8T*9/)&(
?7
end andD7
architecture one9line of andD is
begin
): @A <A: and A"? and AD7
end one9line7
optional configuration>
configuration andDcon of andD is
for one9line
end for7
end andDcon7
6/+D.vhd in a single design file
library +++7
use +++.8T*9/)&(9::;$.all7
entity decode is
port<
A, =, en > in 8T*9/)&(7
V#, V:, V", VD > out 8T*9/)&(
?7
end decode7
architecture structural of decode is
component inv
port<,> in std9logic7 !> out std9logic?7
end component7
component andD
port<A:, A", AD> in std9logic7
):> out std9logic?7
end component7
signal notA, not=> std9logic7
begin
:> inv
port map< A, notA?7
"> inv
port map< =, not=?7
A:> andD
port map<notA, en, not=, V#?7
A"> andD
port map<A, en, not=, V:?7
AD> andD
port map<notA, en, =, V"?7
A$> andD
port map<A, en, =, VD?7
end structural7
).T)1A/ ()16&B4AT)1 :>
configuration decode9con of decode is
6or structural
6or :> inv use configuration work.invcon7
end for7
6or "> inv use configuration work.invcon7
end for7
6or all> andD use configuration work.andDcon7
end for7
end for7
end decode9con7
).T)1A/ ()16&B4AT)1 ">
configuration decode9con of decode is
6or structural
6or :> inv use entity work.inv<one9line?7
end for7
6or "> inv use entity work.inv<one9line?7
end for7
6or all> andD use entity work.andD<one9line?7
end for7
end for7
end decode9con7
8uppose the code for the main program was the same as given above i.e. entity decode and
architecture structural. However, assume that the entity for the inverter was as given below
entity inv is
port<
5> in 8T*9/)&(7
/ > out 8T*9/)&(
?7
end inv7
architecture one9line of inv is
begin
/ @A not<5?7
end one9line7
the component given in the mail architecture is
component inv
port<,> in std9logic7 !> out std9logic?7
end component7
n such a case,
The configuration for decode should be written as
configuration decode9con of decode is
6or structural
6or all> inv use entity work.inv<one9line?7
.ort map <5 AI,, / AI!?7
end for7
6or all> andD use entity work.andD<one9line?7
end for7
end for7
end decode9con7
.orts from the component declaration are called formal ports. .ort names for the entity are
called actuals.
222222222)42222222222
-apping library entities>
/et us assume that one A1* gate of the decoder needs to be implemented differently from
others due to physical constraints of the device. .e. A three input and gate is built from two
" input and gates.
n such a case,
library +++7
use +++.8T*9/)&(9::;$.all7
entity and" is
port<
., V> in 8T*9/)&(7
4 > out 8T*9/)&(
?7
end andD7
architecture one9line of and" is
begin
4 @A. and V7
end one9line7
optional configuration>
configuration and"con of and" is
for one9line
end for7
end and"con7
Assume that the other two entity architecture pair inv and andD remain the same as in the
first case given on page :".
Two and agtes can be connected to form a three input and gate as shown below>
entity struc9andD is
port<
:, ", D > in 8T*9/)&(7
!: > out 8T*9/)&(
?7
end struc9andD7
architecture many9lines of struc9andD is
component and"
port<., V> in 8T*9/)&(7
4 > out 8T*9/)&(?7
+nd component7
8ignal 8:> std9logic7
begin
6:> and"
.ort map<.AI: , VAI ", 4AI8: ?7
6"> and"
.ort map<.AID , VAI 8:, 4AI!:?7
end many9lines7
configuration andDstr of struc9andD is
for many9lines
6or 6:> and" use configuration work.and"con7
+nd 6or7
6or 6"> and" use configuration work.and"con7
+nd 6or7
end andDstr7
(onfiguration for the main program will look like>
configuration decode9con" of decode is
6or structural
6or all> inv use entity work.inv<one9line?7
end for7
6or A:> andD use entity work.struc9andD<many9lines?
.ort map<:AIA:, "AIA", DAIAD, !:AI):?7
+nd 6or7
6or others> andD use entity work.andD<one9line?7
end for7
end for7
end decode9con"7
2222222222222222222222222222222222222222222222222222222222222222222222222222222222222
**1T &) (H+(51& 6)4 A// TH+ ()16&B4AT)1 ()*+8 A=)F+ =BT 8T// ** 8)-+
=A8( ()16&B4AT)1 TH1& A1* T4!1& 8T4B(TB4A/ -)*+/ 6)4 TH+ -B/T./+,+4
=+/)3. H).+ B /5+ THAT.
W2AsA&A4
22222222222222222222222222222222222222222222222222222222222222222222222222222222222222
2-Input Multiplexer, structural model
Tried "nput now. 3ill go for $nput the next time. This already took a lot of time and my
brain.
library ieee7
use ieee.std9logic9::;$.all7
entity mux" is
port <a, b, sel> in std9logic7
f> out std9logic?7
end mux"7

architecture netlist of mux" is
signal n:, n", nD> std9logic7

component and"
port<x, y> in std9logic7 O> out std9logic?7
end component7

component or"
port<x, y> in std9logic7 O> out std9logic?7
end component7

component inv
port<x> in std9logic7 O> out std9logic?7
end component7
begin
u:> inv port map<xAIsel, OAIn:?7
u"> and" port map<xAIn:, yAIa, OAIn"?7
uD> and" port map<sel, b, nD?7
u$> or" port map<n", nD, f?7
end netlist7