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(x)
1.5 V
1.0 V
Vox
500 mV
- tox
VGB - VFB
s,max = 420 mV
QG
Xd,max
2 p
ion
ers
inv
- 500 mV
letio
dep
consider: bulk charge is constant for VGB > VTn --> all of the additional charge in
the silicon is stored in the inversion layer, once inversion occurs. The inversion
layer is separated from the gate by the gate oxide; we can relate the inversion
charge (per cm2) to the applied voltage over VTn through Cox the capacitance
(per cm2) of the oxide
on
ati
ul
VFB = 0.97 V
QB,max
QB(VGB)
0
QN(VGB)
VGB (V)
VTn = 0.6 V
cu
ac
Q N = C ox ( V GB V Tn )
MOS Capacitance
gate
ion
qG
ers
inv
qN(vGB)
Si/SiO2 surface
on
pleti
de
QB,max
qB(vGB)
s
C b = -----Xd
Note that Xd is
a function of VGB
vGB (V)
C = C ox C b
VTn = 0.6 V
VFB = 0.97 V
cu
i
lat
on
bulk
ox
C ox = -------t ox
ac
(a)
C/Cox
accumulation
inversion
1.0
0.8
ion
t
ple
de
0.6
0.4
VFB = 0.97 V
2
0.2
VTn = 0.6 V
1
1
VGB (V)
(b)
Step 1: identify the atband voltage from the gate and bulk potentials in
equilibrium
2q s N d ( 2 n )
V Tp = V FB 2 n ------------------------------------- = 1.03 2 ( 0.48 ) 3.28 = 3.21 V
C
ox
Why? positive charge on gate ( since VGB - VFB > 0 V) must be mirrored by a
negative charge in the substrate.
n-type substrate: negatively charged electrons are accumulated under the gate
p-type substrate: negatively charged ionized acceptors are left, after holes are
repelled away from positive charge on gate
Step 3: construct C(VGB) plot, using the knowledge that the substrate is depleted
on the other side of VFB from accumulation in Step 2 and that inversion occurs
after depletion. Calculation of VT and Cmin is necessary to quantify the plot
Example:
0.75
1.16/1.72 = 0.67
gate:
polysilicon (where p+ = - 550 mV); gate oxide thickness = 200 ,
substrate: n type silicon, n = 480 mV (Nd = 1018 cm-3)
p+
0.5
VGB - VFB > 0 V --> accumulated; substrate is depleted for VGB < 1.03 V
Check: VGB = 0 --> negative charge on gate; positive in bulk (since gate is at
- 0.55 V and substrate is at + 0.48 V in thermal equilibrium) --> positive donors in
depletion region under gate ... and possibly holes due to inversion
1.03 V
-3.21 V
0
-4
-3
-2
-1
VGB
Two complementary devices (each with two symbols): both are very useful
,,,
,,,,,,,,,
,,, , , , , , ,
, , ,,,,,,,,,,,,,,,,
,,,,,,, ,,,,,,,,,,,,,,
,,,,,,, ,,,,,,,,,,,,,,
,,,,,,,
,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,
,,,,,,,
,,,,,,,,,,,,,,,,,,,,
,,
,
,,
,,
,,
,,
gate
interconnect
gate contact
polysilicon gate
contact
n+ polysilicon gate
metal
interconnect
IDn
D
+
IDn
VDS > 0
G
+
VGS
B
+
VBS
_ _
S
+ S
+
_
VSG
VSB
_
B
VSD > 0
IDp
IDp
source contacts
Drain
Gate
drain
contacts
Source
n+
Source
Bulk or
Body
Gate
Drain
p+
Bulk or
Body
p+
edge of
active area
drain
interconnect
source
interconnect
n+
bulk
contact
(a)
gate oxide
source
interconnect
n+ polysilicon gate
bulk
drain
interconnect
interconnect
,
,,,,,,
,
,
,,,,
,,,,
,
,,
,,,
,,,,
,,,,,,
deposited
oxide
n+ drain diffusion
Ldiff
+
field n source diffusion
oxide
[ p-type ]
p+
Four electrical terminals: source (lowest potential for n-channel, highest for pchannel), drain, gate, and bulk.
Basic concept: inversion layer (called the channel) formed under gate between
source and drain enables drift current
(b)
IDn(VGS , VDS)
D
G
+
VSD
G
+ V
DS
B
VGS
VSG
_
VG
_
D
IDp
5V
+ V
D
ID(VSG ,VSD)
(a)
(a)
VGS = 3.5 V
VSG = 3.5 V
600
500
300
VDS = VGS VTn = VGS 1 V
(triode
region)
250
VGS = 3 V
400
IDn
(A)
constant current
(saturation) region
300
IDp
(A)
VGS = 2.5
100
150
100
VSG = 0, 0.5, 1 V
(cutoff region)
VSG = 2 V
50
VGS = 1.5 V
1
VSG = 3 V
(saturation region)
VSG = 25
VGS = 0, 0.5, 1 V
(cutoff region)
VGS = 2 V
200
(triode
region)
200
VDS (V)
VSG = 1.5 V
1
(b)
VSD (V)
(b)