Merge

EECS 247 Lecture 1: Overview 2002 B.
Boser 1
A/D
DSP
EECS 247
Analog-Digital Interface
Integrated Circuits
2002
Bernhard E. Boser
Department of Electrical Engineering
and Computer Sciences
EECS 247 Lecture 1: Overview 2002 B. Boser 2
A/D
DSP
Administrative
Course web page:
http://www.eecs.berkeley.edu/~boser
(link to EECS 247)
Overview
Scope of course
Reference texts
Grade and homework policy
Office hours
Tuesday 2 to 3pm
Friday 11am to noon
Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com
A/D
DSP
Acknowledgement
Introduction to System Design and Modeling
course, developed by Eric Swanson
Notes from Prof. Gray for an earlier version of
this course
Countless books and articles
A/D
DSP
Analog-Digital Interface Circuits
Anatomy of analog processor
analog pre/post processing
A/D and D/A converters
digital signal processor
Analog
Postprocessing
D/A
Conversion
DSP
A/D
Conversion
Analog
Preprocessing
Analog Input
Analog Output
A/D
DSP
Why Digital Processing?
Digital circuitry:
Cost/function decreases by 29% each year
Thats 30X in 10 years
Analog circuitry:
Cost/function is constant
Dropping supply voltages threaten feasibility
Transition to DSP is inevitable!
Ref: International Technology Roadmap for Semiconductors,
http://public.itrs.net
A/D
DSP
Why Analog Processing?
The real or physical world is analog
Examples:
Digital Audio
RF receiver
Wireline communications
A/D
DSP
Example: Digital Audio
Goal
Lossless archival and transmission
of audio signals
Circuit functions:
Preprocessing
Amplification
Anti-alias filtering
A/D Conversion
>16Bits, >41kHz
DSP
Storage
Processing (e.g. recognition)
D/A Conversion
Postprocessing
Smoothing
Amplification
Analog
Postprocessing
D/A
Conversion
DSP
A/D
Conversion
Analog
Preprocessing
Analog Input
Analog Output
A/D
DSP
Example: RF Receiver
Goals
Wireless communication
Minimizing use of bandwidth
Immunity to interference
Circuit functions:
Preprocessing
Filtering
Amplification
Frequency translation
A/D Conversion
DSP
Demodulation
Decoding
D/A Conversion
Postprocessing
Smooting
Amplification
Analog
Postprocessing
D/A
Conversion
DSP
A/D
Conversion
Analog
Preprocessing
Analog Input
Analog Output
A/D
DSP
Example: Modem
Goals
Transmit data over inexpensive, noisy channel
Maximize distance, minimize errors
Circuit functions
Transmit DSP
Bandwidth efficient and error tolerant data encoding
Transmitter
Pulse shaping (minimize ISI)
Line driver
Noisy Channel
Frequency (and time) dependent attenuation
Noise
Receiver
Equalization
Clock recovery, slicing
Receive DSP
Decode data
Receive DSP
Receiver
Noisy
Channel
Transmitter
Transmit DSP
Digital
Clock and Data in
Digital
Clock and Data out
A/D
DSP
Signal Processing Fundamentals
EECS 247
Filtering
Data Conversion
Data detection, timing recovery
EECS 142, 242
RF amplification, mixing
Oscillators
Nonlinear circuits
A/D
DSP
System Modeling
Top-down design
Abstraction
Key for dealing with complexity (> 10
6
transistors)
Each level establishes requirements for next level down in
the hierarchy
Challenges
Unrealizable blocks
Physical constraints
Modeling errors
Number and complexity of blocks
Verification
A/D
DSP
Challenge of IC Fabrication
No other EE discipline is less forgiving of errors
You can change PLDs or software in a day
You can build and test a printed circuit board in a week
It takes months to tape out and fabricate a chip
Debugging and characterizing a (defective) chip also takes
months
State-of-the-art chips are never perfect
But they have to be good enough for someone to buy them
If you want to sell bugs, try a career in software
(quote from Eric Swanson)
A/D
DSP
Modeling Tools
This is not a tool-centric course
Knowledge of design fundamentals lives through many
generations of tools
Behavioral modeling tools are not always effective:
long learning curve
Tools we will use
MATLAB / Simulink (student version is adequate)
SPICE
MathCAD, Excel,
A/D
DSP
EECS 247 versus 240
EECS 247
Macro-models, behavioral simulation, large systems
Signal processing fundamentals
High level of abstraction:
physical constraints (e.g. finite gain, supply, noise) added where
appropriate
Matlab
EECS 240
Transistor level, building blocks
Device and circuit fundamentals
Little abstraction
SPICE
EECS 247 Lecture 2: Introduction to Filters 2002 B. Boser 1
A/D
DSP
Introduction to Filters
Filtering = frequency-selective signal processing
Its the most common type of signal processing
Examples:
Extract desired signal from many (radio)
Separating signal and noise
Amplifier bandwidth limitations
Where to start
Perfectionist: ideal (low-pass) filter
Engineer: continuous time, first-order low-pass filter
A/D
DSP
First-Order RC Filter (LPF1)
Steady-state frequency response:
kHz
RC
s
s V
s V
s H
o
o
in
out
100 2
1
with
1
1
) (
) (
) (
= =
+
= =


A/D
DSP
Poles and Zeros
s-plane (pzmap):

=
+
=
z
p
s
s H
o
o
: Zero
: Pole
1
1
) (
j
p=-
o
A/D
DSP
Magnitude Response
- 5
0
5
x 10
5
-5
0
5
x 10
5
0
0.5
1
1.5
2
2.5
3
Frequency [Hz]
Magnitude Response (s-plane)
Sigma [Hz]
M
a
g
n
i
t
u
d
e

[
l
i
n
e
a
r
]
L02_bode3_lpf1.m
A/D
DSP
Frequency Response
Asymptotes:
- 20 dB/dec rolloff
- 90 degrees phase shift per 2 decades
Matlab code (L02_bode_lpf1.m):
wo = 2*pi*100e3;
s = tf('s');
h = 1 / (1+s/wo);
bodehz(h, logspace(1, 10, 100));
Note: bodehz is same as bode, but frequency axis
is in Hz, rather than rad/s.
-120
-100
-80
-60
-40
-20
0
Bode Diagram
Frequency [Hz]
P
h
a
s
e
(
d
e
g
)
M
a
g
n
itu
d
e
(
d
B
)
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-90
-60
-30
0
0 ) (
1 ) (
0
= =
= =

=
j s H
j s H
A/D
DSP
Parasitics
Can we really get 100dB attenuation at 10GHz?
Probably not
Parasitics limit the performance of analog
components
E.g.
Shunt capacitance
Feed-through capacitance
Finite inductor, capacitor Q
A/D
DSP
LPF2
( )
P
P
C C sR
sRC
s H
+ +
+
=
1
1
) (
( )
P
P
RC
z
RC C C R
p
1
: Zero
1 1
: Pole
=

+
=
A/D
DSP
Frequency Response
dB
C
C
C C
C
j H
j H
P
P
P
60
10
) (
1 ) (
3
0
=
=
+
=
=
LPF2
Frequency [Hz]
P
h
a
s
e

(
d
e
g
)
M
a
g
n
itu
d
e

(
d
B
)
-80
-70
-60
-50
-40
-30
-20
-10
0
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-90
-45
0
Why not just make C larger?
Beware of other parasitics not included in this model
A/D
DSP
Continuous Time Analog
Analog passive components arent ideal
Extra real poles/zeroes result from parasitics
Parasitic effects begin to appear 50dB beyond desired
component characteristics
Common sense helps you anticipate them
Digital filters do not suffer from these effects
A/D
DSP
Second-Order LPF
Improved attenuation (compared to 1
st
order)
Complex poles (rather than multiple real ones)
Why?
Visualize 3D s-plane plot!
Biquadratic (2
nd
order) transfer function:
2
2
1
1
) (
P P P
s
Q
s
s H

+ +
=
P
Q j H
j H
j H
P
=
=
=
=

=

) (
0 ) (
1 ) (
0
A/D
DSP
Biquad Poles
( )
otherwise complex real, are poles for
4 1 1
2
s at poles has
1
1
) (
2
1
2
2
2
=
+ +
=
P
P
P
P
P P P
Q
Q
Q
s
Q
s
s H

A/D
DSP
Complex Poles
( ) 1 4 1
2
s
2
2
1
=
>
P
P
P
P
Q j
Q
Q
Distance from origin in s-plane:

( )
2
2
2
2
1 4 1
2
P
P
P
P
Q
Q
d
=
+
=
A/D
DSP
s-Plane
poles
j
P
radius =
P
2Q
- part real
P
=
A/D
DSP
LPF3
10
100 2
=
=
P
P
Q
kHz
- 2
-1
0
1
2
x 10
5
-2
-1
0
1
2
x 10
5
0
0.5
1
1.5
2
2.5
3
Frequency [Hz]
Sigma [Hz]
M
a
g
n
i
t
u
d
e

[
l
i
n
e
a
r
]
A/D
DSP
Bode Diagram
Frequency (rad/sec)
P
h
a
s
e

(
d
e
g
)
M
a
g
n
it
u
d
e
(
d
B
)
-200
-150
-100
-50
0
50
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-180
-135
-90
-45
0
Frequency Response
-40 dB/dec
-180
o
A/D
DSP
Varying Q Magnitude
Gain at
p
:
20 log Q [dB]
10
4
10
5
10
6
-50
-40
-30
-20
-10
0
10
20
30
40
LPF3 Magnitude Response
Frequency [Hz]
M
a
g
n
it
u
d
e

[
d
B
]
Q = 0.5
Q = 10.0
Q = 100.0
A/D
DSP
Phase
Slope at
p
:
-45 Q deg/decade
10
4
10
5
10
6
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
LPF3 Phase Response
Frequency [Hz]
P
h
a
s
e

[
d
e
g
r
e
e
s
]
Q = 0.5
Q = 10.0
Q = 100.0
A/D
DSP
Implementation of Biquads
Passive RC: only real poles
Terminated LC
lowest power (well its passive!)
No noise (except load and source)
Active Biquad
Filter texts give you dozens of topologies.
Who needs or wants that many choices?
Single-opamp biquad: Sallen-Key
Two-opamp biquad: Tow-Thomas
A/D
DSP
Sallen-Key LPF
Single gain element
Parasitic sensitive
Versions for LPF, HPF, BP,
Ref: K. L. Su, Analog Filters, Chapman & Hall, 1996, pp. 215.
2 2 1 2 1 1
2 2 1 1
2
2
1 1 1
1
1
) (
C R
G
C R C R
Q
C R C R
s
Q
s
G
s H
P
P
P
P P P
+ +
=
=
+ +
=

A/D
DSP
Component Sizing Choice 1
4 unknowns: R
1
, R
2
, C
1
, C
2
2 knowns:
P
, Q
P
problem is underdetermined
Choice 1: minimum component spread
9 . 2
1
3
6 . 1
1
1
1
2 1
2 1
= =
= = =
= =
P
P
Q
G
k
C
R R
nF C C

A/D
DSP
SK Magnitude Response 1
10% increase of R
1
more than doubles Q
P
!
The circuit is very sensitive
to component variations.
10
4
10
5
10
6
-50
-40
-30
-20
-10
0
10
20
30
40
Sallen-Key Choice 1 Magnitude Response
Frequency [Hz]
M
a
g
n
it
u
d
e

[
d
B
]
nominal R1
R1 10% large
A/D
DSP
Component Sizing Choice 2
Choice 2: minimum sensitivity
pF
R Q
C
nF
R
Q
C
k R R
G
P P
P
P
40
2
1
16
2
2
1
1
2
1
1
2 1
= =
= =
= =
=
400 4
2
2
1
= =
P
Q
C
C
Note also:
Huge element spread
This topology is suitable only for
low-Q filter implementations.
A/D
DSP
SK Magnitude Response 2
10% increase of R
1
has only small
effect on response!
The circuit is NOT very sensitive
to component variations.
10
4
10
5
10
6
-50
-40
-30
-20
-10
0
10
20
30
Sallen-Key Choice 2 Magnitude Response
Frequency [Hz]
M
a
g
n
it
u
d
e

[
d
B
]
nominal R1
R1 10% large
A/D
DSP
Sensitivity
Implementation and component
sizing have huge impact on
sensitivity
High-sensitivity circuits are
problems in practice
No theory for finding a low-
sensitivity architecture
Ladder filters are usually low
sensitivity
Use proven circuits & check!
0 2 Choice
% 95 5 . 9
5 . 9 5 . 0 1 Choice
Example
with
Definition
1
1
1
1
1
1
1
=
=
= =
P
P
P
Q
R
P
P
P
Q
R
Q
R
P
P
y
x
y
x
S
R
R
Q
Q
Q S
R
R
S
Q
Q
dx
dy
y
x
S
x
x
S
y
y
Common sense: Sensitivity is a first order approximation,
correct only for infinitesimally small errors
A/D
DSP
Summary
Frequency Response
Poles and zeros are like tent poles and pegs
Frequency response is evaluated on j axis
Poles and zeros close to j axis dominate resonse
Practical Implementation Constraints
Components are not ideal
Avoid solutions requiring large element spread
Beware of high-sensitivity architectures
EECS 247 Lecture 3: Second Order Transfer Functions 2002 B. Boser 1
A/D
DSP
2
nd
Order Transfer Functions
Imaginary axis zeroes
Tow-Thomas Biquad
Example
A/D
DSP
Imaginary Axis Zeros
Sharpen transition band
notch out interference
High-pass filter (HPF)
Band-reject filter
2
2
2
) (
1
1
) (
+ +
+
=

Z
P
P P P
Z
K j H
s
Q
s
s
K s H
Note: Always represent transfer functions as a product of a gain

term, poles, and zeros (pairs if complex). Then all
coefficients have a physical meaning, reasonable
magnitude, and easily checkable unit.
A/D
DSP
Imaginary Axis Zeros
-5
0
5
x 10
5
-5
0
5
x 10
5
0
0.5
1
1.5
2
Sigma [Hz]
Frequency [Hz]
M
a
g
n
itu
d
e

[lin
e
a
r
]
-5
0
5
x 10
5
-5
0
5
x 10
5
0
0.5
1
1.5
2
Sigma [Hz]
Frequency [Hz]
M
a
g
n
itu
d
e

[lin
e
a
r
]
No finite zeros With finite zeros
A/D
DSP
Imaginary Zeros
Zeros substantially sharpen
transition band
At the expense of reduced stop-
band attenuation at high frequency
P Z
P
P
f f
Q
kHz f
3
2
100
=
=
=
Pole-Zero Map
Real Axis
Im
a
g
A
x
is
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
x 10
6
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
x 10
6
10
4
10
5
10
6
10
7
-50
-40
-30
-20
-10
0
10
Frequency [Hz]
M
a
g
n
itu
d
e
[d
B
]
With zeros
No zeros
A/D
DSP
Moving the Zeros
P Z
P
P
f f
Q
kHz f
=
=
=
2
100
Pole-Zero Map
Real Axis
Im
a
g
A
x
is
-6 -4 -2 0 2 4 6
x 10
5
-6
-4
-2
0
2
4
6
x 10
5
10
4
10
5
10
6
10
7
-50
-40
-30
-20
-10
0
10
20
Frequency [Hz]
M
a
g
n
itu
d
e
[d
B
]
A/D
DSP
Tow-Thomas Biquad
Ref: P. E. Fleischer and J. Tow, Design Formulas for biquad active filters using
three operational amplifiers, Proc. IEEE, vol. 61, pp. 662-3, May 1973.
Parasitic insensitive
Multiple outputs
A/D
DSP
Frequency Response
( ) ( )
( ) ( )
0 1
2
1 0 0 1 0 2 0
0 1
3
0 1
2
0 1
2
2 2
0 1
2
0 0 2 1 1 2
2
1
1
a s a s
b a b a s a b b
a k V
V
a s a s
b s b s b
V
V
a s a s
b a b s b a b
k
V
V
in
o
in
o
in
o
+ +
+
=
+ +
+ +
=
+ +
+
=
V
o2
implements a general biquad section with arbitrary poles and zeros
V
o1
and V
o3
realize the same poles but are limited to at most one finite zero
A/D
DSP
Component Values
8
7
2
1 7 3
2 8 2
1
1 1
1
2 1 7 3 2
8
0
6
8
2
7 4
8 1
6
8
1 1
1
2 1 7 5 3
8
0
1
1
R
R
k
C R R
C R R
k
C R
a
C C R R R
R
a
R
R
b
R R
R R
R
R
C R
b
C C R R R
R
b
=
=
=
=
=
=
=
8 2 7
2
8
6
2 0
0 1
5
1 1 2 1 2
4
1 0 2 1
3
2 0
1
2
1 1
1
1 1 1
1 1
1
R k R
b
R
R
C b
a k
R
C b b a k
R
C a k k
R
C a
k
R
C a
R
=
=
=
=
=
=
=
8 2 1
and , , , , given R C C k b a
i i i
that follows it
1 1
2 1 7 3 2
8
C R Q
C C R R R
R
P P
P
=
=
A/D
DSP
Filter Design Example
Application: testing of ultra-linear ADC
Problem: sinusoidal source has higher distortion than
the ADC!
Solution
Filter source with bandpass before converting
Check resulting source with spectral analyzer
Twist: the analyzer is not sufficiently linear either
notch out sinusoid and look just at harmonics
Implementation
Bandpass & Notch at 1kHz
Use V
o2
for bandpass (only possibility),
V
o1
for notch
A/D
DSP
1kHz
Generator
1kHz
BPF
1kHz
Notch
spectrum
analyzer
ADC under
test
Principle: IC test circuits are useless if you cant
verify their performance!
Our filter
A/D
DSP
Filter Coefficients
( ) ( )
( ) ( )
0 1
2
1 0 0 1 0 2 0
0 1
3
0 1
2
0 1
2
2 2
0 1
2
0 0 2 1 1 2
2
1
1
a s a s
b a b a s a b b
a k V
V
a s a s
b s b s b
V
V
a s a s
b a b s b a b
k
V
V
in
o
in
o
in
o
+ +
+
=
+ +
+ +
=
+ +
+
=
( )
1 k
outputs) other below
slightly V unused keep (to 05 . 1 k
: levels signal reasonable Choose
bandpass) a in want we as (just 0
: free" " for ss Get Bandpa
1
0
1 2
: Notch Design
2
o3 1
0 0 2
1 1 1 2
2
1
2 2
0 0
=
=
=
=
=
=
= = =
b a b
a b a b
b
b
kHz a b
P

A/D
DSP
Final Filter
0 1
2
0 1 3
0 1
2
0
2
2
0 1
2
1 1
05 . 1
1
a s a s
a a
V
V
a s a s
a s
V
V
a s a s
s a
V
V
in
o
in
o
in
o
+ +
=
+ +
+
=
+ +
=
Choose:
C1=C2=112nF (large to minimize noise)
R8=1k
f
P
=1kHz, Q
P
=30 (check sensitivity!)
Solve equations
R1=42.631k
R2=1.4921k
R3=1.3534k
R4=42.631k
R5=1.4921k
R6=R7=R8
Lets order the parts
A/D
DSP
Capacitors
C0G capacitors
Vishay Vitramon, C0G Dielectric Capacitor datasheet, 2000.
http://www.vishay.com/document/45002/45002.pdf
Negligible voltage coefficient (for linearity)
Excellent tempco (30ppm/C)
2% initial accuracy is easy to get
No high-value capacitors are trimmable
Resistors will be trimmed to compensate for capacitor
variations
A/D
DSP
Resistors
Trimmed resistors combine fixed metal film resistors and
precision trim potentiometers in series
1%-accurate, 5ppm/C, lab grade metal film resistors provide 90%
of the nominal resistance
Ref: Caddock Electronics, Type TN Lab Grade Low TC Precision Film Resistor
datasheet, 1999.
50ppm/C trim pots provide between 0% and 20% of the nominal
resistance
Ref: Vishay Foil Resistors, Model 1268 Precision Trimming Potentiometers datasheet
Use two fixed resistors in series with the trimpot to minimize trimpot
value and optimize overall tempco
R6-R8 are 0.1%-accurate, 5ppm/C metal film
A/D
DSP
Opamps
For opamps, well use the Burr-Brown OPA627
Ref: Texas Instruments / Burr-Brown, OPA627 and OPA604
datasheets, 1989.
The finest audio opamp in the world, and, at $15/each,
priced accordingly!
But money is no object when designing IC test fixtures (only
a few are ever built)
Adequate speed for this application
A/D
DSP
Bandpass/Bandstop Responses
A/D
DSP
Filter Design Example (cont.)
Note that the bandpass output H
1
provides
>30dB attenuation to all harmonics present in
the 1kHz generator output
Opamp outputs have 0.00.5dB peak gain
This maximizes each opamps output swing for
best dynamic range
Lets magnify the frequency axis for the two
responses of interest
A/D
DSP
A/D
DSP
Temperature changes wont change these
responses too much
Lab temperatures are stable to 253C
Our lab-grade RC products move <100ppm/C
Initial component values are another story
What if C1=114nF and C2=113nF?
Thats within their 2% accuracy specifications
Whats ?
P
C
S
1
A/D
DSP
Frequency (kHz)
G
a
i
n

(
d
B
)
20
0
- 20
- 40
- 60
0.9 1.1
H
1
H
2
C1=.114F
C2=.113F
Rs nominal
A/D
DSP
Obviously, weve got to tune the filter
back to its original specification
How is that tuning done?
Do you tell your technician to twiddle pots
randomly until it works?
Or do you document a robust tuning
procedure?
A/D
DSP
RC Filter Tuning Strategy
Famous biquads like the Tow-Thomas come
complete with their own tuning strategies
The circuit topologies allow 1 trim operation to adjust 1
design parameter (such as f
P
, f
Z
, Q
P
, Q
Z
, gain) without
changing the others
Rationale for a biquads tuning strategy becomes
apparent when studying design equations such as
the Tow-Thomas equations on slide 6
A/D
DSP
Tow-Thomas Tuning Strategy
R3 will be set to a fixed value to keep the
unused OPAMP3 output below 0dB
Tuning involves the following steps performed
in the specified sequence:
Adjust R2 to center the bandpass at 1kHz
Adjust R5 to center the notch at 1kHz
Adjust R1 to set the bandpass Q to 30
Adjust R4 to deepen the notch
A/D
DSP
The design equations also provide the range of
adjustment required for a given resistor
Remember that an excessively large adjustment range
translates into excessively large tempco
R1 tuning range (from slide 7):
a
1
1
R
1
C
1

1
a
1
C
1MAX
1
a
1
C
1MIN
< R
1
<
known set by capacitor tolerances
A/D
DSP
An even simpler way to determine
resistor ranges is to:
Set all capacitors to their high tolerance
limit (nominal+2% in this case)
Calculate Rs for these capacitances
(these will be the minimum resistance
values)
Set capacitors to their low tolerance limit
Calculate maximum Rs
A/D
DSP
Tow-Thomas Biquad
C
2
(0.112)
v
IN
R
7
(1K)
R
1
(40K+5K)
R
5
(1.4K+200)
R
6
(1K)
R
8
(1K)
R
3
(1.35K)
R
4
(40K+5K)
OPAMP1 OPAMP2 OPAMP3
C
1
(0.112)
R
2
(1.4K+200)
resistors: metal film + trimpot
A/D
DSP
If youve left your filter unattended for a while,
assume that its trim potentiometers are
completely misadjusted
Adjust all trimpots to 0 and start over
Lets return to our C1=114nF, C2=113nF example
A/D
DSP
Frequency (kHz)
G
a
i
n

(
d
B
)
20
0
- 20
- 40
- 60
0.9 1.1
H
1
H
2
C1=114nF
C2=113nF
Rs nominal
A/D
DSP
Frequency (kHz)
G
a
i
n

(
d
B
)
20
0
- 20
- 40
- 60
0.9 1.1
H
1
H
2
C1=114nF
C2=113nF
trimpots=0
A/D
DSP
For most Rs and Cs in this biquad
Hence,
This means a +2% change in R
2
will cause a
1% change in f
P
Note that f
Z
sensitivities are also 1/2
A 4% increase in R
5
will shift our notch (currently at
1.02kHz) back to the right place
x
f
P
1
~
2
1
=
P
f
x
S
A/D
DSP
Frequency (kHz)
G
a
i
n

(
d
B
)
20
0
- 20
- 40
- 60
0.9 1.1
H
1
H
2
C1=114nF
C2=113nF
R1=41k
R2=1456
R3=1350
R4=41k
R5=1456
R6=R7=R8=1k
A/D
DSP
Summary
General 2
nd
order transfer function
Imaginary axis zeros
General purpose biquad
Large selection in literature
Tow-Thomas biquad:
3 opamps
Parasitic insensitive
Multiple outputs
Tuning strategy
EECS 247 Lecture 4: Dynamic Range 2002 B. Boser 1
A/D
DSP
Electronic Noise
Dynamic range in the analog domain
Resistor noise
Amplifier noise
Maximum signal levels
Tow-Thomas Biquad noise example
Implications on power dissipation
A/D
DSP
Analog Dynamic Range
Finite precision effects in digital filters are
rapidly becoming negligible
Floating point digital filters with huge mantissas
will be reduced to negligible cost
The only fixed-point numbers will come from
ADCs
But we will always have thermal noise
A/D
DSP
Lets say youve selected the poles and
zeroes of your analog filter transfer
function
Of the infinitely many ways to build a
filter with a given transfer function, each
of those ways has a different output
noise!
A/D
DSP
The job of a high-performance analog filter
designer is to get reasonably close to the
optimal noise for a given transfer function
Not the absolute minimum noise, just close
The job of a mixed-signal chip architect is to
appreciate filter noise and to be able to model
filters well enough to know that a given
dynamic range objective is feasible
A/D
DSP
Well begin our adventure in analog filter
implementation by looking at the noise
in resistors and simple RC filters
A/D
DSP
Resistor Noise
Capacitors are
noiseless
Resistors have
thermal noise
This noise is
uniformly distributed
from dc to infinity
Frequency-
independent noise is
called white noise
R
C
v
IN
v
OUT
A/D
DSP
f R T k v
r B n
= 4
2
Resistor Noise
Resistor noise has
A mean value of zero
A mean-squared value
R
C
v
IN
v
OUT
measurement bandwidth (Hz)
absolute temperature (K)
Boltzmanns constant = 1.38e-23 J/K
ohms
Volts
2
A/D
DSP
Resistor Noise
Resistor rms noise voltage in
a 10Hz band centered at
1kHz is the same as resistor
rms noise in a 10Hz band
centered at 1GHz
Resistor noise spectral
density, N
0
, is the rms noise
per Hz of bandwidth:
R
C
v
IN
v
OUT
R T k
f
v
N
r B
n
4
2
0
=
=
A/D
DSP
Resistor Noise
Dont bother to remember
Boltzmanns constant
Instead, remember forever that N
0
for a 1k resistor at room
temperature is 4nV/Hz
Scaling R,
A 10M resistor gives 400nV/Hz
A 50 resistor gives 0.9nV/Hz
Or, remember that
k
B
T
r
= 4x10
-21
J (T
r
= 17
o
C)
R
C
v
IN
v
OUT
A/D
DSP
Resistor Noise
Resistor noise gives our filter
a non-zero output when
v
IN
=0
In this simple example, both
the input signal and the
resistor noise obviously have
the same transfer functions
to the output
Since noise has random
phase, we can use any
polarity convention for a
noise source (but we have to
use it consistently)
R
C
v
IN
v
OUT
e
+ -
A/D
DSP
Resistor Noise
What is the thermal noise of the
RC filter?
Lets ask SPICE!
Netlist:
Noise from RC LPF
vin vin 0 ac 1V
r1 vin vout 8kOhm
c1 vout 0 1nF
.ac dec 100 10Hz 1GHz
.noise V(vout) vin
.end
R=8k
C=1nF
v
IN
v
OUT
e
+ -
A/D
DSP
LPF1 Output Noise Density
[Hz]
N
o
i
s
e

S
p
e
c
t
r
a
l

D
e
n
s
i
t
y

(
n
V
/
H
z
)
100
0.01
0.1
1
10
10
1
10
3
10
7
10
5
10
9
20 kHz corner
Hz
Hz
R T k N
r B
nV
3 . 11
nV
4 8
4
0
=
=
=
A/D
DSP
Total Noise
Suppose we want to know the value of v
o
now,
whats the standard deviation error?
(E.g. on the display of a volt-meter connected to v
o
).
Answer:
df jf H TR k v
B o
2
0
2
) 2 ( 4
=
A/D
DSP
Total Noise
Note that noise is integrated in the mean-
squared domain, because noise in a
bandwidth df around frequency f
1
is
uncorrelated with noise in a bandwidth df
around frequency f
2
Powers of uncorrelated random variables add
Squared transfer functions appear in the mean-
squared integral
A/D
DSP
Total Noise
C
T k
df
jfRC
TR k
df jf H TR k v
B
B
B o
=
+
=
=
2
0
2
0
2
2 1
1
4
) 2 ( 4

A/D
DSP
Total Noise
This interesting and somewhat counterintuitive result
means that even though resistors provide the noise
sources, capacitors set the total noise
For a given capacitance, as resistance goes up, the
increase in noise density is balanced by a decrease
in noise bandwidth
C
T k
v
B
o
=
2
A/D
DSP
kT/C Noise
The rms noise voltage of the simplest possible (first
order) filter is k
B
T/C
For 1pF, k
B
T/C = 64 V-rms (at 298K)
1000pF gives 2 V-rms
The noise of a more complex filter is K x k
B
T/C
K depends on implementation and features such as
filter order
A/D
DSP
LPF1 Output Noise
[Hz]
100
0.01
0.1
1
10
10
1
10
3
10
7
10
5
10
9
N
o
i
s
e

S
p
e
c
t
r
a
l

D
e
n
s
i
t
y

(
n
V
/
H
z
)
I
n
t
e
g
r
a
t
e
d

N
o
i
s
e

(

V
r
m
s
)
2Vrms
A/D
DSP
LPF1 Output Noise
Note that the integrated noise essentially
stops growing above 100kHz for this 20kHz
lowpass filter
Beware of faulty intuition which might tempt
you to believe that an 80, 1000pF filter has
lower integrated noise than our 8000,
1000pF filter
A/D
DSP
LPF1 Output Noise
[Hz]
100
0.01
0.1
1
10
10
1
10
3
10
7
10
5
10
9
N
o
i
s
e

S
p
e
c
t
r
a
l

D
e
n
s
i
t
y

(
n
V
/
H
z
)
I
n
t
e
g
r
a
t
e
d

N
o
i
s
e

(

V
r
m
s
)
80, 1000pF
A/D
DSP
LPF1 Output Noise
Of course, an 80, 100,000pF filter has
both the same bandwidth AND lower
integrated noise than our 8000,
1000pF filter
In the analog filter dynamic range game,
the highest capacitance wins
A/D
DSP
LPF1 Output Noise
[Hz]
100
0.01
0.1
1
10
10
1
10
3
10
7
10
5
10
9
N
o
i
s
e

S
p
e
c
t
r
a
l

D
e
n
s
i
t
y

(
n
V
/
H
z
)
I
n
t
e
g
r
a
t
e
d

N
o
i
s
e

(

V
r
m
s
)
80, 100000pF
A/D
DSP
Analog Circuit Dynamic Range
The biggest signal we can ever expect at the output of a circuit
is limited by the supply voltage, V
DD
hence (for sinusoids)
The noise is
So the dynamic range in dB is:
2 2
1
) (
max
DD
V
rms V =
C
T k
K rms V
B
n
= ) (
[pF] in C with [dB] 75 20log
[V/V]
8 ) (
) (
10
max
+
=
= =
K
C
V
T Kk
C V
rms V
rms V
DR
DD
B
DD
n
A/D
DSP
Analog Circuit Dynamic Range
For integrated circuits built in modern CMOS
processes, V
DD
< 3V and C < 1nF (K = 1)
DR < 110dB
For PC board circuits built with old-fashioned 30V
opamps and discrete capacitors of < 100nF
DR < 140dB
A 30dB advantage!
A/D
DSP
Dynamic Range versus Bits
Bits and dB are related:
see quantization noise, later in the course
Hence
110 dB 18 Bits
140 dB 23 Bits
[dB] 6 2 N DR + =
A/D
DSP
Dynamic Range versus Power
Each extra bit corresponds to 6dB
6dB means cutting noise power by 4!
This translates into 4x larger capacitors
To drive these at the same speed, G
m
must increase 4x
Power is proportional to G
m
(for fixed supply and V
dsat
)
In analog circuits that are limited by thermal noise,
1 extra bit costs 4x power
E.g. 16Bit ADC at 200mW 17Bit ADC at 800mW
Do not overdesign the dynamic range of analog circuits!
P.S. What is the cost of an extra bit in a 64Bit adder?
A/D
DSP
Active Filter Example
C
v
IN
v
OUT
R
R
2
2
2
=
=
K
C
T k
v
B
o
( )
sRC
s H
+
=
1
1
Frequency response:
Total noise (see EE240):
Noise depends on filter topology
Opamps contribute yet more noise
A/D
DSP
Behavioral Opamp Model
Specification Example
Gain G 100k
Unity-gain bandwidth f
u
100 MHz
Input refd thermal noise 5 nV/Hz
Beware of flicker noise and input current noise (BJTs).
A/D
DSP
SPICE Analysis
A/D
DSP
Noise Analysis
Opamp noise
dominates in this
example
Opamp adds
significant noise above
filter roll-off
A/D
DSP
Opamp Bandwidth
Minimize opamp bandwidth:
f
u
= 1MHz 7V-rms
f
u
= 10MHz 20V-rms
Of course, the opamp has to
be fast enough to faithfully
realize the 20kHz corner!
A/D
DSP
Frequency Response
A/D
DSP
Tow-Thomas Noise Analysis
A/D
DSP
Tow-Thomas Biquad
A/D
DSP
Bandpass Noise
Noise from the passband
dominates this integral.
Unfortunately the opamp adds
significant additional noise at high frequency
A/D
DSP
RC Filter Reduces BP Noise
We cannot reduce the opamp noise or bandwidth lets filter its noise!
1k / 5nF RC LPF
corner at 32kHz
0.9V rms noise from 5nF is negligible
A/D
DSP
BP Response with RC Filter
RC provides negligible attenuation.
But thats not the point.
Lets look at the noise
Without RC
A/D
DSP
BP Noise after RC Filter
RC filter reduces total noise
from 20V to 5V rms.
(Without opamp noise is 3V rms).
A/D
DSP
BP Dynamic Range
Maximum sinewave input: 7.8V rms
(limited by opamp)
Noise: 5.2V rms (with RC)
Dynamic range: 123dB
No IC with integrated capacitors can
get close to this dynamic range
A/D
DSP
Bandstop Noise
Much lower than at 1kHz,
but much higher bandwidth!
Noise above notch dominates.
Opamp doubles total noise
No notch in the noise response
A/D
DSP
Noise versus Pole Q
R
1
= R
4
= 42k 10k:
Q drops from 30 to 7
R = 10k
R = 42k
A/D
DSP
Noise versus Pole Q
Noise drops by 30/7
from 2.8mV to 1.2mV rms.
rms total noise is approximately
proportional to Q
of course in this circuit the opamp noise
swamps this effect
(this simulation uses noiseless opamps)
A/D
DSP
Noise Summary
Thermal noise is a fundamental property of
(electronic) circuits
Noise is closely related to
Capacitor size and
Power dissipation
In filters, noise is proportional to order, Q, and
depends on implementation
Operational amplifiers can contribute
significantly to overall filter noise
EECS 247 Lecture 5: Filter Syntesis & Group Delay 2002 B. Boser 1
A/D
DSP
Filter Synthesis
Analog filter synthesis
IIR filters
LP, HP, BP, BS
Magnitude response templates
Filter prototypes
Synthesis with biquads
Phase response
Group delay
Step response
All-pass filters
A/D
DSP
Filter Approximation
Objective: Magnitude specification H(s)
Classic IIR Filters
Chebychev 2
Uses zeros for good attenuation but has no passband
ripples. A good all-round combination.
Butterworth
Poles only and no passband ripple. Less ringing in step
response than Chebychev 2.
Elliptic
Passband and stopband ripples. Use this when only
magnitude response counts. Large overshoot in step
response. High Q poles result in high sensitivity.
Bessel
Great step response at the cost of poor attenuation.
A/D
DSP
Design Example
10
4
10
5
10
6
10
7
-120
-100
-80
-60
-40
-20
0
Rp = 3 dB
Rs = 80 dB
fp = 100kHz fs = 1MHz
Frequency [Hz]
M
a
g
n
it
u
d
e

[
d
B
]
Butterworth (N = 5)
Chebychev 2 (N = 4)
Elliptic (N = 3)
A/D
DSP
Matlab Code
fp = 1.0e5; wp = 2*pi*fp;
fs = 1.0e6; ws = 2*pi*fs;
rp = 3;
rs = 80;
% filter prototype
[Nb, Wb] = buttord(wp, ws, rp, rs, 's');
[b, a] = butter(Nb, Wb, 's');
Hb = tf(b, a);
[Nc, Wc] = cheb2ord(wp, ws, rp, rs, 's');
[b, a] = cheby2(Nc, rs, Wc, 's');
Hc = tf(b, a);
[Ne, We] = ellipord(wp, ws, rp, rs, 's');
[b, a] = ellip(Ne, rp, rs, We, 's');
He = tf(b, a);
A/D
DSP
Step response
Slow rise time
Overshoot
Acceptable in some
applications, problematic
in others.
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 10
-5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Butterworth
Chebychev 2
Elliptic
Step Response
Time (sec)
A
m
p
l
i
t
u
d
e
A/D
DSP
2
out
1
i n
Random Data
H
Filter Binary
Data Transmission
0 0.5 1 1.5
x 10
-3
-1.5
-1
-0.5
0
0.5
1
1.5
input
output
A/D
DSP
Eye Diagram
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 10
-4
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Time
A/D
DSP
Increased Data Rate
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
x 10
-4
-1.5
-1
-0.5
0
0.5
1
1.5
input
output
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 10
-5
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Time
A/D
DSP
Group Delay
Nonuniform group delay is one source
of eye closure
Group delay?
A/D
DSP
Consider a continuous time filter with s-
domain transfer function G(s):
The filter input is the sum of two sinewaves at
slightly different frequencies (<<):
Amplitude and Phase Distortion
v
IN
(t) = A
1
sin(t) + A
2
sin[(+) t]
G(j) G(j)e
j()
A/D
DSP
The filter output is:
v
OUT
(t) = A
1
G(j) sin[t+()] +
A
2
G[ j(+)] sin[(+)t+ (+)]
{ ]} [
= A
1
G(j) sin
t +
()
+
{ ]} [
+ A
2
G[ j(+)] sin (+) t +
(+)
+
A/D
DSP
{ ]} [
v
OUT
(t) = A
1
G(j) sin
t +
()
+
{ ]} [
+ A
2
G[ j(+)] sin (+) t +
(+)
+
(+)
+
()+
d()
d

[ ][
1
) ( ]
1 -

d()
d
()
+
()
-
( )

A/D
DSP
If the second term in this equation is non-
zero, then the filters output at frequency
+ is time-shifted differently than the
filters output at frequency
Phase distortion
(+)
+
d()
d
()
+
()
( )
A/D
DSP
If the second term in this equation is zero,
then the filters output at frequency + and
the output at frequency are each delayed in
time by -()/

PD
-()/ is called the phase delay and
has units of time
(+)
+
d()
d
()
+
()
( )
A/D
DSP
Since 0, phase distortion is avoided only if:
Clearly, if ()=k, k a constant, we avoid
phase distortion
This type of filter phase response is called
linear phase
Phase shift varies linearly with frequency
d()
d
()
-
= 0
A/D
DSP

GR
-d()/d=k is called the group delay
and also has units of time

GR
=
PD
implies linear phase
Note: Filters with ()=k+c are also called linear
phase filters, but theyre not free of phase distortion
A/D
DSP
If
GR
=
PD
,
[ )] (
v
OUT
(t) = A
1
G(j) sin t -
GR
+
[
+ A
2
G[ j(+)] sin (+)
)] (
t -
GR
If G( j)=G[ j(+)] for all inputs within the
signal-band, v
OUT
is a scaled, time-shifted replica of
the input, with no amplitude distortion
A/D
DSP
No amplitude distortion:
G( j)=G[ j(+)]
No phase distortion:
GR
=
PD
Neither of these conditions are realizable exactly in
continuous time filters
Real passbands cant have flat amplitude responses
Derivatives of sums of arctangents arent constant
A/D
DSP
Group Delay Comparison
100kHz corner frequency
Chebychev II versus Bessel
A/D
DSP
Magnitude Response
Bode Magnitude Diagram
Frequency [Hz]
M
a
g
n
i
t
u
d
e

(
d
B
)
10
4
10
5
10
6
10
7
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
4th Order Chebychev 2
4th Order Bessel
A/D
DSP
Phase Response
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 10
5
-300
-250
-200
-150
-100
-50
0
Frequency [Hz]
P
h
a
s
e

[
d
e
g
r
e
e
s
]
4th Order Bessel
A/D
DSP
Group Delay
10
4
10
5
10
6
10
7
0
1
2
3
4
5
6
7
Frequency [Hz]
G
r
o
u
p

D
e
la
y

[

s
]
4th Order Bessel
A/D
DSP
Normalized Group Delay
10
4
10
5
10
6
10
7
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
Frequency [Hz]
G
r
o
u
p

D
e
l
a
y

[
n
o
r
m
a
l
i
z
e
d
]
4th Order Bessel
A/D
DSP
Step Response
Step Response
Time (sec)
A
m
p
l
i
t
u
d
e
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 10
-5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
4th Order Bessel
A/D
DSP
Eye Diagrams
Note: the Chebychev output should be scaled to the same peak amplitude as the
output from the Bessel. The Bessel has a clear advantage.
-1 0 1 2 3 4 5 6
x 10
-5
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Time
4th Order Bessel
-1 0 1 2 3 4 5 6
x 10
-5
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Time
4th Order Chebychev
A/D
DSP
Allpass Filters
Delay equalization
Unity magnitude response
arbitrary delay
Can compensate arbitrary phase
distortion (e.g. from a given channel)
A/D
DSP
Second-Order All Pass Filter
j
radius =
P
P
2Q
P
A/D
DSP
Second-Order All Pass Filter
From graphical considerations alone, the
second-order all pass filter has unity
magnitude response at all frequencies
Its phase shift is twice that of its pole
All pass sections cant cancel out the delay of
other filter sections,
But they can add strategic delay to improve the
phase response of a companion filter
A/D
DSP
All Pass Filters
An all pass filter used to make a companion
filters group delay more constant in the filter
passband is called a phase equalizer or
delay equalizer
Group-delay-critical applications frequently
devote as many poles to phase response
reshaping as they devote to magnitude
response shaping
A/D
DSP
All Pass Filters
Phase equalizers are commonly used in
digital data receivers
If youre not sure whether or not you need a
phase equalizer, build one
Start with just as many poles as your magnitude
shaper
CAD tools like MATLABs iirgrpdelay help
synthesize optimal phase equalizers
Unfortunately iirgrpdelay is for sampled data filters
only use the bilinear transform (see later)
A/D
DSP
Magnitude Response
Frequency [Hz]
M
a
g
n
it
u
d
e

(
d
B
)
10
4
10
5
10
6
10
7
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Allpass
Cheby+Allpass
8th Order Bessel
A/D
DSP
Phase Response
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 10
5
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
Frequency [Hz]
P
h
a
s
e

[
d
e
g
r
e
e
s
]
Allpass
Cheby+Allpass
8th Order Bessel
A/D
DSP
Normalized Group Delay
10
4
10
5
10
6
10
7
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
Frequency [Hz]
G
r
o
u
p

D
e
l
a
y

[
n
o
r
m
a
l
i
z
e
d
]
Cheby+Allpass
8th Order Bessel
A/D
DSP
Step Response
Step Response
Time (sec)
A
m
p
l
i
t
u
d
e
0 0.5 1 1.5 2 2.5 3
x 10
-5
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
Allpass
Cheby+Allpass
8th Order Bessel
A/D
DSP
Eye Diagrams
-1 0 1 2 3 4 5 6
x 10
-5
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Time
8th Order Bessel
-1 0 1 2 3 4 5 6
x 10
-5
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Time
4th Order Chebychev with 4th Order Allpass
A/D
DSP
FIR Filter Phase Response
A significant advantage of FIR over IIR filters
is that FIR filters can be realized with linear
phase response
But (with few exceptions) FIR filters are only
practical in the digital domain
A/D
DSP
Summary
Filter design:
Magnitude response
Template
Approximation (matlab) H(s)
Realization with
Cascades of biquads
Sensitivity limits practical designs to <3 sections
Ladder filters next lecture
Phase / group delay
Phase equalization (allpass)
EECS 247 Lecture 6: Ladder Filters 2002 B. Boser 1
A/D
DSP
Higher Order Filter Options
Cascade of Biquads
High-Q poles
High component sensitivity
Ladders
Low sensitivity (Orchard)
Synthesize from LC prototypes
Digital filters
Preferred solution when possible
A/D
DSP
Cascade of Biquads
LPF with
f
pass
= 20 kHz r
pass
= 0.5 dB
f
stop
= 22.05 kHz r
stop
= 50 dB
8
th
order Elliptic Filter
Implementation with Biquads
Goal: maximize dynamic range
Pair poles and zeros
highest Q poles with closest zeros is a good starting point, but not
necessarily optimum
Ordering
lowest Q poles is a good start
A/D
DSP
Bode Diagram
Frequency [Hz]
P
h
a
s
e

(
d
e
g
)
M
a
g
n
it
u
d
e

(
d
B
)
-120
-100
-80
-60
-40
-20
0
10
4
10
5
-720
-540
-360
-180
0
180
Filter Response
Frequency [Hz]
M
agnitude (dB
)
10
4.1
10
4.2
10
4.3
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
A/D
DSP
Pole-Zero Map
Q
pole
f
pole
[kHz]
38. 4389 20.0501
8.2903 19.0959
2.4134 16.0142
0.7130 9.4282
f
zero
[kHz]
70.6923
28.7992
22.8585
21.4663
Pole-ZeroMap
Real Axis
I
m
a
g

A
x
is
-5 -4 -3 -2 -1 0 1 2 3 4 5
x 10
4
-5
-4
-3
-2
-1
0
1
2
3
4
5
x 10
5
A/D
DSP
Biquad Response
Frequency [Hz]
M
a
g
n
i
t
u
d
e

(
d
B
)
10
4
10
5
-50
-40
-30
-20
-10
0
10
Biquad 1
Biquad 2
Biquad 3
Biquad 4
A/D
DSP
Intermediate Outputs
Biquad 1
Frequency [Hz]
M
a
g
n
itu
d
e
(d
B
)
10
4
10
5
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
Biquads 1, 2
Frequency [Hz]
M
a
g
n
itu
d
e
(d
B
)
10
4
10
5
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Biquads 1, 2, 3
Frequency [Hz]
M
a
g
n
itu
d
e
(d
B
)
10
4
10
5
-120
-100
-80
-60
-40
-20
0
Biquads 1, 2, 3, & 4
Frequency [Hz]
M
a
g
n
itu
d
e
(d
B
)
10
4
10
5
-120
-100
-80
-60
-40
-20
0
20
A/D
DSP
Frequency [Hz]
M
a
g
n
itu
d
e
(
d
B
)
10
4.2
10
4.3
-60
-50
-40
-30
-20
-10
0
Sensitivity
Component variation in Biquad 4:
Increase
p
by 1%
Decrease
z
by 1%
Frequency [Hz]
M
agnitude (dB
)
10
4.27
10
4.28
1 0
4.29
10
4.3
10
4.31
-7
-6
-5
-4
-3
-2
-1
0
1
Frequency [Hz]
M
agnitude (dB
)
10
4. 3
10
4.4
-60
-55
-50
-45
-40
High Q poles High sensitivity
in Biquad realizations
A/D
DSP
Ladder Filters
Ladder example
Table
De-normalization
State variable synthesis
Transmission zeros
Implementation
Tuning
Gm-C
A/D
DSP
LC Ladder Synthesis
CAD tool
Filter table
A. Zwerev, Handbook of filter synthesis, Wiley, 1967.
R. Saal, Handbook of filter synthesis, AEG-Telefunken, 1979.
A. B. Williams and F. J. Taylor, Electronic filter design, 3
rd
edition,
McGraw-Hill, 1995.
Example:
f
corner
= 10MHz, f
stop
= 20MHz, R
p
= 2dB, R
s
=25dB
5
th
order Butterworth (from Matlab)
A/D
DSP
Filter Table
Williams and Taylor, p. 11.3
Denormalization:
Multiply all L, C with
L
r
= R/
corner
= 14.1 nH
C
r
= 1/R/
corner
= 14.1 nF
R is the value of the source
and termination resistor
(choose both 1 for now)
A/D
DSP
SPICE Verification
-6 dB passband attenuation
due to termination
10MHz 100MHz 1MHz
V
1
V
3
V
5
i
2
i
4
A/D
DSP
State Space Description
[ ]
[ ]
[ ]
=
=
=
=
=
t
s
i
R
V
i
sC
V
V V
sL
i
i i
sC
V
V V
sL
i
i
R
V V
sC
V
5
4
5
5
5 3
4
4
4 2
3
3
3 1
2
2
2
1
1
1
1
1
1
1
1
sRC V
V 1
1
2
=
RC Integrator:
A/D
DSP
Normalize
[ ] [ ]
[ ]
[ ] [ ]
( ) ( )
2
*
4
4 2
*
2
2
5
*
4
5
5
5 3 *
4
5 3
4
*
4
4 2
*
3
3
3 1 *
2
3 1
2
*
2
*
2 1
1
1
and with
1
1
1
1
1
R
L
C
R
L
C
R
V
R
V
sC
V
V V
R sC
V V
sL
R
V
V V
R sC
V
V V
R sC
V V
sL
R
V
R
V
R
V V
sC
V
t
s
i
= =
=
= =
=
= =
=
[ ]
[ ]
[ ]
=
=
=
=
=
t
s
i
R
V
i
sC
V
V V
sL
i
i i
sC
V
V V
sL
i
i
R
V V
sC
V
5
4
5
5
5 3
4
4
4 2
3
3
3 1
2
2
2
1
1
1
1
1
1
1
1
*
4 4
*
2 2
R i V
R i V
=
=
A/D
DSP
Synthesize
A/D
DSP
Negative Resistors
Single ended Differential
A/D
DSP
Frequency Response
A/D
DSP
Scale Node Voltages
Scale V
o
by factor s
A/D
DSP
Noise
Total noise: 1.4 V rms
(noiseless opamps)
Thats excellent, but the
capacitors are very
large (and the resistors
small).
Suppose our application
calls for 140 V rms
A/D
DSP
Scale to Meet Noise Target
Scale capacitors and resistors
to meet noise objective
s = 10
-4
Noise: 141 V rms (noiseless opamps)
A/D
DSP
Completed Design
A/D
DSP
Sensitivity
C
1
made (arbitrarily) 50%(!) larger than
its nominal value
0.5 dB error at band edge
3.5 dB error in stopband
Looks like very low sensitivity
More analysis needed (Monte Carlo?)
A/D
DSP
Transmission Zeros
i
C1
i
Ca
( )

+
+ = +
=
=
1
3 1 1 1
1 1 1
3 1
) (
C C
C
V V C C s i i
V sC i
V V sC i
a
a
a C a
C
a a
V
1
V
3
V
5
A/D
DSP
Filter Table
5
th
order Chebychev II
Williams & Taylor,
p. 11.112
50dB stopband attenuation
A/D
DSP
Equivalent Circuit
i
a V
3
C
1
*
( )
( )
1
1
*
1
3 1
*
1
1
3 1 1 1
and : with
C C
C
a C C C
aV V sC
C C
C
V V C C s i i i
a
a
a
a
a
a C a
+
= + =
=
+
+ = + =
V
1
V
3
V
5
A/D
DSP
Realization with Integrator
( )
( )
( )

+
=
+
+
+
=
+
+
=
3 *
2 1
1
3
1
2
1
1
3 2
1
1
1
1
1
1
V sC
R
V
R
V V
C C s
V
C C
C
i
R
V V
C C s
aV i
R
V V
C C s
V
a
s
i
a
a
a
L
s
i
a
L
s
i
a
A/D
DSP
Active RC Simulation
A/D
DSP
Summary
Higher Order Filter Realization
Cascade of Biquads
High sensitivity often problem for N>4
Ladder Filters
Based on LC prototypes
Low sensitivity
Active RC simulation retains low sensitivity
Many implementation choices:
Active RC, Gm-C, MOSFET-C
EECS 247 Lecture 7: Finite Bandwidth 2002 B. Boser 1
A/D
DSP
Implementation Issues
Component spread
Sensitivity
Tuning
Noise
Finite Gain
Finite Bandwidth

A/D
DSP
Finite Bandwidth
Model finite bandwidth only
DC gain infinite
(keep things manageable &
stand a chance to actually
learn something from the
calculation)
Errors:
DC Gain: minor problem
Pole: phase shift
Whats the effect on a filter?
{
RC
s
s V
V
o
u o
u o
u o
i
o
1
with
1
1
pole
error gain C D
ideal
=
+
+
=

43 42 1
43 42 1
s
u

A/D
DSP
Effect on Filter Response
! for Solve
1 : Hence
1 Filter Actual
) ( Filter Ideal
with
1
1
Integrator Actual
Integrator Ideal
actual
2
actual
actual ideal
2
ual filter_act
al filter_ide
2
2
int_actual
int_ideal
actual
ideal
p
p
p
p p
p
s
s H
s H
p
p
s
s
H
s
H
p s
p s
u o u
o
o
+ =

+

=
+

=
=
=


A/D
DSP
Solving for p
actual
,
Q) (high

2
2 2
actual
ideal
a i
a a
i i
a a
i i
p
j p
j p

>>
>>
>>
=
+ =
+ =
( )
+ = +

+ =
+
+ + = +
2
corner
2
2
2 2
2
2
2
2
2
2
2
2 1
assuming 2 1
2 using 2 1
1
1
1

i i
i a
a
i i
a
i
a
i i
a
i
a
i
a
i a
a
a
a a
a i
a a
a a i i
Q
Q
Q Q
j
j j
A/D
DSP
Effect of Finite Amplifier Bandwidth
Solution:
Very fast amplifier, or
Compensation circuit

2
corner
2 1

i i a
Q
j
Q enhancement peaking in response (or instability)

corner
corner
200
need 1%) by Q increase hence (and, 1% reduce To
8 . 0
MHz 100
MHz 1
10 2 1
MHz 100 MHz, 1 10,
: Example
Qf f
f f Q
u
i i a
u
>
< <
=

= = =

A/D
DSP
Pole-Zero Cancellation
( )
( )
+
+
+
+
=
+ + +
+
=
+ + +
+
=
+ +
+
+
=
u
o
u
z
z
u
o
o
z
u u
o
z o
z
u u
z
z
u u
z
R
R
s
C sR
s
R
R s
C sR
s
C sR
RC
s
C sR
sRC
C sR
s s
sRC
C sR
H

1
1
1
1
1
1
1 1
1
1
1
1
1 1
1 1
1
1 be should error,
response ideal
4 4 4 4 3 4 4 4 4 2 1
3 2 1
o u
u
z
u
o
u
z
C
C R
R
R

>>
=
+
assuming
1
R
1
1
Need
z
EECS 247 Lecture 8: Sampling 2002 B. Boser 1
A/D
DSP
Sampling and Aliasing
Any continuous time signal can be sampled and
processed in the sampled-data domain
A/D converters look at signals at only discrete points in time
Computer models of continuous systems must operate at
discrete time intervals
Even analog filters can use continuous or sampled time
signal representations
Multiple continuous time signals can yield exactly the
same sampled data signal aliasing
Lets look at samples taken at 1sec intervals of several
sinusoidal waveforms
A/D
DSP
Sampling Sinewaves
time
v
o
l
t
a
g
e
v(t) = sin [2(101000)t]
T = 1s
f
s
= 1/T = 1MHz
f
x
= 101kHz
A/D
DSP
Sampling Sinewaves
time
v
o
l
t
a
g
e
v(t) = - sin [2(899000)t]
T = 1s
f
s
= 1MHz
f
x
= 899kHz
A/D
DSP
Sampling Sinewaves
time
v
o
l
t
a
g
e
v(t) = sin [2(1101000)t]
T = 1s
f
s
= 1MHz
f
x
= 1101kHz
A/D
DSP
Aliasing
Multiple continuous time signals can produce
identical series of sampled voltages
The translation of signals from Nf
S
f
IN
down
to f
IN
is called aliasing
Sampling theorem: f
s
> 2f
B
If aliasing occurs, no signal processing
operation downstream of the sampling
process can recover the original continuous
time signal
If you dont like it, sample faster!
A/D
DSP
Time vs Frequency Domain
Time Frequency
multiply convolve
T
f
S
=1/T
f
B
A/D
DSP
Nomenclature
Continuous time signal x(t)
Sampling interval T
Sampling frequency f
s
= 1/T
Sampled signal x(kT) = x(k)
time
x(kT) x(k)
T
x(t)
A/D
DSP
Sampled Signal Properties
Its obvious from the preceding slides that the
frequency content of a continuous signal can
be grossly distorted by sampling
What do we know about the relationships
between x(t) and x(k)?
Well assume that x(t) is stationary; that is, its
mean is constant and its autocorrelation R(t
1
,t
2
)
depends only on the time difference t
1
-t
2
A/D
DSP
Sampled Signal Properties
If x(t) is stationary, then
(Athanasios Papoulis, Signal Analysis, 1977, Section 9.4.):
x(k) is also stationary
Sampling doesnt change the mean: E{x(k)}=E{x(t)}
E{} is the expectation operator
Sampling doesnt change energy:
E{[x(k)]
2
}= E{[x(t)]
2
}
Continuous time energy will show up someplace in
the frequency domain after sampling
Aliasing may move continuous signal frequency
components to wrong frequencies
A/D
DSP
Anti-Aliasing Filter
time time
f
s
frequency time
frequency time
Anti-Aliasing Filter
Aliasing
f
s
f
s
Filtered Spectrum
f
B
f
B

A/D
DSP
Sampled Signals
Sampled data signals are valid only at
sampling instances
In an actual circuit, the signal transitions to
the new value between sampling instances
The value between sampling instances is
insignificant and often erroneous (e.g.
amplifier slewing distortion)
A/D
DSP
Zero-Order Hold
Reconstructs CT signal
from SD signal
Frequency response?
0 0.5 1 1.5 2 2.5 3 3.5
x 10
-5
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Time
A
m
p
lit
u
d
e
sampled data
after ZOH
A/D
DSP
Zero-Order Hold
( )
d
d
d
fT j
d
d
d
sT
d
sT
d
e
fT
fT
sT
e
sT
e
sT
2
2 sin
1
1
Step response Laplace transform
T
d
time
T
d
0
A/D
DSP
0 0.5 1 1.5 2 2.5 3
x 10
6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency
M
a
g
n
i
t
u
d
e
sampled signal
sinc
zoh signal
Spectrum of Reconstructed Signal
Reconstructed
signal
SD signal:
periodic spectrum
Sinc
T
d
= T = 1/f
s
A/D
DSP
0 0.5 1 1.5 2 2.5 3
x 10
6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency
M
a
g
n
i
t
u
d
e
sampled signal
sinc
zoh signal
Spectrum of Reconstructed Signal
Reconstructed
signal
SD signal:
periodic spectrum
Sinc
T
d
= 0.5T
A/D
DSP
Summary
Quantization in Time:
Continuous time (CT) vs Sampled Data (SD)
Sampling theorem: f
s
> 2f
B
IF sampling theorem is met, CT signal can be
recovered from SD signal without loss of
information
ZOH reconstructs CT from SD signal
EECS 247 Lecture 9: SC Integrators 2002 B. Boser 1
A/D
DSP
Switched-Capacitor Filters
Analog sampled-data filters:
Continuous amplitude
Quantized time
Applications:
Oversampled A/D and D/A converters
Analog front-ends (CDS, etc)
Standalone filters
E.g. National Semiconductor LMF100
Replaced by ADC + DSP in many cases
A/D
DSP
Switched-Capacitor Resistor
Capacitor C is the
switched capacitor
Non-overlapping clocks
1
and
2
control switches
S1 and S2, respectively
v
IN
is sampled at the
falling edge of
1
S
Why is this a resistor?
v
IN
v
OUT
C
S1 S2
1

2
2
T=1/f
S
A/D
DSP
Switched-Capacitor Resistors
v
IN
v
OUT
C
S1 S2
1

2
2
T=1/f
S
The charge transferred
from v
IN
to v
OUT
each
sample period is:
The average current
flowing from v
IN
to v
OUT
is:
Q = C(v
IN
v
OUT
)
i = f
S
C(v
IN
v
OUT
)
A/D
DSP
Switched-Capacitor Resistors
v
IN
v
OUT
C
S1 S2
1

2
2
T=1/f
S
With the current through the
switched capacitor resistor
proportional to the voltage across it,
the equivalent switched capacitor
resistance is:
i = f
S
C(v
IN
v
OUT
)
R
EQ
=
1
f
S
C
Of course this current flows in
burststhink of big electrons.
A/D
DSP
Switched-Capacitor Filter
Lets build an SC filter
Well start with a simple RC LPF
Replace the physical resistor by
an equivalent SC resistor
3-dB bandwidth:
v
IN
v
OUT
C
1
S1 S2
1

2
C
2
0
=
1
R
EQ
C
2
= f
S
C
1
C
2
v
OUT
C
2
R
EQ
v
IN
A/D
DSP
Switched-Capacitor Filters
In SCFs, all critical frequencies track the sampling
frequency
Crystal oscillators for f
S
are stable to 10ppm/C
RC products used in active-RC filters can be tuned, but RCs
in active-RC filters dont track together nearly as well
Capacitor ratios in monolithic filters are perfectly
stable over time and temperature
Capacitor ratios cant be trimmed easily
The trick is to achieve initial ratio accuracies of 1000ppm
out of double-poly CMOS processes
A/D
DSP
Transient Analysis
SC response:
extra delay and steps with
finite rise time. Impractical
No problem
exaggerated
A/D
DSP
Transient Analysis
ZOH
ZOH: pick signal after settling
(usually at end of clock phase)
Adds delay and sin(x)/x distortion
When in doubt, use a ZOH in
periodic ac simulations
A/D
DSP
Periodic AC Analysis
A/D
DSP
Magnitude Response
1. RC filter output
2. SC output after ZOH
3. Input after ZOH
4. Corrected output
(2) over (3)
periodic with f
s
Identical to RC for f<<f
s
/2
A/D
DSP
Periodic AC Analysis
SPICE frequency analysis
ac linear, time-invariant circuits
pac linear, time-variant circuits
SpectreRF statements
V1 ( Vi 0 ) vsource type=dc dc=0 mag=1 pacmag=1
PSS1 pss period=1u errpreset=conservative
PAC1 pac start=1 stop=1M lin=1001
Output
Divide results by sinc(f/f
s
) to correct for ZOH distortion
A/D
DSP
Spectre Circuit File
rc_pac
simulator lang=spectre
ahdl_include "zoh.def"
S1 ( Vi c1 phi1 0 ) relay ropen=100G rclosed=1 vt1=-500m vt2=500m
S2 ( c1 Vo_sc phi2 0 ) relay ropen=100G rclosed=1 vt1=-500m vt2=500m
C1 ( c1 0 ) capacitor c=314.159f
C2 ( Vo_sc 0 ) capacitor c=1p
R1 ( Vi Vo_rc ) resistor r=3.1831M
C2rc ( Vo_rc 0 ) capacitor c=1p
CLK1_Vphi1 ( phi1 0 ) vsource type=pulse val0=-1 val1=1 period=1u
width=450n delay=50n rise=10n fall=10n
CLK1_Vphi2 ( phi2 0 ) vsource type=pulse val0=-1 val1=1 period=1u
width=450n delay=550n rise=10n fall=10n
V1 ( Vi 0 ) vsource type=dc dc=0 mag=1 pacmag=1
PSS1 pss period=1u errpreset=conservative
PAC1 pac start=1 stop=3.1M log=1001
ZOH1 ( Vo_sc_zoh 0 Vo_sc 0 ) zoh period=1u delay=500n aperture=1n tc=10p
ZOH2 ( Vi_zoh 0 Vi 0 ) zoh period=1u delay=0 aperture=1n tc=10p
A/D
DSP
ZOH Circuit File
// Copy from the SpectreRF Primer
module zoh (Pout, Nout, Pin, Nin) (period, delay,
aperture, tc)
node [V,I] Pin, Nin, Pout, Nout;
parameter real period=1 from (0:inf);
parameter real delay=0 from [0:inf);
parameter real aperture=1/100 from (0:inf);
parameter real tc=1/500 from (0:inf);
{
integer n; real start, stop;
node [V,I] hold;
analog {
// determine the point when aperture begins
n = ($time() - delay + aperture) / period +
0.5;
start = n*period + delay - aperture;
$break_point(start);
// determine the time when aperture ends
n = ($time() - delay) / period + 0.5;
stop = n*period + delay;
$break_point(stop);
// Implement switch with effective series
// resistence of 1 Ohm
if ( ($time() > start) && ($time() <= stop))
I(hold) <- V(hold) - V(Pin, Nin);
else
I(hold) <- 1.0e-12 * (V(hold) - V(Pin, Nin));
// Implement capacitor with an effective
// capacitance of tc
I(hold) <- tc * dot(V(hold));
// Buffer output
V(Pout, Nout) <- V(hold);
// Control time step tightly during
// aperture and loosely otherwise
if (($time() >= start) && ($time() <= stop))
$bound_step(tc);
else
$bound_step(period/5);
}
}
A/D
DSP
Switched-Capacitor Noise
The resistance of switch
S1 produces a noise
voltage on C with
variance kT/C
The corresponding
noise charge is
Q
2
=C
2
V
2
=kTC
This charge is sampled
when S
1
opens
v
IN
v
OUT
C
S1 S2
1

2
2
T=1/f
S
A/D
DSP
The resistance of switch
S2 contributes to an
uncorrelated noise
charge on C at the end
of
2
The mean-squared
noise charge
transferred from v
IN
to
v
OUT
each sample
period is Q
2
=2kTC
v
IN
v
OUT
C
S1 S2
1

2
2
T=1/f
S
A/D
DSP
The mean-squared noise current due to S1 and S2s kT/C noise is :
This noise is approximately white (see next slide) and distributed
between 0 and f
s
/2 (noise spectra are single sided by convention)
The spectral density of the noise is:
The noise from an SC resistor equals the noise from a physical
resistor with the same value!
( )
2
2
2
2
s B s
TCf k Qf i = =
C f
R
R
T k
TCf k
TCf k
f
i
s
EQ
EQ
B
s B
f
s B
s
1
using
4
4
2
2
2 2
= = = =

A/D
DSP
SC Resistor Noise Spectrum
S
y
(f)
C
R
sw
4k
B
TR
sw
f
s
( )
C
T k
df f S
f
T
C R
T
a
fT e
e
f C
T k
f S
r B
y
s sw
a
a
s
r B
y
s
f
=
= =
+
2
0
2
2
) (
1
and
2 cos 1 1
1 2
) (
0 0.1 0.2 0.3 0.4 0.5

-4
-3
-2
-1
0
1
2
3
4
Normalized Frequency f/f
s
N
o
r
m
a
l
i
z
e
d

N
o
i
s
e

D
e
n
s
i
t
y

S
(
f
)
/
(
2
k
T
/
C
)
T/ = 1
T/ = 3
Noise essentially white for T/t > 3
Settling constraints ensure that this condition
is usually met in practice
Note: This is the noise density of an SC
resistor only. The noise density from an SC
filter is usually not white.
A/D
DSP
Periodic Noise Analysis
PSS pss period=100n maxacfreq=1.5G errpreset=conservative
PNOISE ( Vrc_hold 0 ) pnoise start=0 stop=20M lin=500 maxsideband=10
ZOH1
T = 100ns
ZOH1
T = 100ns
S1
R
100kOhm
R
100kOhm
C
1pF
C
1pF
PNOISE Analysis
sweep from 0 to 20.01M (1037 steps)
PNOISE1
Netlist
ahdl_include "zoh.def" ahdl_include "zoh.def"
Vclk
100ns
Vrc Vrc_hold
Sampling Noise from SC S/H
C1
1pF
C1
1pF
C1
1pF
C1
1pF
R1
100kOhm
R1
100kOhm
R1
100kOhm
R1
100kOhm
Voltage NOISE
VNOISE1
Netlist
simOptions options reltol=10u vabstol=1n iabstol=1p simOptions options reltol=10u vabstol=1n iabstol=1p simOptions options reltol=10u vabstol=1n iabstol=1p simOptions options reltol=10u vabstol=1n iabstol=1p
A/D
DSP
Sampled Noise Spectrum
Density of sampled noise
with sinc distortion.
Normalized density of
sampled noise, corrected for
sinc distortion.
A/D
DSP
Total Noise
Sampled noise in
0 f
s
/2: 62.2V rms
(expect 64V for 1pF)
A/D
DSP
Opamps versus OTA
Low impedance output
Can drive R-loads
Good for RC filters,
OK for SC filters
Extra buffer adds complexity,
power dissipation
High impedance output
Cannot drive R-loads
Ideal for SC filters
Simpler than Opamp
A/D
DSP
Opamps versus OTA Noise
Opamp and switch noise add OTA contributes no excess noise
(actual designs can increase noise)
+ =
switch
noise
2
R
1
R
C
kT
v
oT
C
kT
v
oT
=
2
A/D
DSP
Amplifier Bandwidth Requirements
corner
corner
corner
00 0 1 ... 50
: Filter CT
200 ... 16
100 ... 8
2
2
10
2
1 1
accuracy settling Bit 16 for
10
1
10
T
: Filter SC
f f
f f
f f
f f f
f
f
u
u
s
s s u
u u
s
=
=
=

= =
=
+
SC filters have comparable or

slower amplifier bandwidth
requirements than CT filters
A/D
DSP
SC Filter Summary
Pole and zero frequencies proportional to
s
Capacitor ratios
High accuracy and stability in response
Low time constants realizable without large R, C
Compatible with transconductance amplifiers
No excess opamp noise
Reduced circuit complexity, power
Amplifier bandwidth requirements comparable to CT
filters
o Catch: Sampled data filter aliasing
EECS 247 Lecture 10: SC Filter Frequency Response 2002 B. Boser 1
A/D
DSP
SC Filter Frequency Response
Sampled data (and hence SC) filter responses
are periodic
CT and SD responses agree only for f << f
s
Derive exact SD frequency response
RC SC example
z-transform
SC integrator styles
A/D
DSP
RC / SC Bandpass
phi1 phi1 phi1
phi2 phi2
Cs = 6.28pF
-1M
fo = 10kHz
Q = 10
Cint = 10pF
Cs = 6.28pF
Cd = 628fF
Cint = 10pF Cint = 10pF
phi1 phi1 phi1
phi2 phi2
Cd = 628fF
phi1 phi1 phi1
phi2 phi2
Cs = 6.28pF
Vo_lp_sc
Vo_bp_sc
-1M
Cs
fs = 100kHz
CLK1
RC / SC Biquad Comparison
Vin
V1
ac = 1V
V1
ac = 1V
phi1 phi1 phi2
phi2 phi1
6.28pF
Periodic AC Analysis PAC_lin
sweep from 0 to 200k (500 steps)
PAC_lin
sweep from 0 to 200k (500 steps)
Periodic AC Analysis PAC_log
log sweep from 10 to 200k (500 steps)
PAC_log
PAC_log
PAC_log
-1M -1M -1M -1M -1M -1M
R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm R = -1.592MOhm R = -1.592MOhm R = -1.592MOhm R = -1.592MOhm R = -1.592MOhm R = -1.592MOhm R = -1.592MOhm R = -1.592MOhm
Cint = 10pF Cint = 10pF Cint = 10pF Cint = 10pF Cint = 10pF
R * Q = 15.92MOhm
R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm R = 1.592MOhm
Vo_bp_rc Vo_lp_rc
Cint = 10pF Cint = 10pF Cint = 10pF Cint = 10pF
Netlist
ahdl_include "zoh.def" ahdl_include "zoh.def" ahdl_include "zoh.def" ahdl_include "zoh.def" ahdl_include "zoh.def" ahdl_include "zoh.def" ahdl_include "zoh.def" ahdl_include "zoh.def" ahdl_include "zoh.def" ahdl_include "zoh.def" ahdl_include "zoh.def" ahdl_include "zoh.def" ahdl_include "zoh.def" ahdl_include "zoh.def" ahdl_include "zoh.def" ahdl_include "zoh.def"
ZOH1
T = 10us
ZOH2
T = 10us
phi1
A/D
DSP
Frequency response
CT bandpass has zero
at finfinity
Where did that zero go
in the SC filter?
Note: f
s
/2 would be a
reasonable place!
RC Filter
SC Aliases
A/D
DSP
Non-Inverting SC Integrator
phi1a phi1a phi2b
Cs
1pF
Ci
1pF
Gm = 50uS
Vo1 Vo1
Vi
VS1
1V
150kHz
fs = 1MHz
CLK1
Non-Inverting SC Integrator
Transient Analysis
to 3us
phi1 phi2
phi1c phi1c
phi2c
Vo2 Vo2 Vo2 Vo2
A/D
DSP
Transient Analysis
A/D
DSP
Difference Equation
1
Q
s(kT)
= C
s
V
i(kT)
Q
i(kT)
= Q
i(kT-T/2)
2
Q
s(kT+T/2)
= 0 Q
i(kT+T/2)
= Q
i(kT)
+ Q
s(kT)
= Q
i(kT-T/2)
+ Q
s(kT)
With V
o
= Q
i
/C
i
and V
i
= Q
s
/C
s
V
o2(kT+T/2)
= V
o2(kT-T/2)
+ (C
s
/C
i
) V
i(kT)
A/D
DSP
Laplace Transform
V
o2(kT+T/2)
= V
o2(kT-T/2)
+ (C
s
/C
i
) * V
i(kT)
Laplace Transform
) ( ) ( ) (
2
2
2
2
s V
C
C
e s V e s V
i
i
s
T
s
o
T
s
o
+ =
+
A/D
DSP
z-Transform
1
1
1
1 inverting_ - non int_
1
2
2 inverting_ - non int_
1
2 2
2 2
2
2
2
2
1 ) (
) (
) (
1 ) (
) (
) (
) ( ) ( ) (
) ( ) ( ) (
) ( ) ( ) (
2
1
2
1
2
1
2
1
= =
= =
+ =
+ =
+ =
z
z
C
C
z V
z V
z H
z
z
C
C
z V
z V
z H
z z V
C
C
z z V z V
z V
C
C
z z V z z V
e z
s V
C
C
e s V e s V
i
s
i
o
i
s
i
o
i
i
s
o o
i
i
s
o o
sT
i
i
s
T
s
o
T
s
o
Note: the derivation assumes that
the output is taken at the end of
phase 2. If, as is often the case,
the output is used only at the end
of the next phase 1, the
numerator is z
-1
.
Ref: Oppenheim and Schafer,
Discrete-Time Signal Processing,
Chapter 4
A/D
DSP
Frequency Response
jfRC
f H
f f fT
jfT C
C
fT j C
C
fT j fT fT j fT C
C
z z C
C
z
z
C
C
z H f H
s
fT j fT e z e z
e z
jfT jfT
jfT
2
1
) (
or 1 for
2
1
sin 2
1
sin cos sin cos
1
1
1
) ( ) (
RC
int
s
int
s
int
s
sin cos
int
s
1
int
s
int_ni SC_ni
2
1
2
1
2
1
2
2
1
2
=
<< <<
=
+ +
=
=
=
+ = =
=
A/D
DSP
Inverting SC Integrator
fT j C
C
f H
z
z
C
C
z H
sin 2
1
) (
1
) (
int
s
SC_i
1
int
s
int_i
2
1
=
Note: H
int_i
(z) assumes that the output is used at
the end of phase 2. If, as is often the case, the
output is used already at the end of phase 1, the
numerator is 1.
If, as is normally the case, circuit topologies are
used where inverting and non-inverting SC
integrators alternate, this is not an issue.
Cs
1pF
Ci
1pF
Gm = 50uS
Vi
VS1
1V
150kHz
fs = 1MHz
CLK1
Inverting SC Integrator
Transient Analysis
to 3us
phi2 phi2
Vo1 Vo1 Vo1 Vo1 Vo1 Vo1 Vo1 Vo1
phi1c phi1c phi1c phi1c phi1c phi1c phi1c phi1c
phi2c phi2c phi2c phi2c
Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2
A/D
DSP
Transient Analysis
A/D
DSP
General SC Integrator
( ) ( ) ( ) ( )
( ) ( ) ( ) ( ) z V
C
C
z V
z
z
C
C
z V
z
z
C
C
z V
z V
C
C
z V
z C
C
z V
z
z
C
C
z V
i
i
i
i
i
i
o
i
i
i
i
i
i
o
3
3
2 1
2
1 1
1
2
3
3
2 1
2
1 1
1
1
1
1 1
1
1
1
2
1
2
1
C1 C1 C1 C1 C1 C1 C1 C1
Ci Ci Ci Ci
Vo1 Vo1 Vo1 Vo1 Vo1 Vo1 Vo1 Vo1 Vo1 Vo1 Vo1 Vo1
Vi1 Vi1 Vi1 Vi1 Vi1 Vi1 Vi1 Vi1
phi1
phi1 phi1 phi1 phi1 phi1 phi1 phi1 phi1
phi2
phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2
phi1c phi1c phi1c phi1c phi1c phi1c phi1c phi1c phi1c phi1c phi1c phi1c
phi1
phi2c phi2c phi2c phi2c phi2c phi2c
phi2
Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2 Vo2
C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2
phi1
phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2
phi1
phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2 phi2
C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3
Vi2 Vi2 Vi2 Vi2 Vi2 Vi2 Vi2 Vi2 Vi2 Vi2 Vi2 Vi2 Vi2 Vi2 Vi2 Vi2
Vi3 Vi3 Vi3 Vi3 Vi3 Vi3 Vi3 Vi3 Vi3 Vi3 Vi3 Vi3 Vi3 Vi3 Vi3 Vi3
A/D
DSP
Integrator Signal Flow Diagram
1
int
1
1 1
z C
( )
1
3
1

z C
1
1

z C
2
C
) (
1
z V
o
) (
2
z V
i
) (
1
z V
i
) (
3
z V
i
A/D
DSP
SFD of SC BP
1
int
1
1 1
z C
1
int
1
1 1
z C
1
z C
s s
C
1
1
) (z V
LP
) (z V
BP
) (z V
i
s
C
d
C
A/D
DSP
Frequency Response of SC BP
( )
( )
( )
Q C
C
f C
C
f
Q
f
z
Q f
f
z
z z
V
V
V C
z
z
C
V
V C V C V C
z C
V
d
s
s
s
s s
s
s i
BP
BP s LP
BP d LP s i s BP
1
and : using
1
2
1
1
H
helps) rule s (Mason' work some
1
1
1
1 1
0
int
0 0
0
0
2
BP
1
1
int
1
int
= =
+
+ +
= =
=
+ +

A/D
DSP
s-Plane versus z-Plane
j
s-plane
z-plane
A/D
DSP
z-Plane
In the z-plane
The distance from the pole to the unit circle
is inversely proportional to pole Q
The angle to the pole is equal to 360 (or
2 radians) times the ratio of the pole
frequency to the sampling frequency
How do poles and zeroes in the
complex z-plane relate to frequency
response?
A/D
DSP
z-Domain Frequency Response
The j axis maps onto the
unit circle
Particular values:
f = 0 z = 1
f = f
s
/2 z = -1
The frequency response is
obtained by evaluating H(z)
on the unit circle at
z = e
jT
= cos(T)+jsin(T)
Once z=1 (f
s
/2) is reached,
the frequency response
repeats, as expected
(cos(T),sin(T))
2f
f
S
f = 0
f = f
s
/2
A/D
DSP
Pole-Zero Map in z-Plane
Pole-ZeroMap
Real Axis
I
m
a
g

A
x
i
s
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
The zero from finfinity
is mapped to z=0, a
non-physical frequency.
This explains the poor
attenuation at f=f
s
/2.
A/D
DSP
Frequency Response
Bode Diagram
Frequency (rad/sec)
P
h
a
s
e

(
d
e
g
)
M
a
g
n
it
u
d
e

(
d
B
)
-60
-50
-40
-30
-20
-10
0
10
20
fs/f0 = 1000
100
10
10
2
10
3
10
4
10
5
-270
-225
-180
-135
-90
A/D
DSP
Frequency Warping
Frequency response
Continuous time (s-plane): imaginary axis
Sampled time (z-plane): unit circle
Continuous to sampled time transformation
Should map imaginary axis onto unit circle
How do SC integrators map frequencies?
fT j C
C
z
z
C
C
z H
sin 2
1
1
) (
int
s
1
int
s
SC
2
1
=

A/D
DSP
CT SC Integrator Comparison
CT Integrator
SC Integrator

RC
jf
s
s H
2
1
1
) (
RC
=
=
T f j C
C
z
z
C
C
z H
SC
sin 2
1
1
) (
int
s
1
int
s
SC
2
1
=
s s
C f
C
RC
int
= =
Identical time constants:
Compare: H
RC
(f
RC
) = H
SC
(f
SC
)
=
s
SC s
RC
f
f f
f
sin
A/D
DSP
LDI Integration
=
s
SC s
RC
f
f f
f
sin
RC frequencies up to f
s
/
map to physical (real) SC
frequencies
Frequencies above f
s
/ do
not map to physical
frequencies
Mapping is symmetric about
f
s
/2 (aliasing)
Accurate only for f
RC
<< f
s
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
f
RC
/ f
s
fS
C

/

fs
A/D
DSP
Types of Integration
Lossless discrete integration
Bilinear integration
(Delta rule)
(and many others, e.g. Euler,
Runge Kutta, Gear, )
Time
S
i
g
n
a
l

A
m
p
l
i
t
u
d
e
Time
S
i
g
n
a
l

A
m
p
l
i
t
u
d
e
( )
1
1
2
1
=
z
z
z H
( ) ( ) ( ) ( ) [ ] T kT v kT v
T
T kT v kT v
i i o o
+ + =
2
A/D
DSP
Bilinear Transform
Bilinear integrator
Frequency translation
( ) ( ) ( ) ( ) [ ]
[ ] [ ]
( )
1
1
1 1
1
1
2 ) (
) (
) ( 1
2
) ( 1
2
+
= =
+ =
+ + =
z
z T
z V
z V
z H
z V z
T
z V z
T kT v kT v
T
T kT v kT v
i
o
i o
i i o o
( )
=
=
=
=
s
SC s
RC
e z
SC
jf s
f
f f
f
z H
s
T SC jf
RC
tan
1
2
2
A/D
DSP
Bilinear Transform
Entire j axis maps onto the unit circle
Mapping is nonlinear (tan distortion)
prewarp specifications of RC prototype
Matlab filter design automates this (see,
e.g. bilinear)
=
s
SC s
RC
f
f f
f
tan
0 0.5 1 1.5 2 2.5 3 3.5
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
f
RC
/ f
s
fS
C

/

fs
A/D
DSP
Bilinear Bandpass
f
s
= 100kHz
f
c
= f
s
/8
Q = 10
Matlab:
0.0378 z^2 - 0.0378
H(z) = ----------------------
z^2 - 1.362 z + 0.9244
Pole-ZeroMap
Real Axis
Im
a
g
A
x
is
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
zero at f
s
/2
A/D
DSP
( )
( )
( ) ( )
( ) ( )
6 5 6 5 5 4
2
5 2 3 5 2 5 1 3
2
3
1 2
2
K K z K K K K z
K K K z K K K K K z K
z V
z V
i
o
+ + + +
+ + + +
=
phi1 phi1 phi1
phi2 phi2
K1 CA = 0F
-1M -1M
CA = 1pF CA = 1pF CA = 1pF CA = 1pF
phi1 phi1 phi2
phi2 phi1
K5 CB = 500fF
-1M -1M -1M -1M
CB = 1pF
phi1 phi1 phi1
phi2 phi2
K4 CA = 1.125pF
K3 CB = 37.8fF
K2 CA = 151.2fF
K6 CA = 151.2fF
Vo Vi
Martin-Sedra Biquad
Periodic AC Analysis PAC1
log sweep from 1k to 50k (300 steps)
fs = 100kHz
CLK1
V1
ac = 1V
Ref: K. Martin and A. S. Sedra,
Strays-insensitive switched-
capacitor filters based on the bilinear
z transform, Electron. Lett., vol. 19,
pp. 365-6, June 1979.
A/D
DSP
Magnitude Response
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 10
5
-70
-60
-50
-40
-30
-20
-10
0
Frequency [Hz]
M
a
g
n
it
u
d
e

[
d
B
]
A/D
DSP
LD vs Bilinear Transform
LDI transform:
Realized by standard SC integrators
High frequency zeros are lost
Simple filter synthesis:
Replace RC integrators with SC integrators
Ensure that inverting and non-inverting integrators alternate in loops
Bilinear transform
Maps entire j axis onto unit circle (nonlinear mapping)
Not implemented by standard SC integrators
Synthesis:
Biquads: direct coefficient comparison
Ladders: see
R. B. Datar and A. S. Sedra, Exact design of strays-insensitive
switched capacitor high-pass ladder filters, Electron. Lett., vol. 19, no
29, pp. 1010-12, Nov. 1983.
EECS 247 Lecture 11: Digital Filters 2002 B. Boser 1
A/D
DSP
Digital Filters
Advantages of digital filters
Dynamic range
No coefficient errors, aging
Programmable
Always work on first silicon if
FIR filters
Linear phase
Synthesis
FIR / IIR comparison
Implementation issues
Coefficient rounding
Intermediate result dynamic range
Limit cycles
A/D
DSP
Analog versus Digital DR
Its much less expensive to add dynamic range to
digital circuits than analog circuits
To double the dynamic range of a digital datapath,
we need to add only a bit to an already-wide
datapath:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16
+6dB DR
A/D
DSP
For comparison, consider summing the outputs of 4
identical analog circuits with identical inputs:
A1 A2 A3 A4
v
OUT
v
IN
A/D
DSP
Analog noise is typically uncorrelated in each of the
blocks A1-A4:
A1 A2 A3 A4
v
OUT
v
IN
Signal grows 4X
Noise grows 2X
+6dB Dynamic Range
A/D
DSP
Doubling analog DR is very expensive:
4X the power
4X the area
Doubling digital DR is relatively cheap,
And cost/function decreases by 29%/year (3dB/year)!
Practical circuits tolerate very little loss of DR due to
finite datapath precision in their DSP sections
Analog dynamic range is too precious to lose
Digital DR loss of 5% (~ 0.4dB) of total noise power is typical
Why use analog filters at all?
A/D
DSP
ADC Dynamic Range
The figure shows the DR of
the best standalone ADCs
in 2000
Dynamic range decreases
as converter bandwidth
increases
From 1975-1995, ADC
performance at any
sampling frequency
improved by 2dB/year
ADC Sampling Frequency (Hz)
10
4
10
6
10
8
40
80
60
120
140
100
20
D
y
n
a
m
i
c

R
a
n
g
e

(
d
B

|

B
i
t
s
)
6
13
10
20
23
16
3
A/D
DSP
ADC Dynamic Range
ADCs embedded in IC Systems
on a Chip (SoCs) have less DR
than the best standalone ADCs
The embedded ADC performance
level is shown in red
Analog-digital crosstalk and
design risk issues limit embedded
ADC DR to about 100dB
1 GHz, 30dB DR levels are much
more forgiving and the
performance gap narrows
10
4
10
6
10
8
40
80
60
120
140
100
20
D
y
n
a
m
i
c

R
a
n
g
e

(
d
B
)
embedded ADCs
A/D
DSP
ADC Dynamic Range
Minimization of analog
signal processing is a key
goal of mixed-signal IC
architecture
However, analog signal
processing is almost
unavoidable above the
red line
10
4
10
6
10
8
40
80
60
120
140
100
20
D
y
n
a
m
i
c

R
a
n
g
e

(
d
B
)
embedded ADCs
A/D
DSP
Practical Constraints
Only few ADC design teams in the world can produce
green line dynamic range
If your SoC architecture requires one of those teams
to succeed, think again!
Mixed-signal SoC architectures fail when their
architects choose to ignore long-established,
empirically-proven performance scaling laws
A/D
DSP
FIR Filters
Only finite zeros
Linear phase if coefficients are symmetric
Implement with delays, multipliers, adders
Lack of good analog delays prevents widespread use
of analog FIR filters
Good synthesis tools (e.g. Remez-Exchange
algorithm)
A/D
DSP
Consider the Nth-order FIR filter with transfer
function:
H(z) = a
0
+ a
1
z
-1
+ a
2
z
-2
++ a
N-2
z
2-N
+ a
N-1
z
1-N
+ a
N
z
-N
Suppose the filter coefficients are symmetric
about the middle term, i.e.:
H(z) = a
0
+ a
1
z
-1
+ a
2
z
-2
++ a
2
z
2-N
+ a
1
z
1-N
+ a
0
z
-N
A/D
DSP
H(z) = a
0
+ a
1
z
-1
+ a
2
z
-2
++ a
2
z
2-N
+ a
1
z
1-N
+ a
0
z
-N
= a
0
(1+z
-N
) + a
1
(z
-1
+z
1-N
) + a
2
(z
-2
+ z
2-N
) +
= a
0
z
-N/2
(z
N/2
+z
-N/2
) + a
1
z
-N/2
(z
-1+N/2
+z
1-N/2
) +
+ a
2
z
-N/2
(z
-2+N/2
+ z
2-N/2
) +
= z
-N/2
[ a
0
(z
N/2
+z
-N/2
) + a
1
(z
-1+N/2
+z
1-N/2
) +
a
2
(z
-2+N/2
+ z
2-N/2
) +]
A/D
DSP
The term in brackets [] is a sum of cosine
terms with no phase shift:
H(e
jT
) = e
-jNT/2
[ 2a
0
cos(NT/2)
+ more real cos terms]
() = - NT/2
GR
= NT/2
The constant group delay of the symmetric
coefficient FIR filter is obvious:
half the filter impulse response duration
A/D
DSP
Coefficient Symmetry
Three classes of zero
groupings produce
symmetric coefficients
and linear phase
The first is real axis
zeroes at r and 1/r:
H(z) = z
-2
-(r+1/r)z
-1
+1
A/D
DSP
Conjugate pairs of unit
circle zeroes provide
linear phase:
H(z) = z
-2
- 2z
-1
cos +1

A/D
DSP
Finally, groups of four
zeroes at re
j
and
(1/r)e
j
provide linear
phase
The filter coefficients for
these 4 zeroes are:
1
-2(r+1/r)cos
4+r
2
+1/r
2
-2(r+1/r)cos
1
A/D
DSP
Another interesting case involves
antisymmetric filter coefficients:
Its easy to show that
H(z) = a
0
+ a
1
z
-1
+ a
2
z
-2
+- a
2
z
2-N
- a
1
z
1-N
- a
0
z
-N
H(e
jT
) = e
-jNT/2
e
j/2
[ 2a
0
sin(NT/2)
+ more sin terms]
A/D
DSP
For the antisymmetric coefficient case
() = - NT/2
GR
= NT/2
2
Its still linear phase, but with the frequency
independent 90 phase shift characteristic of
differentiators
A/D
DSP
Linear Phase FIR Example
fs = 1e6;
Fp = 0.10*fs; Fs = 0.13*fs;
Rp = 0.1; Rs = 60;
x = (10^(Rp/20)1)/(10^(Rp/20)+1);
y = 10^(-Rs/20);
[N,fo,ao,W]=remezord(
[Fp Fs],[1 0],[x y],fs);
b = remez(N, fo, ao, W);
Hr = tf(b, 1, 1/fs);
Hr = Hr / 10^(rpass/40);
0 1 2 3 4 5
x 10
5
-70
-60
-50
-40
-30
-20
-10
0
Frequency 0...f
s
/2 [Hz]
M
a
g
n
it
u
d
e

[
d
B
]
0 2 4 6 8 10
x 10
4
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
0
Frequency 0...f
s
/2 [Hz]
M
a
g
n
itu
d
e
[d
B
]
A/D
DSP
z-Plane
-2 -1 0 1 2 3 4 5
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Pole-Zero Map
Real Axis
I
m
a
g
i
n
a
r
y

A
x
i
s
A/D
DSP
Phase Response
0 1 2 3 4 5
x 10
5
0
500
1000
1500
2000
2500
Frequency [Hz]
P
h
a
s
e

[
d
e
g
r
e
e
s
]
Linear?
A/D
DSP
FIR / IIR Comparison
91
st
order linear phase FIR
or
7
th
order elliptic IIR
0 1 2 3 4 5
x 10
5
-70
-60
-50
-40
-30
-20
-10
0
Frequency 0...f
s
/2 [Hz]
M
a
g
n
i
t
u
d
e

[
d
B
]
FIR
IIR
1 2 3 4 5 6 7 8 9 10
x 10
4
-0.16
-0.14
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
Frequency 0...f
s
/2 [Hz]
M
a
g
n
itu
d
e

[d
B
]
FIR
IIR
A/D
DSP
FIR Coefficient Rounding
0 1 2 3 4 5
x 10
5
-120
-100
-80
-60
-40
-20
0
Frequency 0...f
s
/2 [Hz]
M
a
g
n
i
t
u
d
e

[
d
B
]
8 Bits
16 Bits
24 Bits
Floating Point
A/D
DSP
FIR Coefficient Precision
Finite precision FIR filters add transfer functions of
two filters
The infinite precision FIR filter
A rounding error FIR filter
The infinite precision FIR dominates the passband
response
The rounding error FIR filter sets stopband
attenuation when the infinite precision FIR response
is much smaller
A/D
DSP
FIR Coefficient Precision
Random rounding errors transform to white
stopband noise
Stopband attenuation increases by about 6dB for each bit of
coefficient precision
If you dont like the highest bump in the stopband
response, generate a new pattern of rounding error
Use slightly different dc gain
Or slightly different Parks-McClellan (remez) bands
Trial and error can improve filter stopbands by
several dB at a given coefficient precision
A/D
DSP
Filter Dynamic Range
Digital filters need more numeric dynamic range than
the signals they process
They must not overload
They must not surprise you with quantization noise
Digital multiplier/accumulators are multiplexed
Difference equations are added up term-by-term, giving us
intermediate transfer functions to worry about
Intermediate overload is as bad as overload
Lets look at an IIR bandstop filter example
A/D
DSP
2
nd
-Order Bandstop Filter
Bandstop filters have
transfer functions:
Their gains are close to
unity at both dc and f
s
/2
s
P
s
P
Qf
f
r
f
f
r z z r
z z
z H

+
+
=

1
2
1 ) cos 2 (
1 ) cos 2 (
) (
1 2 2
1 2
A/D
DSP
2
nd
Bandstop design
specifications:
f
S
=1MHz
f
P
=20kHz
Q
P
=100

A/D
DSP
Direct Form Realization
[ ] [ ]
k k k k k k
x x x y r y z r y
z z z X r z z r z Y
+ = +
+ = +

) cos 2 ( ) cos 2 (
1 ) cos 2 ( ) ( 1 ) cos 2 ( ) (
1 2 1
2 2
2
1 2 1 2 2
1 ) cos 2 (
1 ) cos 2 (
) (
) (
1 2 2
1 2
+
+
=

r z z r
z z
z X
z Y
Note: Direct form realizations are not ideal for higher order IIR filters. Lattice filters
(and variants), which simulate LC ladders, are less susceptible to finite
coefficient precision and dynamic range.
A/D
DSP
2
nd
We can build a direct form bandstop this way (method #1):
Or this way (method #2):
The order of addition matters if we overload in the middle!
2 2
2
3 result te intermedia
1
2
1
) cos 2 ( ) cos 2 (

+ + = z r y r y x x x y
k k k k k k
4 4 4 4 4 4 4 3 4 4 4 4 4 4 4 2 1
4 4 4 4 3 4 4 4 4 2 1
4 4 3 4 4 2 1
2 1
2 2
2 1
) cos 2 ( ) cos 2 (

+ + =
k k k k k k
x x x z r y r y y
A/D
DSP
2
nd
Proceeding from left to right, the difference
equation generates 3 intermediate transfer
functions plus the complete bandstop transfer
function
All 4 of these transfer function magnitude
responses for method 1 are shown on the
next slide
A/D
DSP
Method #1 Bandstop Responses
Frequency (kHz)
G
a
i
n

(
d
B
)
20
0
- 20
- 40
- 60
0 100 200 300 400 500
intermediate responses
complete bandstop
A/D
DSP
12dB max. gain
Frequency (kHz)
G
a
i
n

(
d
B
)
20
0
- 20
- 40
- 60
0 100 200 300 400 500
intermediate responses
A/D
DSP
The complete bandstop filter never exceeds
unity gain for sinusoidal inputs
Intermediate gains exceed 12dB
Thats 2-bits above the input MSB
Lets examine the area of the notch in more
detail
A/D
DSP
Frequency (kHz)
G
a
i
n

(
d
B
)
19.5 20.5
20
0
- 20
- 40
- 60
no high Q surprises
A/D
DSP
Next, well examine all the intermediate
transfer functions for the method #2
difference equation
The following figures show significantly
different intermediate frequency responses
and somewhat lower maximum intermediate
gains
A/D
DSP
Frequency (kHz)
G
a
i
n

(
d
B
)
0
- 50
- 100
- 150
- 200
0 100 200 300 400 500
9.5dB max. gain
A/D
DSP
Frequency (kHz)
G
a
i
n

(
d
B
)
19.5 20.5
20
0
- 20
- 40
- 60
A/D
DSP
Avoiding Overload
Sinusoidal steady-state responses for
intermediate results are easy to compute and
provide useful insight, but sinusoidal inputs
are never worst cases for overload
Absolute values of filter impulse response
coefficients can give worst-case conditions for
overload and intermediate overload
A/D
DSP
Digital Filter Models
The order of arithmetic operations in digital
signal processing matters
Digital filter models must be cycle true
Unanticipated filter overloads are inexcusable
design errors
Real-world chip developments must never be late-
to-market because of such easy-to-avoid errors!
A/D
DSP
Biquad Quantization Noise
Suppose we build our bandstop difference equation with B-bit
registers and a BxB = 2B hardware multiplier:
Build up the difference equation leaving partial results in a 2B-bit
accumulator
Accumulate y(k)s with a minimum number (i.e. 1) of rounding
operations
If each of the 5 products above is rounded to B-bits, youll have 5X
more quantization noise power
Output noise from rounding operations can be large for high Q
digital biquads
2 2
2 1 2 1
) cos 2 ( ) cos 2 (

+ + = z r y r y Gx Gx Gx y
k k k k k k
A/D
DSP
Datapath rounding operations can degrade
digital filter dynamic ranges by surprisingly
large amounts
Digital filter models must be bit true
Bit true and cycle true models require that
filter models (and modelers) provide exact
test vectors for integrated digital filters
A/D
DSP
Limit Cycles
A disadvantage of digital IIR filters relative to digital
FIR filters is that their responses get strange as they
settle in response to transients
As settling error approaches rounding error, offsets
and oscillations can occur
Non-zero offsets lead to dead zones
Oscillations are called limit cycles
A combination of rounding (or truncation) and
feedback is required for limit cycles
A/D
DSP
Limit Cycles
Well look for limit
cycles in the
bandpass filter:
Note that this filter
passes frequencies
near f
S
/4
0.125 (z
-2
-1)
z
-2
+ 0.75
H(z) =
A/D
DSP
Frequency (kHz)
G
a
i
n

(
d
B
)
20
0
- 20
- 40
- 60
0 100 200 300 400 500
Bandpass Magnitude Response
A/D
DSP
Bandpass Transient Response
Lets examine the bandpass filters response
to the initial condition y(1)=y(2)=10
The bandpass filter output should decay to 0
The floating point filter output does
The fixed point filter output doesnt
Lets take a look
A/D
DSP
Sample Number (time)
F
i
l
t
e
r

O
u
t
p
u
t
10
5
0
- 5
- 10
0 10 20 30 40 50
Bandpass Transient Response
floating point filter
rounded filter
A/D
DSP
Limit Cycles
This bandpass filter limit cycle oscillation
occurs right at f
s
/4
Right in the middle of the filter passband
Could this be a low-level input to the filter at f
s
/4?
IIR filter designers must evaluate and be wary
of limit cycle oscillations
A/D
DSP
Bit true and cycle true digital filter models
allow simulation and evaluation of:
Overload and intermediate overload
Quantization noise
Limit cycles and dead zones
Finite precision coefficient effects
Spending time and money on silicon without
such models is crazy!
EECS 247 Lecture 12: Amplitude Quantization 2002 B. Boser 1
A/D
DSP
Amplitude Quantization
Amplitude quantization
Quantization noise
Static ADC performance measures
Offset
Gain
INL
DNL
ADC Testing
Code boundary servo
Histogram testing
A/D
DSP
Ideal Quantizer
Quantization step (= 1 LSB)
N = 3 Bits
Full-scale input range:
-0.5 (2
N
-0.5)
Quantization error:
bounded by /2 +/2
for inputs within full-scale range
-1 0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
D
i
g
i
t
a
l

O
u
t
p
u
t

C
o
d
e
A/D Characteristics [1]
ADC characteristics
ideal converter
-1 0 1 2 3 4 5 6 7 8
-1
-0.5
0
0.5
1
Q
u
a
n
t
i
z
a
t
i
o
n

e
r
r
o
r

[
L
S
B
]
ADC Input Voltage [1/ ]
A/D
DSP
Quantization Error PDF
Uniformly distributed from
/2 +/2 provided that
Busy input
Amplitude is many LSBs
No overload
Not Gaussian!
Zero mean
Variance
Spectral density white if the joint
pdf of the input at different
sample times is smooth
Ref: W. R. Bennett, Spectra of quantized signals,
Bell Syst. Tech. J., vol. 27, pp. 446-72, July
1988.
B. Widrow, A study of rough amplitude
quantization by means of Nyquist sampling
theory, IRE Trans. Circuit Theory, vol. CT-3, pp.
266-76, 1956.
-/2 -/2
Pdf
error
1/
12
2
2 /
2 /
2
2

=
+

de
e
e
A/D
DSP
Signal-to-Quantization Noise Ratio
Since if some conditions are met (!) the quantization error is random, it
is often referred to as noise
In this case, we can define a peak signal-to-quantization noise ratio,
SQNR, for sinusoidal inputs:
Actual converters do not quite achieve this performance due to other
errors, including
Electronic noise
Deviations from the ideal quantization levels
dB 76 . 1 02 . 6
2 5 . 1
12
2
2
2
1
2
2
2
+ =
=

=
N
SQNR
N
N
e.g. N SQNR
8 50 dB
12 74 dB
16 98 dB
20 122 dB
A/D
DSP
Static ADC Errors
Deviations of characteristic from ideal staircase
Offset
Gain error
Differential Nonlinearity, DNL
Integral Nonlinearity, INL
A/D
DSP
-1 0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
D
i
g
i
t
a
l

O
u
t
p
u
t

C
o
d
e
ADC Input Voltage [LSB]
ADC characteristics
ideal converter
Offset and Gain Error
Offset error
Full-scale error
A/D
DSP
-1 0 1 2 3 4 5 6 7 8 9
0
1
2
3
4
5
6
7
8
D
i
g
i
t
a
l

O
u
t
p
u
t

C
o
d
e
ADC Input Voltage [1/]
ADC characteristics
ideal converter
Differential Nonlinearity
DNL = deviation of
bin width from
+0.4 LSB DNL error
-0.4 LSB DNL error
A/D
DSP
-1 0 1 2 3 4 5 6 7 8 9
0
1
2
3
4
5
6
7
8
D
ig
it
a
l
O
u
t
p
u
t

C
o
d
e
ADC characteristics
ideal converter
Differential Nonlinearity
-1 0 1 2 3 4 5 6 7 8 9
0
1
2
3
4
5
6
7
8
D
ig
it
a
l
O
u
t
p
u
t

C
o
d
e
ADC characteristics
ideal converter
Non-monotonic
(> 1 LSB DNL)
Missing code
(+0.5/-1 LSB DNL)
A/D
DSP
Large DNL Errors
A converter with DNL larger
than 1LSB could be
equivalent an ideal ADC
with 1 bit less resolution
At right:
alternating DNL 1/+1 LSB
0 1 2 3 4 5 6 7 8
1
2
3
4
5
6
7
D
i
g
i
t
a
l

O
u
t
p
u
t

C
o
d
e
ADC characteristics
ideal converter
0 1 2 3 4 5 6 7 8
-1
-0.5
0
0.5
1
Q
u
a
n
t
i
z
a
t
i
o
n

e
r
r
o
r

[
L
S
B
]
A/D
DSP
Integral Nonlinearity
INL = deviation of actual
center of bin from its ideal
location
A straight line through the
endpoints is usually used as
reference,
i.e. offset and gain errors
are ignored in INL
calculation
Note that INL errors can be
much larger than DNL errors
and vice-versa
-1 0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
D
i
g
i
t
a
l

O
u
t
p
u
t

C
o
d
e
ADC Input Voltage [1/]
ADC characteristics
ideal converter
-1.1 LSB INL
A/D
DSP
Monotonicity
Monotonicity guaranteed if
| INL | =0.5 LSB
The best fit straight line is taken as the reference for determining
the INL.
This implies
| DNL | =1 LSB
Note: these conditions are sufficient but not necessary for
monotonicity
Ref: R. J. van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog
Converters, Kluwer Academic Publishers, 1994.
A/D
DSP
DAC DNL and INL
Ref: Understanding Data Converters, Texas Instruments Application Report
SLAA013, Mixed-Signal Products, 1995.
A/D
DSP
DNL and INL Testing
Code boundary servo
Code density (histogram) testing
A/D
DSP
Code Boundary Servo
C
1
ADC
Input
R
2
C
2
ADC
V
REF
i
1
i
2
Digital
Comp.
A<B
B
AB
A
Code
Input
ADC
Output
f
S
A/D
DSP
Code Boundary Servo
i
1
and i
2
are small, and
C
1
is large, so the ADC
analog input moves a
small fraction of an LSB
each sampling period
For a code input of 101,
the ADC analog input
settles to the code
boundary shown
V
REF
000
001
010
011
100
101
110
111
A
D
C

D
i
g
i
t
a
l

O
u
t
p
u
t
0 V
REF
2
ADC Analog Input
A/D
DSP
Code Boundary Servo
C
1
Good DVM
R
2
C
2
ADC
V
REF
i
1
i
2
Digital
Comp.
A<B
B
AB
A
Code
Input
ADC
Output
f
S
A/D
DSP
Code Boundary Servo
A very good digital voltmeter (DVM)
measures the analog input voltage
corresponding to the desired code boundary
DVMs have some interesting properties
They can have very high resolutions (8 decimal
digit meters are inexpensive)
To achieve stable readings, DVMs average
voltage measurements over multiple 60Hz ac line
cycles to filter out pickup in the measurement loop
60Hz pickup in typical measurement loops is
~10mV
A/D
DSP
Code Boundary Servo
A high-accuracy (as opposed to high-
resolution) DVM is unnecessary
The same meter can measure the ADCs voltage
reference
A high-accuracy ADC reference voltage is
likewise unnecessary
V
REF
must be stable to within a fraction of an LSB
for the duration of the INL test
A/D
DSP
Code Boundary Servo
ADCs of all kinds are
notorious for kicking
back high-frequency,
signal-dependent
glitches to their analog
inputs
A magnified view of an
analog input glitch
follows
Good DVM
R
2
C
2
ADC
V
REF
f
S
A/D
DSP
Code Boundary Servo
Just before the input is
sampled and
conversion starts, the
analog input is pretty
quiet
As the converter begins
to quantize the signal, it
kicks back charge
time
0 1/f
S
a
n
a
l
o
g

i
n
p
u
t
start of conversion
A/D
DSP
Code Boundary Servo
The difference between
what the ADC
measures and what the
DVM measures is not
ADC INL, its error in
the INL measurement
How do we control this
error?
time
0 1/f
S
a
n
a
l
o
g

i
n
p
u
t
ADC converts this voltage
DVM measures the average
input including the glitch
A/D
DSP
Code Boundary Servo
A large C
2
fixes this
At the expense of longer
measurement time
(the DVM is slow anyway)
Good DVM
R
2
C
2
ADC
V
REF
f
S
A/D
DSP
Histogram Testing
Code boundary measurements are slow
Long testing time
May miss dynamic errors
Histogram testing
Quantize input with known pdf (e.g. ramp or
sinusoid)
Derive INL and DNL from deviation of measured
pdf from expected result
A/D
DSP
Histogram Test Setup
DNL is usually measured via a code
frequency of occurrence histogram
Hardware looks like this:
Ramp
0
V
REF
ADC PC
V
REF
A/D
DSP
Measuring DNL Error
Ramp speed is adjusted to provide an average of 100
outputs of each ADC code
(for 1/100 LSB resolution)
Ramps can be quite slow for high resolution ADCs:
(65536 codes)(100 conversions/code)
100000 conversions/sec
= 65.6 sec
A/D
DSP
Histogram of Ideal 3 Bit ADC
-1 0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
D
ig
it
a
l
O
u
t
p
u
t

C
o
d
e
ADC characteristics
ideal converter
0 1 2 3 4 5 6 7
0
20
40
60
80
100
120
140
160
180
200
ADC output code
C
o
u
n
t
s
A/D
DSP
Histogram of Sample 3 Bit ADC
-1 0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
D
ig
it
a
l
O
u
t
p
u
t

C
o
d
e
ADC characteristics
ideal converter
+0.4 LSB DNL
-0.4 LSB DNL
+0.4 LSB INL
0 1 2 3 4 5 6 7
0
20
40
60
80
100
120
140
160
180
200
ADC output code
C
o
u
n
t
s
A/D
DSP
DNL from Histogram
Remove over-range bins
(0 and 7)
0 1 2 3 4 5 6 7
0
20
40
60
80
100
120
140
ADC output code
C
o
u
n
t
s
,

E
n
d

b
in
s

r
e
m
o
v
e
d
A/D
DSP
DNL from Histogram
Scale:
1. divide by average count
2. subtract 1
(ideal bins have exactly the
average count, which, after
normalization, is 1)
Result is DNL
0 1 2 3 4 5 6 7
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
ADC output code
D
N
L

=

C
o
u
n
t
s

/

M
e
a
n
(
C
o
u
n
t
s
)
A/D
DSP
INL from Histogram
The DNL tells us width of all
bins (DNL + 1)
We can use it to reconstruct
the exact converter
characteristic (having
measured only the
histogram) by simply adding
up all bin-width
The INL is the deviation from
a straight line through the
end points
-1 0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
ADC Input Voltage
R
e
c
o
n
s
t
r
u
c
t
e
d

C
h
a
r
a
c
t
e
r
is
t
ic
A/D
DSP
DNL and INL of Sample ADC
-1 0 1 2 3 4 5 6 7 8
0
1
2
3
4
5
6
7
D
ig
it
a
l
O
u
t
p
u
t

C
o
d
e
ADC characteristics
ideal converter
+0.4 LSB DNL
-0.4 LSB DNL
+0.4 LSB INL
1 2 3 4 5 6
-1
-0.5
0
0.5
1
1.5
2
bin
D
N
L

[
in

L
S
B
]
DNL and INL of 3 Bit converter (from histogram testing)
avg=-1.9e-017, std.dev=0.25, range=0.8
1 2 3 4 5 6
-1
-0.5
0
0.5
1
1.5
2
bin
I
N
L

[
in

L
S
B
]
avg=0.2, std.dev=0.22, range=0.4
A/D
DSP
Sinusoidal Inputs
Ramps are limited to slow
inputs and may miss dynamic
effects
Solution: use sinusoidal test
signal
Problem: ideal histogram is
not flat but has bath-tub
shape
0 500 1000 1500 2000 2500 3000 3500 4000
0
50
100
150
200
250
Raw Histogram of ADC Output
A/D
DSP
Sinusoidal Inputs
After correction for
sinusoidal pdf
0 500 1000 1500 2000 2500 3000 3500 4000
0
0.2
0.4
0.6
0.8
1
1.2
1.4
x 10
-3
Linearized Histogram
A/D
DSP
DNL and INL
Ref: [1] M. V. Bossche, J . Schoukens,
and J . Renneboog, Dynamic
Testing and Diagnostics of A/D
Converters, IEEE Transactions
on Circuits and Systems, vol.
CAS-33, no. 8, Aug. 1986.
[2] IEEE Standard 1057
0 500 1000 1500 2000 2500 3000 3500 4000
-1
-0.5
0
0.5
1
1.5
code
D
N
L

[
L
S
B
]
DNL = +1.3 / -1 LSB, 1 missing codes (DNL<-0.9)
0 500 1000 1500 2000 2500 3000 3500 4000
-1
-0.5
0
0.5
1
1.5
2
code
I
N
L

[
L
S
B
]
INL = +1.7 / -0.69 LSB
A/D
DSP
DNL/INL Code
function [dnl,inl] = dnl_inl_sin(y);
%DNL_INL_SIN
% dnl and inl ADC output
% input y contains the ADC output
% vector obtained from quantizing a
% sinusoid
% Boris Murmann, Aug 2002
% Bernhard Boser, Sept 2002
% histogram boundaries
minbin=min(y);
maxbin=max(y);
% histogram
h = hist(y, minbin:maxbin);
% cumulative histogram
ch = cumsum(h);
% transition levels
T = -cos(pi*ch/sum(h));
% linearized histogram
hlin = T(2:end) - T(1:end-1);
% truncate at least first and last
% bin, more if input did not clip ADC
trunc=2;
hlin_trunc = hlin(1+trunc:end-trunc);
% calculate lsb size and dnl
lsb= sum(hlin_trunc) / (length(hlin_trunc));
dnl= [0 hlin_trunc/lsb-1];
misscodes = length(find(dnl<-0.9));
% calculate inl
inl= cumsum(dnl);
A/D
DSP
DNL/INL Code Test
% converter model
B = 6; % bits
range = 2^(B-1) - 1;
% thresholds (ideal converter)
th = -range:range; % ideal thresholds
th(20) = th(20)+0.7; % error
fs = 1e6;
fx = 494e3 + pi; % try fs/10!
C = round(100 * 2^B / (fs / fx));
t = 0:1/fs:C/fx;
x = (range+1) * sin(2*pi*fx.*t);
y = adc(x, th) - 2^(B-1);
hist(y, min(y):max(y));
dnl_inl_sin(y);
-30 -20 -10 0 10 20 30
-1
-0.5
0
0.5
1
code
D
N
L

[L
S
B
]
DNL = +0.7 / -0.71 LSB, 0 missing codes (DNL<-0.9)
-30 -20 -10 0 10 20 30
-0.2
0
0.2
0.4
0.6
0.8
code
IN
L

[L
S
B
]
INL = +0.76 / -0.063 LSB
A/D
DSP
Limitations of Histogram Testing
The histogram (as any ADC test, of course) characterizes one
particular converter. Test many devices to get valid statistics.
Histogram testing assumes monotonicity.
E.g. code flips will not be detected.
Dynamic sparkle codes produce only minor DNL/INL errors.
E.g. 123, 123, , 123, 0, 124, 124, look at ADC output to
detect.
Noise not detected or improves DNL.
E.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10, 10,
Ref: B. Ginetti and P. Jespers, Reliability of Code Density Test for High Resolution
ADCs, Electron. Lett., vol. 27, pp. 2231-3, Nov. 1991.
EECS 247 Lecture 13: Spectral Testing 2002 B. Boser 1
A/D
DSP
Discrete Fourier Transform
The DFT of a block of N time samples
{a
n
} = {a
0
,a
1
,a
2
,,a
N-1
}
is a set of N frequency bins
{A
m
} = {A
0
,A
1
,A
2
,,A
N-1
}
where:
A
m
=

n=0
N-1
a
n
W
N
mn
m = 0,1,2,,N-1
W
N
e
j2/N
A/D
DSP
Inverse DFT
The inverse DFT flips a set of frequency bins
{A
m
} = {A
0
,A
1
,A
2
,,A
N-1
}
back to the corresponding time domain samples
{a
n
} = {a
0
,a
1
,a
2
,,a
N-1
}:
a
n
=
m=0
N-1
A
m
W
N
- mn
n=0,1,2,,N-1
W
N
e
j2/N
1
N
A/D
DSP
DFT Properties
DFT of N samples spaced T=1/f
s
seconds:
N bins
Bin m represents frequencies at m * f
s
/N [Hz]
DFT resolution:
Proportional to 1/(NT) in [Hz/bin]
NT is total time spent gathering samples
A/D
DSP
DFT Properties
Given that A
N-m
and A
m
are complex conjugates,
For real time sequences, frequency domain
magnitudes mirror around f
S
/2
A
N-m
= A
m
*
A
N-m
= A
m

A/D
DSP
Energy Theorem
Relates energy in the time domain to
energy in the frequency domain:
n=0
N-1
a
n
m=0
N-1
A
m
2
1
N
=
A/D
DSP
Energy Theorem
n=0
N-1
a
n
m=0
N-1
A
m
2
1
N
=
n=0
N-1
a
n
m=0
N-1
A
m
2
1
N
2
=
1
N
a
rms
=
m=0
N-1
A
m
2
1
N
A/D
DSP
A dc sequence a
n
=a
dc
has only one nonzero term in
its DFT:
A
0
= Na
dc
A sinewave at the center frequency of bin m has 2
nonzero terms, A
m
and A
N-m
, and their magnitudes
are the same:
a
rms
=
2
N
A
m
A
m
=
Na
rms
2
Energy Theorem
A/D
DSP
White noise with rms value a
rms
distributes its energy
evenly into all frequency bins
If the magnitude in each bin is A,
The Energy Theorem
a
rms
=
1
N
NA
2
=
N
A
A = a
rms
N
A/D
DSP
DFT Magnitude Plots
Because A
m
magnitudes are symmetric around f
S
/2, it
is redundant to plot A
m
s for m>N/2
Usually magnitudes are plotted on a log scale
normalized so that a full scale sinewave of rms value
a
FS
yields a peak bin of 0dBFS:
A
m
(dBFS) = 20 log
10
A
m
a
FS
N/2
A/D
DSP
Normalized DFT
fs = 1e6;
fx = 50e3;
afs = 1;
N = 100;
% time vector
t = linspace(0, (N-1)/fs, N);
% signal
y = afs * cos(2*pi*fx*t);
% spectrum
s = 20 * log10(abs(fft(y)/N/afs*2));
% drop redundant half
s = s(1:N/2);
% frequency vector (normalized to fs)
f = (0:length(s)-1) / N;
0 0.2 0.4 0.6 0.8 1
x10
-4
-1
-0.5
0
0.5
1
Time
A
m
p
l
i
t
u
d
e
0 0.1 0.2 0.3 0.4 0.5
-350
-300
-250
-200
-150
-100
-50
0
Frequency [ f / f
s
]
M
a
g
n
i
t
u
d
e

[

d
B
F
S

]
A/D
DSP
Another Example
This does not look
like the spectrum of
a sinusoid
0 1 2 3 4 5
x 10
-5
-1
-0.5
0
0.5
1
Time
S
i
g
n
a
l

A
m
p
l
i
t
u
d
e
0 0.1 0.2 0.3 0.4 0.5
-50
-40
-30
-20
-10
Frequency [ f / f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
F
S

]
A/D
DSP
DFT Periodicity
The DFT implicitly assumes that
time sample blocks repeat every N
samples
With a non-integral number of
periods periods within our
observation window, the input yields
a huge amplitude/phase
discontinuity at the block boundary
This energy spreads into all
frequency bins as spectral
leakage
Spectral leakage can be eliminated
by either
An integral number of sinusoids in
each block
Windowing
0 0.2 0.4 0.6 0.8 1 1.2 1.4
x10
-4
-1
-0.5
0
0.5
1
Time
S
ig
n
a
l
A
m
p
lit
u
d
e
0 0.2 0.4 0.6 0.8 1 1.2 1.4
x10
-4
-1
-0.5
0
0.5
1
Time
S
i
g
n
a
l

A
m
p
l
i
t
u
d
e
A/D
DSP
Spectra
0 0.2 0.4 0.6 0.8 1 1.2 1.4
x 10
-4
-1
-0.5
0
0.5
1
Time
S
i
g
n
a
l

A
m
p
l
i
t
u
d
e
0 0.1 0.2 0.3 0.4 0.5
-60
-50
-40
-30
-20
-10
Frequency [ f / f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
F
S

]
0 0.2 0.4 0.6 0.8 1 1.2 1.4
x 10
-4
-1
-0.5
0
0.5
1
Time
S
i
g
n
a
l

A
m
p
l
i
t
u
d
e
0 0.1 0.2 0.3 0.4 0.5
-400
-300
-200
-100
0
Frequency [ f / f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
F
S

]
A/D
DSP
Integral Number of Periods
fs = 1e6;
% number of full cycles in test
cycles = 67;
% power of 2 speeeds up analysis
% but make N/cycles non-integer!
N = 2^10;
% signal frequency
fx = fs*cycles/N
0 0.1 0.2 0.3 0.4 0.5
-350
-300
-250
-200
-150
-100
-50
0
50
Frequency [ f / f
s
]
A
m
p
lit
u
d
e

[

d
B

]
A/D
DSP
Integral Number of Periods
Fundamental falls into a single
DFT bin
Noise (here numerical
quantization) occupies all
other bins
Integral number of periods
constrains signal frequency f
x
Alternative: windowing
0 0.1 0.2 0.3 0.4 0.5
-350
-300
-250
-200
-150
-100
-50
0
50
Frequency [ f / f
s
]
A
m
p
lit
u
d
e

[

d
B

]
A/D
DSP
Windowing
Spectral leakage can also be virtually
eliminated by windowing time samples prior
to the DFT
Windows taper smoothly down to zero at the
beginning and the end of the observation window
Time samples are multiplied by window
coefficients on a sample-by-sample basis
Windowing sinewaves places the window
spectrum at the sinewave frequency
Convolution in frequency
A/D
DSP
Nuttall Window
Time samples are
multiplied by window
coefficients on a
sample-by-sample basis
Multiplication in the time
domain corresponds to
convolution in the
frequency domain
100 200 300 400 500 600 700 800 900 1000
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
A/D
DSP
DFT of Nuttall Window
Only first 20 bins shown
Response essentially
zero for bins > 5
2 4 6 8 10 12 14 16 18 20
-120
-100
-80
-60
-40
-20
DFT Bin
N
o
r
m
a
liz
e
d

A
p
lit
u
d
e
A/D
DSP
Windowed Data
The plot on the right
shows the signal before
and after windowing
Windowing removes the
discontinuity at block
boundaries
0 0.2 0.4 0.6 0.8 1
x 10
-3
-1
-0.5
0
0.5
1
Time
S
ig
n
a
l
A
m
p
lit
u
d
e
0 0.2 0.4 0.6 0.8 1
x 10
-3
-2
-1
0
1
2
Time
W
in
d
o
w
e
d

S
ig
n
a
l
A
m
p
lit
u
d
e
A/D
DSP
DFT of Windowed Signal
Spectra of signal before
and after windowing
Window gives ~ 100dB
attenuation of sidelobes
(use longer window for
higher attenuation)
Signal energy
smeared over several
(approximately 10) bins
0 0.1 0.2 0.3 0.4 0.5
-70
-60
-50
-40
-30
-20
-10
0
Frequency [ f / f
s
]
S
p
e
c
t
r
u
m

n
o
t

W
in
d
o
w
e
d

[

d
B
F
S

]
0 0.1 0.2 0.3 0.4 0.5
-140
-120
-100
-80
-60
-40
-20
0
Frequency [ f / f
s
]
W
in
d
o
w
e
d

S
p
e
c
t
r
u
m

[

d
B
F
S

]
A/D
DSP
Integral Cycles versus Windowing
Integral number of cycles
Signal energy falls into single DFT bin
Requires careful choice of f
x
Ideal for simulations, usually impractical for measurements
Windowing
No restrictions on f
x
and no need to lock it to f
s
ideal for measurements
Signal energy (and harmonics) distributed over several DFT
bins
Requires more datapoints for set accuracy
A/D
DSP
Spectral ADC Testing
ADC with B bits
1 full scale input
B = 10;
delta = 2/(2^B-1);
th = -1+delta/2:delta:1-delta/2;
x = sin();
y = adc(x, th) * delta - 1;
A/D
DSP
ADC Output Spectrum
Signal amplitude:
Bin: N * fx/fs + 1
(Matlab arrays start at 1)
A =0dBFS
SNR?
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
-120
-100
-80
-60
-40
-20
0
Frequency [ f / f
s
]
A
m
p
lit
u
d
e

[

d
B
F
S

]
N = 16384 A = 0.0dBFS
A/D
DSP
ADC Output Spectrum
Noise bins: all except signal bin
bx = N*fx/fs + 1;
As = 20*log10(s(bx))
sn(bx) = 0;
An = 10*log10(sum(sn.^2))
SNR = As - An
SNR = 62dB (10 bits)
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
-120
-100
-80
-60
-40
-20
0
Frequency [ f / f
s
]
A
m
p
lit
u
d
e

[

d
B
F
S

]
N = 16384 A = 0.0dBFS SNR = 62.0dB
A/D
DSP
Spectral Components
Signal S
DC
Distortion D
Noise N
Signal-to-noise ratio
SNR = S / N
Signal-to-distortion ratio
SDR = S / D
Signal-to-noise+distortion ratio
SNDR = S / (N+D)
Spurious-free dynamic range
SFDR
0 0.05 0.1 0.15 0. 2 0.25 0.3 0.35 0.4 0.45
-120
-100
-80
-60
-40
-20
0
H
1
= -76.0dBFS
H
2
= -57. 8dBFS
H
3
= -78. 9dBFS
DC = -40. 1dBFS
A = -0. 0dBFS
Frequency [ f / f
s
]
A
m
p
lit
u
d
e

[

d
B
F
S

]
N = 16384 SNR = 61.9dB SDR = 57.7dB SNDR = 53.5dB SFDR = 57.8dB
A/D
DSP
Distortion Components
At multiples of f
x
Aliasing:
f
0
= f
x
= 0.18 f
s
f
1
= 2 f
0
= 0.36 f
s
f
2
= 3 f
0
= 0.54 f
s
0.46 f
s
f
3
= 4 f
0
= 0.72 f
s
0.28 f
s
f
4
= 5 f
0
= 0.90 f
s
0.10 f
s
f
5
= 6 f
0
= 1.08 f
s
0.08 f
s
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
-120
-100
-80
-60
-40
-20
0
H
1
= -76.0dBFS
H
2
= -57.8dBFS
H
3
= -78.9dBFS
DC = -40.1dBFS
A = -0.0dBFS
Frequency [ f / f
s
]
A
m
p
lit
u
d
e

[

d
B
F
S

]
A/D
DSP
Spectrum versus INL, DNL
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
-120
-100
-80
-60
-40
-20
0
H
1
= -76.0dBFS
H
2
= -57.8dBFS
H
3
= -78.5dBFS
DC = -40.1dBFS
A = -0.0dBFS
Frequency [ f / f
s
]
A
m
p
lit
u
d
e

[

d
B
F
S

]
100 200 300 400 500 600 700 800 900 1000
-1
-0.5
0
0.5
1
1.5
2
bin
D
N
L

[
in

L
S
B
]
DNL and INL of 10 Bit converter (from converter decision thresholds)
avg=0.0053, std.dev=0.0048, range=0.019
100 200 300 400 500 600 700 800 900 1000
-1
-0.5
0
0.5
1
1.5
2
2.5
3
bin
I
N
L

[
in

L
S
B
]
avg=0.21, std.dev=0.75, range=2.1
Good DNL and poor INL
suggests distortion problem
A/D
DSP
Noise
At right is the spectrum of
a 10-Bit converter
SNDR = 47dB
somethings amiss
Distortion?
SDR = 59.9dB no
Must be a noise problem,
but is it thermal or
quantization noise?
0 0.1 0.2 0.3 0.4 0.5
-140
-120
-100
-80
-60
-40
-20
0
Frequency [ f / f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
F
S

]
A/D
DSP
Noise
At right is the spectrum of a
same 10-Bit converter for
f
x
= f
s
/ 16
Since f
x
divides f
s
, the
quantization noise is
periodic!
It falls into the same bins the
harmonics would normally
occupy
Hence
SNR thermal noise
SDR quantization noise
(apparently the culprit)
0 0.1 0.2 0.3 0.4 0.5
-140
-120
-100
-80
-60
-40
-20
0
Frequency [ f / f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
F
S

]
A/D
DSP
Noise
Same converter again
(f
x
= f
s
/ 16)
The quantization noise
problem has been fixed:
SDR = 62dB for 10bits
Congratulations!
But apparently the fix causes
a thermal noise problem:
SNR = 45.5dB
Another revision
(our competitors like this )
0 0.1 0.2 0.3 0.4 0.5
-120
-100
-80
-60
-40
-20
0
Frequency [ f / f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
F
S

]
A/D
DSP
Noise
One more time
(f
x
= f
s
/ 16)
The quantization noise is
not a major error:
SDR = 74dB
SNR = 56.1dB
This corresponds to
Gaussian noise with
variance /2 at the
converter input a
reasonable design choice
0 0.1 0.2 0.3 0.4 0.5
-140
-120
-100
-80
-60
-40
-20
0
Frequency [ f / f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
F
S

]
A/D
DSP
Noise
The DNL and INL
confirm the good result
But the INL shows
some bowing lets
see if our test masked a
distortion problem
100 200 300 400 500 600 700 800 900 1000
-1
-0.5
0
0.5
1
1.5
2
bin
D
N
L

[
in

L
S
B
]
-0.2 / +0.2 LSB, avg=0.00031, std.dev=0.083, range=0.48
100 200 300 400 500 600 700 800 900 1000
-1
-0.5
0
0.5
1
1.5
2
bin
I
N
L

[
i
n

L
S
B
]
-0.3 / +0.2 LSB, avg=-0.039, std.dev=0.071, range=0.47
A/D
DSP
Noise
For that we revert to
simulating with f
s
/f
x
non-
integer
A 3
rd
harmonic is barely
visible
How can we lift it out
of the noise?
0 0.1 0.2 0.3 0.4 0.5
-140
-120
-100
-80
-60
-40
-20
0
Frequency [ f / f
s
]
A
m
p
lit
u
d
e

[

d
B
F
S

]
A/D
DSP
Noise
Increasing N, the number of
samples (and hence the
measurement or simulation
time) distributes the noise
over more bins
More bins less noise
power per bin (total noise
stays same)
SFDR = 78dB for 10Bit is
acceptable in many
applications (e.g. digital
imaging)
0 0.1 0.2 0.3 0.4 0.5
-150
-100
-50
0
Frequency [ f / f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
F
S

]
A/D
DSP
Effective Number of Bits
Is a 10-Bit converter with 55dB SNDR really a
10-Bit converter?
Effective Number of Bits
Bits 8 . 8
02 . 6
76 . 1 55
dB 02 . 6
dB 76 . 1
=
=
SNDR
ENOB
A/D
DSP
ADC Applications
A/D
DSP
Example: AD9235 12Bit / 65MS/s
A/D
DSP
AD9235 Spectra
SINAD = SNDR
A/D
DSP
AD9235 SNR / SFDR
A/D
DSP
AD9235 DNL / INL
A/D
DSP
AD9235 Block Diagram
A/D
DSP
AD7677 16Bit / 1MS/s
A/D
DSP
AD7677 Spectrum
SINAD = SNDR
A/D
DSP
AD7677 DNL / INL
A/D
DSP
AD7677 DC Input
A/D
DSP
ADS1254 24Bits / 20kS/s
A/D
DSP
Recent Nyquist ADC Performance:
ISSCC Nyquist ADCs
Year paper # lead author power(mW) res SNDR(db) Fs sig BW FOM
2002 10.2 Scholtens 340 6 32dB 1600 660 77
2001 8.1 Choi 545 6 33dB 1300 650 54
2001 8.2 Geelen 300 6 36dB 900 450 93
2000 26.2 Sushihara 400 6 32dB 800 200 20
2000 26.1 Nagaraj 187 6 35.2dB 700 250 76
1999 18.5 Tamba 400 6 35dB 500 250 35
1999 18.6 Yoon 330 6 33dB 500 75 10
2002 18.2 Lin 0.48 6 33dB 22 11 1023
2002 10.3 Sushihara 50 7 36.7dB 450 225 308
2002 10.1 Poulton 4600 8 38.5dB 4000 2000 37
2000 2.5 Ming 250 8 46dB 80 20 16
2002 10.4 Jamal 234 10 57dB 120 60 182
2001 8.3 Park 180 10 57dB 100 50 197
1999 18.3 Hoogzaad 65 10 57dB 40 20 228
2002 10.5 Miyazaki 16 10 54dB 30 15 470
1999 18.2 vanderPloeg 195 10 58dB 25 5 20
1999 18.4 Brandt 75 10 60dB 20 10 133
2002 10.6 Kuttner 12 10 55dB 20 10 468
2000 2.3 Singer 500 12 70dB 65 32 202
2001 8.4 vanderPloeg 295 12 54 25 0
2000 2.4 Pan 850 12 64dB 50 25 47
2002 18.4 Kulhalli 30 12 68dB 21 10 837
1999 18.1 Erdogan 16 12 71dB 0.125 0.05 11
2002 18.5 Waltari 715 13 50 25 0
2000 2.2 Choe 800 13 66dB 40 20 50
2000 2.1 Moreland 1250 14 75dB 100 25 112
2001 8.5 Kelly 340 14 73dB 75 37.5 493
2001 8.6 Yu 860 14 40 0
2000 2.7 Chen 720 14 74dB 20 10 70
All Bandwidths are
in MHz, all FOM
are 10^9
P
BW ENOB
FOM

=
Figure of Merit:
A/D
DSP
10-Bit ADC Power
A/D
DSP
12-Bit ADC Power
EECS 247 Lecture 14: D/A Converter 2002 B. Boser 1
A/D
DSP
D/A Converters
D/A architecture examples
Unit element
Binary weighted
Static performance
Component matching
Architectures
Unit element
Binary weighted
Segmented
Dynamic element matching
Dynamic performance
Glitches
Reconstruction filter
DAC Examples
A/D
DSP
D/A Examples
Voltage, Charge, or Current Based
E.g.
Resistor string
Charge redistribution
M-DAC
A/D
DSP
R-String DAC
Unit element
Inherently monotonic
2
B
resistors and
2
B
switches for B bits
Simple and relatively fast up
to ~ 10 bits
High element count, settling
time for B > 10:
= 0.25 x 2
B
RC
Ref: M. Pelgrom, A 10-b 50-MHz
CMOS D/A Converter with 75-W
Buffer, JSSC, Dec. 1990, pp. 1347.
R1
R2
R3
R_N
Vref
Vout
C
S1
S2
S3
S4
S_N
A/D
DSP
Charge Redistribution DAC
Binary weighted
Monotonicity depends on element matching
B+1 capacitors (2
B
unit elements)
C C 2C 4C 8C 2^(B-1) C
Vref
Vout
reset
b0 (lsb) b1 b2 b3 b_B-1 (msb)
CP
ref
P
B
B
i
i
i
out
V
C C
C b
V
+
2
2
1
0
A/D
DSP
M-DAC
Binary weighted
Often realized with unit elements also
Monotonicity depends on element matching
B current sources (2
B
-1 unit elements)
2^(B-1) Iref

4 Iref

2 Iref

Iref

Iout
A/D
DSP
Static DAC INL / DNL Errors
Component Matching
Systematic Errors
Contact resistance
Edge effects in capacitor arrays
Process gradient
Finite current source output resistance
Random Errors
Lithography
Often Gaussian distribution (central limit theorem)
C. Conroy et al, Statistical Design Techniques for D/A Converters, JSSC Aug. 1989, pp. 1118-28.
A/D
DSP
Gaussian Distributions
-3 -2 -1 0 1 2 3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
x /
P
r
o
b
a
b
ility
d
e
n
s
ity
p
(
x
)
( )
2
2
2
2
1
) (

x
e x p
A/D
DSP
Yield
( )
,
_
2
erf
2
1
2
2
X
dx e X x X P
X
X
x
0 0.5 1 1.5 2 2.5 3

0
0.1
0.2
0.3
0.4
P
r
o
b
a
b
ilit
y

d
e
n
s
it
y

p
(
x
)
0 0.5 1 1.5 2 2.5 3
0
0.2
0.4
0.6
0.8
1
P
(
-
X

x

+
X
)
X
38.3
68.3
95.4
A/D
DSP
Yield
X/ P(-X x X) [%]
0.2000 15.8519
0.4000 31.0843
0.6000 45.1494
0.8000 57.6289
1.0000 68.2689
1.2000 76.9861
1.4000 83.8487
1.6000 89.0401
1.8000 92.8139
2.0000 95.4500
X/ P(-X x X) [%]
2.2000 97.2193
2.4000 98.3605
2.6000 99.0678
2.8000 99.4890
3.0000 99.7300
3.2000 99.8626
3.4000 99.9326
3.6000 99.9682
3.8000 99.9855
4.0000 99.9937
A/D
DSP
Example
Measurements show that the offset voltage of a batch
of operational amplifiers follows a Gaussian
distribution with = 2mV and = 0.
Fraction of opamps with |V
os
| < X = 6mV:
X/ = 3 99.73 % yield (wed still test before shipping!)
Fraction of opamps with |V
os
| < X = 400V:
X/ = 0.2 15.85 % yield
A/D
DSP
DNL Unit Element DAC
Example:
If
R/R
= 1%, what DNL spec
goes into the datasheet so that
99.9% of all converters meet
the spec?
Answer:
From table: X/ = 3.3
DNL
=
R/R
= 1%
3.3
DNL
= 3.3%
+/- 0.033 LSB
i
i
R
R DNL
i
i
o
i
o
o i
i
i
i i
o
R
R
R
R
R
R R
DNL
I R
I R

ref
ref
DNL of unit element DAC is
independent of resolution!
E.g. Resistor string DAC:
A/D
DSP
DAC INL
Error is maximum at mid-scale:
Depends on DAC resolution and element matching
1 2 with
1 2
2
1

B
B
INL
N

Ref: Kuboki et al, TCAS, 6/1982
A/D
DSP
Untrimmed DAC INL
Example:
INL
= 0.1 LSB
= 1% B = 8.6
= 0.5% B = 10.6
= 0.2% B = 13.3
= 0.1% B = 15.3
1
]
1

INL
B
INL
B
2
log 2 2
1 2
2
1
A/D
DSP
Simulation Example
= 1%
B = 12
INL
= 0.3 LSB
(midscale)
500 1000 1500 2000 2500 3000 3500 4000
-1
0
1
2
bin
D
N
L

[
i
n

L
S
B
]
-0.04 / +0.03 LSB, avg=6.7e-005, std.dev=0.01, range=0.069
500 1000 1500 2000 2500 3000 3500 4000
-1
0
1
2
bin
I
N
L

[
i
n

L
S
B
]
-0.2 / +0.8 LSB, avg=0.22, std.dev=0.21, range=0.99
A/D
DSP
Binary Weighted DAC
INL same as for unit
element DAC
DNL depends on
transition
Consider
0111 1000
2^(B-1) Iref

4 Iref

2 Iref

Iref

Iout
Sample realization of
binary weighted DAC:
A/D
DSP
DNL of Binary Weighted DAC
Worst-case transition
occurs at mid-scale:
Example:
B = 12,
= 1%
DNL
= 0.64 LSB
( ) ( )
2
... 1000
2 1
... 0111
2 1 2
2
2 1 2

B
B B
DNL
+

43 42 1 43 42 1
0 2 4 6 8 10 12 14
0
5
10
15
DAC input code
(

D
N
L

/

)
2
A/D
DSP
Simulation Example
= 1%
B = 12
DNL
= 0.6 LSB
(midscale)
MSB transitions
clearly visible
500 1000 1500 2000 2500 3000 3500 4000
-1
0
1
2
bin
D
N
L

[
i
n

L
S
B
]
-0.9 / +0.4 LSB, avg=-7.5e-005, std.dev=0.039, range=1.3
500 1000 1500 2000 2500 3000 3500 4000
-1
0
1
2
bin
I
N
L

[
i
n

L
S
B
]
-0.7 / +0.7 LSB, avg=3.3e-014, std.dev=0.33, range=1.3
A/D
DSP
Another Random Run
Now (by chance) worst
DNL is mid-scale.
Statistical result!
500 1000 1500 2000 2500 3000 3500 4000
-2
-1
0
1
2
bin
D
N
L

[
i
n

L
S
B
]
-1 / +0.1 LSB, avg=-9.3e-005, std.dev=0.035, range=1.4
500 1000 1500 2000 2500 3000 3500 4000
-1
0
1
2
bin
I
N
L

[
i
n

L
S
B
]
-0.8 / +0.8 LSB, avg=-1.1e-013, std.dev=0.37, range=1.6
A/D
DSP
Unit Element vs Binary Weighted
Unit Element DAC Binary Weighted DAC
B
INL
DNL
S
B
2
2
1
2

B S
B
B
INL
INL DNL

1
2
2
2
2 2
Number of switched elements:
Significant difference in performance and complexity!
A/D
DSP
DAC INL/DNL Summary
DAC architecture has significant impact on DNL
INL is independent of DAC architecture and requires element
matching commensurate with overall DAC precision
Results are for uncorrelated random element variations
Systematic errors and correlations are usually also important
Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of
resistor string A/D converters. IEEE Transactions on Circuits and Systems,
vol.CAS-29, (no.6), J une 1982. p.383-9.
A/D
DSP
Segmented DAC
Objective:
compromise between unit element and binary weighted DAC
Approach:
B
1
MSB bits unit elements
B
2
= B-B
1
LSB bits binary weighted
INL: unaffected
DNL: worst case occurs when LSB DAC turns off and one more
MSB DAC element turns on: same as binary weighted DAC
with B
2
+1 bits
Switched Elements: (2
B1
-1) + B
2
A/D
DSP
Comparison
Example:
B = 12, B
1
= 5, B
2
= 7
= 1%
4095
12
31+7
0.01
0.64
0.16
0.32
0.32
0.32
Unit element
Binary weighted
Segmented
# s.e.
DNL
INL
DAC Architecture
A/D
DSP
Dynamic DAC Error: Glitch
Consider binary weighted
DAC transition 011 100
DAC output depends on
timing
Plot shows situation where
MSBs switch on time
LSBs switch
On time
Early
Late
1 1.5 2 2.5 3
0
5
10
i
d
e
a
l
1 1.5 2 2.5 3
0
5
10
e
a
r
l
y
1 1.5 2 2.5 3
0
5
10
Time
l
a
t
e
A/D
DSP
Glitch Energy
Glitch energy (worst case): t 2
B-1
LSB energy: T
Need t 2
B-1
<< T or t << 2
-B+1
Examples:
<< 488
<< 1.5
<< 2
12
16
10
1
20
1000
t [ps] B f
s
[MHz]
Compare to digital circuit clock skew
A/D
DSP
DAC Reconstruction Filter
Need for and
requirements depend
on application
Tasks:
Correct for sinc distortion
Remove aliases
(stair-case
approximation)
0 0.5 1 1.5 2 2.5 3
x 10
6
0
0.5
1
D
A
C

I
n
p
u
t
0 0.5 1 1.5 2 2.5 3
x 10
6
0
0.5
1
s
i
n
c
0 0.5 1 1.5 2 2.5 3
x 10
6
0
0.5
1
D
A
C

O
u
t
p
u
t
Frequency
B f
s
/2
A/D
DSP
Reconstruction Filter Options
Digital and SC filter possible only in combination with
oversampling (signal bandwidth B << f
s
/2)
Digital filter can prewarp spectrum to compensate in-
band sinc attenuation (from ZOH)
Di gi tal
Fi l ter
DAC
SC
Fi l ter
ZOH
CT
Fi l ter
A/D
DSP
Sample DAC Implementations
Untrimmed segmented
T. Miki et al, An 80-MHz 8-bit CMOS D/A Converter, JSSC
December 1986, pp. 983.
A. Van den Bosch et al, A 1-GSample/s Nyquist Current-Steering
CMOS D/A Conveter, JSSC March 2001, pp. 315.
Current copiers:
D. W. J. Groeneveld et al, A Self-Calibration Techique for
Monolithic High-Resolution D/A Converters, JSSC December
1989, pp. 1517.
Dynamic element matching:
R. J. van de Plassche, Dynamic Element Matching for High-
Accuracy Monolithic D/A Converters, JSSC December 1976, pp.
795.
A/D
DSP
A/D
DSP
A/D
DSP
A/D
DSP
A/D
DSP
A/D
DSP
A/D
DSP
A/D
DSP
A/D
DSP
Dynamic Element Matching
f
clk
/ 2 error
1
I
o
/2
I
1
I
2
I
o
( )
( )
1 2
1
) 1 (
2
1 2
1
) 1 (
1
1
1

+
o
o
I I
I I ( )
( )
1 2
1
) 2 (
2
1 2
1
) 2 (
1
1
1
+

o
o
I I
I I
During
1
During
2
( ) ( )
2
2
1 1
2
2
1 1
) 2 (
2
) 1 (
2
2
o
o
I
I
I I
I
+ +
I
o
/2
A/D
DSP
Dynamic Element Matching
f
clk
/ 2 error
2
f
clk
/ 2 error
1
I
o
/4 I
o
/4 I
o
/2
I
1
I
2
I
4
I
3
I
o
( )
( )
( )
( )( )
2 1 4
1
2
) 1 (
1 2
1
) 1 (
3
1 2
1 ) 1 (
2
1 2
1
) 1 (
1
1 1
1
1
1
+ +
+

+
o
o
o
I
I I
I I
I I ( )
( )
( )
( )( )
2 1 4
1
2
) 2 (
1 2
1
) 2 (
3
1 2
1 ) 2 (
2
1 2
1
) 2 (
1
1 1
1
1
1

+

o
o
o
I
I I
I I
I I
During
1
During
2
( )( ) ( )( )
( )
2 1
2 1 2 1
) 2 (
3
) 1 (
3
3
1
4
2
1 1 1 1
4
2
+
+ + +
o
o
I
I
I I
I
E.g.
1
=
2
= 1% matching error is (1%)
2
= 0.01%
A/D
DSP
Sampling
Ideal Sampling Practical Sampling
v
IN
v
OUT
C
S1
1
v
IN
v
OUT
C
M1
1
Grab exact value of V
in
when switch opens
kT/C noise
Finite R
sw
limited bandwidth
R
sw
= f(V
in
) distortion
Switch charge injection (EE240)
Clock jitter
A/D
DSP
kT/C Noise
In high resolution ADCs kT/C noise usually dominates
overall error (power dissipation argument).
2
2
1 2
12
12
FS
B
B
B
V
T k C
C
T k
0.003 pF
0.8 pF
13 pF
206 pF
52,800 pF
8
12
14
16
20
C
min
(V
FS
= 1V) B
A/D
DSP
Acquisition Bandwidth
The resistance R of switch
S1 turns the sampling
network into a lowpass filter
with risetime = RC =
Assuming V
in
is constant
during the sampling period
and C is initially discharged
(a good ideawhy?):
v
IN
v
OUT
C
S1
1
R
( )
/
1 ) (
t
in out
e v t v

=
A/D
DSP
Switch On-Resistance
Example:
B = 14, C = 13pF, f
s
= 100MHz
T/ >> 19.4, R << 40
v
IN
v
OUT
C
S1
1
T=1/f
S
R
( )
( ) 1 2 ln
1
2
1
1 2 ln
1
2
: Case Worst
2
1
2
1
<<
<<
=
<<
<<
B
s
B
FS in
f
in
s
out in
C f
R
T
V v
e v
f
t v v
s

A/D
DSP
Switch On-Resistance
( )
( )
( )
( )
TH DD
in
TH DD
in
DS
V V
v
o ON
TH DD ox
o
V V
v
o
in TH DD ox
TH GS ox
V
DS
triode D
ON
DS
DS
TH GS ox triode D
R R
V V
L
W
C
R
R
v V V
L
W
C
V V
L
W
C
dV
dI
R
V
V
V V
L
W
C I
=

=
=
1
1
ith w
1
1 1
1
1
1
2
0
) (
) (

A/D
DSP
Sampling Distortion
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
-120
-100
-80
-60
-40
-20
0
H
1
= -49.4dBFS
H
2
= -66.3dBFS
H
3
= -105.2dBFS
DC = -43.4dBFS
A = -0.1dBFS
Frequency [ f / f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
F
S

]
TH DD
in
V V
v
T
in out
e v v
1
1
2
1

T/ = 10
V
DD
V
TH
= 2V V
FS
= 1V
A/D
DSP
Sampling Distortion
T/ = 20
V
DD
V
TH
= 2V V
FS
= 1V
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
-120
-100
-80
-60
-40
-20
0
H
1
= -69.5dBFS
H
2
= -76.3dBFS
H
3
= -83.5dBFS
DC = -65.3dBFS
A = -0.0dBFS
Frequency [ f / f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
F
S

]
SFDR is very sensitive to
sampling distortion
Solutions:
Overdesign switches
increased switch
charge injection
Complementary switch
Maximize V
DD
/V
FS
increased noise
Constant V
GS
? f(V
in
)

A/D
DSP
Constant V
GS
Sampling
Switch overdrive voltage is independent of signal
Error from finite R
ON
is linear (to first order)
A/D
DSP
Constant V
GS
Sampling
A/D
DSP
Constant V
GS
Sampling Circuit
Supply
VDD = 3V
VSS = 0V
Constant Vgs Switch
C1
1pF
C2
1pF
M1
10 / 0.35

M2
10 / 0.35

VDD
VP1
100ns
Transient Analysis
to 1.5us
M3
10 / 0.35

C3
1pF
M12
10 / 0.35

M5
10 / 0.35

M4
10 / 0.35

M8
10 / 0.35

M9
10 / 0.35

M9
10 / 0.35

M6
10 / 0.35
M11
10 / 0.35

M11
10 / 0.35

M11
10 / 0.35

M11
10 / 0.35

VS1
1.5V
1MHz
CH
1pF
P
P
A/D
DSP
Clock Multiplier
Supply
VDD = 3V
VSS = 0V
Clock Booster
C1
1pF
C2
1pF
M1
10 / 0.35

M2
10 / 0.35

VDD
VP1
100ns
P
P_N
P_Boost P_Boost_N
Transient Analysis
to 500ns
R1
1GOhm
R2
1GOhm
A/D
DSP
Constant V
GS
Sampler: LOW
Sampling switch
M11 is OFF
C3 charged to VDD
Constant Vgs Switch: P is LOW
VDD
M3
10 / 0.35

C3
1pF
M12
10 / 0.35

M4
10 / 0.35

OFF

VS1
1.5V
1MHz
CH
1pF
~ 2 VDD
(boosted clock)
VDD
VDD
VDD
OFF M11
OFF
A/D
DSP
Constant V
GS
Sampler: HIGH
C3 previously
charged to VDD
M8 & M9 are on:
C3 across G-S of M11
M11 on with constant
VGS = VDD
Constant Vgs Switch: P is HIGH
C3
1pF
M8
10 / 0.35

M9
10 / 0.35

M9
10 / 0.35

M11
10 / 0.35

M11
10 / 0.35

M11
10 / 0.35

M11
10 / 0.35

VS1
1.5V
1MHz
CH
1pF
VDD
A/D
DSP
Constant V
GS
Sampling
A/D
DSP
Complete Circuit
Ref: A. Abo et al, A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital
Converter, J SSC May 1999, pp. 599.
Clock Multiplier
for M3
Switch
M7 & M13 for
reliability
A/D
DSP
CMOS Sample & Hold
v
IN
v
OUT
C
S1A
1D
S2
2
S2A
2
S3
1D
1 S1
v
CM
1D
2
A/D
DSP
CMOS Sample & Hold
v
IN
v
OUT
C
S1A
1D
S2
2
S2A
2
S3
1D
1 S1
v
CM
1D
2
Constant V
GS
A/D
DSP
CMOS Sample & Hold
v
IN
v
OUT
C
S1A
1D
S2
2
S2A
2
S3
1D
1 S1
v
CM
1D
2
Small Nch-only
A/D
DSP
CMOS Sample & Hold
v
IN
v
OUT
C
S1A
1D
S2
2
S2A
2
S3
1D
1 S1
v
CM
1D
2
Charging C
A/D
DSP
CMOS Sample & Hold
S1 is an n-channel MOSFET
S1 provides as much of the sampling path
resistance as possible (R=R
S1A
+R
S1
)
S1A is a wide (much lower resistance than S1)
constant V
GS
switch
If S1As resistance is negligible, aperture delay
depends only on S1 resistance
S1 resistance is independent of v
IN
; hence,
aperture delay is independent of v
IN
A/D
DSP
Charge Injection
At the instant of sampling, some of the charge
stored in sampling switch S1 is dumped onto C
This unwanted charge is called charge injection
The circuit on slide 15.2 has charge injection
that varies in a wildly nonlinear fashion with v
IN
With the CMOS Sampling Circuit, charge
injection comes only from S1 and is first-order
independent of v
IN
Only a dc offset is added to the input signal
This dc offset can be removed with a differential
architecture
A/D
DSP
CMOS Sample & Hold
v
IN
v
OUT
C
S1A
1D
S2
2
S2A
2
S3
1D
1 S1
v
CM
1D
2
Sampling
only 1 transistor in S1
opens to sample the input
A/D
DSP
CMOS Sample & Hold
During
2
, the opamp buffers the
sampling capacitor for loads that need it
The hold topology is shown on the
following slide
A/D
DSP
CMOS Sample & Hold
v
IN
v
OUT
C
S1A
1D
S2
2
S2A
2
S3
1D
1 S1
v
CM
1D
2
Holding
A/D
DSP
Jitter
All of the preceding analyses assume
that sampling impulses are spaced
evenly in time
In the real world, separation of sampling
impulses has some distribution around
the nominal value T
The variability in T is called jitter
A/D
DSP
Jitter
The dominant cause of
clock jitter in most chips
is power supply noise
produced by unrelated
activity in other parts of
the chip
The inverter symbol
represents a chain of
gates in the sampling
clock path
Noisy VDD
Jitter
Free
Clock
Jittered
Output
Clock
A/D
DSP
Jitter
Lets assume the
inverter delay is
100psec, and that
the delay varies by
20% per volt change
in VDD (20psec/V)
200mV of power
supply noise
becomes 4psec of
clock jitter
Noisy VDD
Jitter
Free
Clock
Jittered
Output
Clock
A/D
DSP
Jitter
Sampling jitter adds
an error voltage
proportional to the
product of (t
J
-t
0
) and
the derivative of the
input signal at the
sampling instant
Jitter doesnt matter
when sampling dc
signals
nominal
sampling
time t
0
actual
sampling
time t
J
x(t)
x(t
0
)
A/D
DSP
Jitter
The error voltage is
nominal
sampling
time t
0
actual
sampling
time t
J
x(t)
x(t
0
)
e = x(t
0
)(t
J
t
0
)
A/D
DSP
Jitter Example
Sinusoidal input Worst case
( )
( )
?t t x t e
fA t x
t f fA t x
t f A t x
?t
f
A
x
x
x
) ( ' ) (
2 ) ( '
2 cos 2 ) ( '
2 sin ) (
: Jitter
: Frequency
: Amplitude
=
=
s
B
B
FS
s
x
FS
f
?t
A
t e
f
f
A A
2
1
2 2
) (
2
1
<<
<<
=
=
+
0.5 ps
0.8 ps
1.2 ps
10 MHz
100 MHz
1000 MHz
16
12
8
t << than f
s
B
A/D
DSP
The Jitter Law
The worst case looks pretty stringent
what about the average?
Lets calculate the mean squared jitter error (variance)
If were sampling a sinusoidal signal
x(t) = Asin(2f
x
t),
then
x(t) = 2f
x
Acos(2f
x
t)
E{[x(t)]
2
} = 2
2
f
x
2
A
2
If jitter is uniformly distributed from -/2 to +/2
E{(t
J
-t
0
)
2
} =
2
/12
A/D
DSP
The Jitter Law
If x(t) and the jitter are independent
E{[x(t)(t
J
-t
0
)]
2
}= E{[x(t)]
2
} E{(t
J
-t
0
)
2
}
Hence, the jitter error power is
If the jitter is uncorrelated from sample
to sample, this jitter noise is white
E{e
2
} =
2
f
x
2
A
2
2
/6
A/D
DSP
The Jitter Law
( ) dB 172 . 5 log 20
3
6 /
2 /
10
2 2 2
2 2 2 2
2
jitter
=
=
=

x
x
x
f
f
A f
A
DR
55 dB
109 dB
83 dB
61 dB
DR
jitter
8.8
17.8
13.5
9.8
1 ns
2 ps
0.4 ps
0.5 ps
1 MHz
1 MHz
100 MHz
1000 MHz
ENOB f
x
A/D
DSP
The Jitter Law
The Jitter Law must be respected whenever you require high-
resolution conversion of high frequency signals
Sampling a 1MHz signal with 1nsec of peak-to-peak jitter yields a
dynamic range of only 55dB
In practice, jitter is usually controlled to add negligible to the
total converter error (i.e. thermal and quantization noise)
This translates into the jitter being ~10dB below other noise
sources
For 16 Bit conversion of 1MHz signals, a 109dB jitter DR limit
requires < 2 psec peak-to-peak jitter
A/D
DSP
The Jitter Law
Clock jitter in the single-digit picosecond range doesnt just
happen
Separate supplies
Separate analog and digital clocks
Short inverter chains between clock and sampling switch
Few, if any, other analog-to-digital conversion nonidealities have
the same symptoms as sampling jitter:
RMS noise proportional to input frequency
RMS noise proportional to input amplitude
So, if sampling clock jitter is limiting your dynamic range, its
easy to tell, but difficult to fix
Very difficult to fix in silicon without all-layer mask revisions
EECS 247 Lecture 16: ADC Architectures 2002 B. Boser 1
A/D
DSP
ADC Architectures
Serial ADC
Successive approximation
Flash
Folding
Time-interleaved / parallel converter
Residue type ADCs
Two-step
Pipeline
Algorithmic

Oversampled ADCs
A/D
DSP
Serial ADC
Low complexity
Very high accuracy achievable (digital volt-meter)
Slow: conversion time proportional 2
B
Ramp
Generator
Time
V
R
a
m
p
V
Ramp
V
IN
"0"
Counter
stop
start
A/D
DSP
Successive Approximation
Binary search over DAC output
High accuracy achievable (16+Bits)
Moderate speed proportional to B (1+MHz)
DAC
V
IN
Control
Logic
Clock
V
REF
V
DAC
/ V
REF
Time / Clock Ticks
1
1/2
3/4
5/8
V
IN
A/D
DSP
Flash Converter
Very fast: only 1 clock
cycle per conversion
High complexity:
2
B
-1 comparators
High input capacitance
R/2
R
R
R
R/2
R
Encoder
Digital
Output
V
IN V
REF
A/D
DSP
Folding Converter
Significantly fewer comparators than flash ~2
B/2+1
Fast
Nonidealities in folder limit resolution to ~10Bits
LSB
ADC
MSB
ADC
Folding Circuit
V
IN
Digital
Output
A/D
DSP
Time Interleaved Converter
Extremely fast:
Limited by speed of S/H
Accuracy limited by mismatch
in individual ADCs (timing,
offset, gain, )
S/H
f
s
ADC
f
s
ADC
f
s
+ T/4
ADC
f
s
+ 2T/4
ADC
f
s
+ 3T/4
S
e
r
i
a
l

/

P
a
r
a
l
l
e
l

C
o
n
v
e
r
s
i
o
n
V
IN
D
i
g
i
t
a
l

O
u
t
p
u
t
A/D
DSP
Residue Type ADC
Quantization error output (residuum) enables
cascading for higher resolution
Great flexibility for stages: flash, oversampling ADC,
Optional S/H enables parallelism (pipelining)
Fast: one clock per conversion (with S/H), latency
S/H
(optional)
coarse ADC
(1 ... 6 Bit)
Partial Digital Output
V
IN
Error DAC
A/D
DSP
Pipelined ADC
Approaches speed of flash, but much lower complexity
One clock per conversion, but K clocks latency
Efficient digital calibration possible
Versatile: from 16Bits / 1MS/s to 14Bits / 100MS/s
Digital Correction Logic
Stage 1
B
1
Bits
Stage 2
B
2
Bits
Stage K
B
k
Bits
Digital output
up to (B
1
+ B
2
+ ... + B
k
) Bits
V
IN
A/D
DSP
Algorithmic ADC
Essentially same as pipeline, but a single stage is
used for all partial conversions
K clocks per conversion
S/H
coarse ADC
(1 ... 6 Bit)
Digital Output
V
IN Error
DAC
Shift Register
& Correction Logic
start of conversion
A/D
DSP
Oversampled ADC
Hard to comprehend easy to build
Input is oversampled (M times faster than output rate)
Reduces Anti-Aliasing filter requirements and
capacitor size
Accuracy independent of component matching
Very high resolution achievable (>20 Bits)
H(z)
Digital
Decimation
Filter
DAC
V
IN
Digital
Output
f
s
f
s
/M
A/D
DSP
Speed Comparison
10
0
10
1
10
2
10
3
10
4
10
5
0
2
4
6
8
10
12
14
16
18
Clock Cycles per Conversion
R
e
s
o
l
u
t
i
o
n

[
B
i
t
]
Flash, Pipeline
Serial
Successive Approximation
Oversampled (L=2)
EECS 247 Lecture 17: Flash and Folding Converters 2002 B. Boser 1
A/D
DSP
High-Speed A/D Converter
Flash Converter
Comparator
Binary Encoder
Interpolation
Folding
A/D
DSP
Flash Converter
Very fast: only 1 clock
cycle per conversion
High complexity:
2
B
-1 comparators
High input capacitance
R/2
R
R
R
R/2
R
Encoder
Digital
Output
V
IN V
REF
A/D
DSP
Comparator
Clock rate f
s
Resolution
Overload Recovery
Input capacitance (and linearity!)
Power dissipation
Common-mode rejection
Kickback noise

A
v
Latch
V
i+
V
i-
D
o+
D
o-
f
s
A/D
DSP
CMOS Comparator Example
A. Yukawa, A CMOS 8-Bit High-Speed A/D Converter IC, JSSC June 1985, pp. 775-9.
A/D
DSP
Comparator with Auto-Zero
I. Mehr and L. Singer, A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications, JSSC
July 1999, pp. 912-20.
A/D
DSP
Auto-Zero Implementation
I. Mehr and L. Singer, A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC, JSSC March 2000, pp. 318-25.
A/D
DSP
Flash Converter Errors
Comparator input:
Offset
Nonlinear input capacitance
Kickback noise (disturbs
reference)
Signal dependent sampling time
Comparator output:
Sparkle codes ( 111101000 )
Metastability
R/2
R
R
R
R/2
R
Encoder
Digital
Output
V
IN V
REF
A/D
DSP
Sparkle Codes
Correct Output:
0110 1000
Actual Output:
1110
0
0
1
0
1
0
1
0
1
Binary Output (negative)
A/D
DSP
Sparkle Tolerant Encoder
0
0
1
0
1
0
1
0
0
0
Protects against a single sparkle.
Ref: C. Mangelsdorf et al, A 400-MHz Flash Converter with Error Correction, J SSC February
1990, pp. 997-1002.
A/D
DSP
Meta Stability
Different gates interpret
metastable output X differently
Correct Output: 0111 or 1000
Actual Output: 1111
Solutions:
Latches (high power)
Gray encoding
0
0
X
1
1
0
1
1
0
Ref: C. Portmann and T. Meng, Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters,
JSSC August 1996, pp. 1132-40.
A/D
DSP
Gray Encoding
Each T
i
affects only one G
i
Avoids disagreement of interpretation by multiple gates
Protects also against sparkles
Follow Gray encoder by (latch and) binary encoder
Binary Gray Thermometer Code
1 1 1 0 0 1 1 1 1 1 1 1 1
0 1 1 1 0 1 0 1 1 1 1 1 1
1 0 1 1 1 1 0 0 1 1 1 1 1
0 0 1 0 1 1 0 0 0 1 1 1 1
1 1 0 0 1 0 0 0 0 0 1 1 1
0 1 0 1 1 0 0 0 0 0 0 1 1
1 0 0 1 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0
B
1
B
2
B
3
G
1
G
2
G
3
T
7
T
6
T
5
T
4
T
3
T
2
T
1
4 3
6 2 2
7 5 3 1 1
T G
T T G
T T T T G
=
=
+ =
A/D
DSP
Reducing Complexity
E.g. 10-bit straight flash
Input range: 0 1V
LSB =: ~1mV
Comparators: 1023 with offset <<LSB
Input capacitance: 1023 * 100fF =102pF
Power: 1023 * 3mW =3W
Techniques:
Interpolation
Folding
Folding & Interpolation
Two-step, pipelining
A/D
DSP
Interpolation
Idea
Interpolation between preamp outputs
Reduces number of preamps
Reduced input capacitance
Reduced area, power dissipation
Same number of latches
Important side-benefit
Decreased sensitivity to preamp offset
improved DNL
A/D
DSP
Simulink Model
2
Y
1
Vi n
2*Delta
Vref2
1*Delta
Vref1
Vi
Preamp2
Preamp1
Vin
A2
A1
A/D
DSP
Preamp Output
Zero crossings (to be
detected by latches) at V
in
=
V
ref1
=1
V
ref2
=2
0 0.5 1 1.5 2 2.5 3
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Vin /
P
r
e
a
m
p

O
u
t
p
u
t
A
1
A
2
A/D
DSP
Differential Preamp Output
Zero crossings at V
in
=
V
ref1
=1
V
ref12
=0.5*(1+2)
V
ref2
=2
0 0.5 1 1.5 2 2.5 3
-0.4
-0.2
0
0.2
0.4
0.6
P
r
e
a
m
p

O
u
t
p
u
t
0 0.5 1 1.5 2 2.5 3
-0.4
-0.2
0
0.2
0.4
0.6
Vin /
A
1
+
A
2
A
1
-A
1
A
2
-A
2
A
1
+A
2
A/D
DSP
Interpolation in Flash ADC
Half as many reference voltages
and preamps
A/D
DSP
Resistive Interpolation
Ref: H. Kimura et al, A 10-b 300-
MHz Interpolated-Parallel A/D
Convterter, J SSC April 1993,
pp. 438-446.
Resistors produce
additional levels
With 4 resistors, the
interpolation factor M=8
(ratio of latches/pramps)
A/D
DSP
DNL Improvement
Preamp offset distributed over
M resistively interpolated
voltages:
impact on DNL divided by M
Latch offset divided by gain of
preamp
use largepreamp gain
A/D
DSP
Preamp Input Range
Linear preamp input ranges
must overlap
i.e. range >
Sets upper bound on gain
<<V
DD
/
0 0.5 1 1.5 2 2.5 3
-0.4
-0.2
0
0.2
0.4
0.6
P
r
e
a
m
p

O
u
t
p
u
t
A
1
-A
1
A
2
-A
2
0 0.5 1 1.5 2 2.5 3
-0.4
-0.2
0
0.2
0.4
0.6
Vin /
A
1
+
A
2
A
1
+A
2
A/D
DSP
Measured Performance
Ref: H. Kimura et al, A 10-b 300-MHz Interpolated-Parallel A/D Convterter, J SSC
April 1993, pp. 438-446.
A/D
DSP
Folding Converter
Significantly fewer comparators than flash ~2
B/2+1
Fast
Nonidealities in folder limit resolution to ~10Bits
LSB
ADC
MSB
ADC
Folding Circuit
V
IN
Digital
Output
A/D
DSP
Folding
Folder maps input to
smaller range
MSB ADC determines
which fold input is in
LSB ADC determines
position within fold
Logic circuit combines
LSB and MSB results
MSB ADC
LSB
ADC
Analog Input
0 0.5 1 1.5 2 2.5 3 3.5 4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
Vin /
F
o
ld
e
r

O
u
tp
u
t
A/D
DSP
Generating Folds
0 0.5 1 1.5 2 2.5 3 3.5 4
-0.5
0
0.5
A
1
0 0.5 1 1.5 2 2.5 3 3.5 4
-0.5
0
0.5
A
2
0 0.5 1 1.5 2 2.5 3 3.5 4
0
0.5
1
A
1
-
A
2
Vin /
0 0.5 1 1.5 2 2.5 3 3.5 4
0
0.5
1
A
1
-
A
2
0 0.5 1 1.5 2 2.5 3 3.5 4
-0.5
0
0.5
A
3
0 0.5 1 1.5 2 2.5 3 3.5 4
-0.5
0
0.5
A
1
-
A
2
+
A
3
Vin /
A/D
DSP
Folding Circuit
M1
10 / 1

M1
10 / 1

M2
10 / 1

M2
10 / 1

I1

I1

Vref1 Vref1
M3
10 / 1

M3
10 / 1

M3
10 / 1

M3
10 / 1

M3
10 / 1

M3
10 / 1

M3
10 / 1

M3
10 / 1

M4
10 / 1

M4
10 / 1

M4
10 / 1

M4
10 / 1

M4
10 / 1

M4
10 / 1

M4
10 / 1

M4
10 / 1

I2

I2

I2

I2

I2

I2

I2

I2

Vref2 Vref2 Vref2 Vref2 Vref2 Vref2 Vref2 Vref2
M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M5
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

M6
10 / 1

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

I3

Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3 Vref3
M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M7
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

M8
10 / 1

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

I4

Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4 Vref4
R1
1kOhm
R2
1kOhm
3 V 3 V
Vo2 Vo1
Vin
A/D
DSP
CMOS Folder Output
0 0.5 1 1.5 2 2.5 3 3.5 4
-0.5
0
0.5
F
o
l
d
e
r

O
u
t
p
u
t
0 0.5 1 1.5 2 2.5 3 3.5 4
-0.1
-0.05
0
0.05
0.1
E
r
r
o
r
Vin /
Ideal Folder
CMOS Folder
Accurate only at
zero-crossings
Lowdown
Most folding ADCs
do not actually use
the folds, but only the
zero-crossings!
A/D
DSP
Parallel Folders
V
ref
+ 3/4 *
Fine Flash
ADC 4
Folder 3
V
ref
+ 2/4 *
Fine Flash
ADC 3
Folder 2
V
ref
+ 1/4 *
Fine Flash
ADC 2
Folder 1
V
ref
+ 0/4 *
Fine Flash
ADC 1
Folder 4
Logic
A/D
DSP
Parallel Folder Outputs
0 1 2 3 4 5
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Vin /
F
o
l
d
e
r

O
u
t
p
u
t
F1
F2
F3
F4
4 Folders
8 Zero crossings
only 3 LSB bits
Better resolution
More folders
huge complexity
Interpolation
A/D
DSP
Folding & Interpolation
V
ref
+ 3/4 *
Fine
Flash
ADC
Folder 3
V
ref
+ 2/4 *
Folder 2
V
ref
+ 1/4 *
Folder 1
V
ref
+ 0/4 *
Folder 4
Encoder
A/D
DSP
Folder / Interpolator Output
0 1 2 3 4 5
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Vin /
F
o
l
d
e
r

/

I
n
t
e
r
p
o
l
a
t
o
r

O
u
t
p
u
t
F1
F2
I1
I2
I3
1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
Vin /
F
o
ld
e
r

/
In
te
r
p
o
la
to
r

O
u
tp
u
t
F1
F2
I1
I2
I3
A/D
DSP
Folder / Interpolator Output
0 1 2 3 4 5
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Vin /
F
o
l
d
e
r

/

I
n
t
e
r
p
o
l
a
t
o
r

O
u
t
p
u
t
F1
F2
I1
I2
I3
1.5 1.6 1.7 1.8 1.9 2 2.1
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
Vin /
F
o
ld
e
r

/
In
te
r
p
o
la
to
r

O
u
tp
u
t
F1
F2
I1
I2
I3
Interpolate only
between closely
spaced folds to avoid
nonlinear distortion
A/D
DSP
A 70-MS/s 110-mW 8-b CMOS Folding
and Interpolating A/D Converter
B. Nauta and G. Venes, J SSC Dec 1985, pp. 1302-8
A/D
DSP
A 70-MS/s 110-mW8-b CMOS Folding and Interpolating A/D Converter
A/D
DSP
A 70-MS/s 110-mW8-b CMOS Folding and Interpolating A/D Converter
EECS 247 Lecture 18: Pipelined ADC 2002 B. Boser 1
A/D
DSP
Pipelined A/D Converter
Model
Digital Correction
Digital Calibration
A/D
DSP
Pipelined ADC
Digital Correction Logic
Stage 1
B
1
Bits
Stage 2
B
2
Bits
Stage K
B
k
Bits
Digital output
up to (B
1
+ B
2
+ ... + B
k
) Bits
V
IN
S/H & Gain
(optional)
coarse ADC
(1 ... 6 Bit)
Partial Digital Output
V
IN
Error
DAC
A/D
DSP
Pipeline Stage Model
See Matlab/Simulink L18_pipe_3_el.mdl
in Matlab window:
points =100
(number of points/lsb
in simulation)
Pipeline Stage, 3 ADC levels
Sum
S/H
Residuum
Ramp
Later Stages
4
Gai n
Digital Output
In Out
DAC
Corrected Output
In Out
ADC Dout
Dout
residuum
( )
ref in res
DV V G V =
A/D
DSP
Simulation of 2-Bit Stage
A/D
DSP
in Matlab window:
points =10
in simulation)
Pipeline ADC, 2 bits per stage
ADC level off in 1st stage
Sum
Residuum 2 Residuum 1
Ramp
Ain
Error
Dout
Pipeline Stage 2
Ain
Residuum
Dout
Pipeline Stage 1
4
Gain
ADC Dout
Pipeline ADC Model
See Matlab/Simulink L18_pipe_2bps_error.mdl
A/D
DSP
Simulation Result
A/D
DSP
Comparator Offset
First stage ADC Levels:
Ideal: -1, 0, +1
Error: -1, 0.3, +1
Problem: Residuum 1 exceeds overloads
2
nd
pipeline stage
Missing Code!
A/D
DSP
Digital Correction
in Matlab window:
points =10
in simulation)
Interstage gain = 2 for digital correction
Sum
Ramp
Ain
Error
Dout
Pipeline Stage 2
Ain
Residuum
Dout
Pipeline Stage 1
2
Gain
ADC Dout
Reduced interstage gain:
No overload (due to comparator offset)
Reduced input (only 1 bit resolution per stage)
A/D
DSP
Digital Correction
enlarged residuum still within
+/-2 input range of next stage
Only 1 Bit resolution from first
stage (3 Bit total)
A/D
DSP
1.5-bps Stage
Pipeline ADC, 1.5 bit per stage (2 comparators per stage)
in Matlab window:
points = 50
in simulation)
Sum
Residuum 3 Residuum 2 Residuum 1
Ramp
Ain
Error
Dout
Pipeline Stage 3
Ain
Error
Dout
Pipeline Stage 2
Ain
Error
Dout
Pipeline Stage 1
2
Gai n6
4
Gain5
Dout
A full bit of overrange is excessive for typical comparator offset
use only 2 (rather than 3) comparators and G=2
3 DAC levels lb(3) = 1.585 Bits
Overall resolution:
1 bps for all stages but last
1.585 Bit for last
A/D
DSP
1.5-bps Pipeline
What is the maximum
offset that can be
corrected?
What is the offset of
each comparator in
this example?
A/D
DSP
Interstage Gain Error
1 0.5 0 0.5 1
1
0
1
First Stage Residue (Gain Error)
Vin
V
r
e
s
1 0.5 0 0.5 1
1
0
1
Converter Transfer Function (Gain Error)
Vin
D
o
u
t
1 0.5 0 0.5 1
0.2
0
0.2
Transfer Function Error(Gain Error)
Vin
D
o
u
t
(
i
d
e
a
l
)

-

D
o
u
t
A/D
DSP
Digital Gain Calibration
Operation of the pipeline stage:
The gain G is off from its correct value (e.g. 1.8 instead of 2)
Digital output from the ADC
Gain error (GV
in
term)
Nonlinearity at segment boundary (DGV
ref
term)
( )
ref in res
DV V G V =
res ref in
V DGV GV + =
A/D
DSP
Digital Gain Calibration
The digital gain in the circuit
at right is still 2
The actual amplifier gain in
stage 1 is smaller or larger due
to component mismatch
E.g.
GV
ref
=1000101101
GV
ref
=1000000000
Hence the overall output is
incorrect, regardless of the
accuracy of stage 2
res ref in
V DGV GV + =
in Matlab window:
points =10
in simulation)
Interstage gain = 2 for digital correction
Sum
Ramp
Ain
Error
Dout
Pipeline Stage 2
Ain
Residuum
Dout
Pipeline Stage 1
2
Gain
ADC Dout
Analog circuit gain
Digital circuit gain
A/D
DSP
Measuring GV
ref
If we knew the value of GV
ref
, we could use use that in our digital logic,
rather than G=2
How can we measure GV
ref
?
If we proceed from the back of the pipeline, we can use the already
calibrated backend to digitize GV
ref
!
The measurement is performed once at startup, the values stored in a
small RAM (one per stage for 1-bps stage resolution)
The digital logic uses adders to sum up the different values of GV
ref
from the table stored in the RAM
( )
( )
ref resB resA
ref x x in res resB
x x in res resA
GV V V
GV GV D V V V V
GV D V V V V
=
= = = =
= = = =
1 ,
0 ,
A/D
DSP
1-Bit per stage
Only 1 comparator per
stage
G<2 to avoid overload in
presence of comparator
offset
Digital gain calibration
EECS 247 Lecture 19: Oversampling 2002 B. Boser 1
A/D
DSP
Oversampled ADCs
One-bit quantization
Quantization noise shaping
A first-order, 1-Bit sigma-delta modulator
The name sigma-delta, delta-sigma, , ,
Time domain model
Small-signal model
Oversampling
A/D
DSP
Oversampling
Nyquist rate ADCs
Sample at f
s
around 2x bandwidth
Resolution set by number of decision levels of quantizer
Oversampled ADCs
Sample at f
s
>>bandwidth (16 500x)
Use few quantization levels (typical 1-Bit)
Employ DSP to reduce quantization error
A/D
DSP
One-Bit Quantization
Lets examine some properties of one bit random
sequences
Values in the sequence are constrained to be either +1 or 1
By picking +1s and 1s at random (using MATLABs
rand.m random number generator), we generate a
sequence with zero mean
The sequence values model outputs of a hypothetical 1-Bit,
1MHz ADC
Nothing stops us from doing a DFT of this sequence
A/D
DSP
Zero Mean 1-Bit DFT
Frequency (kHz)
A
m
(
d
B
W
N
)0
-30
-60
-90
0 400 300 200 100 500
30
A/D
DSP
One-Bit DFTs
For 1-Bit DFT plots, well use a different normalization
scheme
The dBWN (dB White Noise) scale sets the 0dB line at the
noise/bin of a random +1, -1 sequence
From the energy theorem,
n=0
N-1
a
n
m=0
N-1
A
m
2
1
N
= N =
A
m
= N
(+1)
2
or (1)
2
= 1
A/D
DSP
Zero Mean 1-Bit DFT
average of 30 spectra
Frequency (kHz)
A
m
(
d
B
W
N
)
0
-30
-60
-90
0 400 300 200 100 500
30
A/D
DSP
Non-zero Mean Sequences
Of course, 1-Bit sequences can represent dc
inputs from 1 to +1
For example, an average value of +1/11 can
be generated by a sequence with
5/11 probability of 1
6/11 probability of +1
Lets look at DFTs of a non-zero mean
sequence
A/D
DSP
+1/11 Mean 1 Bit DFT
Frequency (kHz)
A
m
(
d
B
W
N
)
0
-30
-60
-90
0 400 300 200 100 500
30
A/D
DSP
+1/11 Mean 1-Bit DFT
Frequency (kHz)
A
m
(
d
B
W
N
)
0
-30
-60
-90
0 400 300 200 100 500
30
averaging makes the dc component clearly visible
A/D
DSP
+1/11 Minimum Error Sequence
No random number generator is required to produce
the 1-Bit sequence which represents +1/11 with the
minimum mean-squared quantization error
This 11 term sequence averages to 1/11:
[1 +1 1 +1 1 +1 1 +1 1 +1 +1]
The sequence in []s repeats
Its DFT follows
A/D
DSP
+1/11 Minimum Error DFT
Frequency (kHz)
A
m
(
d
B
W
N
)0
-30
-60
-90
0 400 300 200 100 500
30
f
S
11
f
S
11
f
S
2
1
2
A/D
DSP
+1/11 Minimum Error Sequence
Minimum error is periodic error with a period of f
s
/11
Note that the fundamental term in this Fourier series is the
smallest (a bit unusual)
A quantization noise model is completely
inappropriate for this type of sequence
Lets deliberately increase the quantization error a
little and attack its periodicity
A/D
DSP
3 Pattern Options
Generate another 1-Bit sequence by concatenation of
the following sequences:
[1 +1 1 +1 1 +1 1 +1 +1]
[1 +1 1 +1 1 +1 1 +1 1 +1 +1]
[1 +1 1 +1 1 +1 1 +1 1 +1 1 +1 +1]
Selection of the above 9, 11, and 13 term sequences
at random yields an average of +1/11 and the
following DFT
A/D
DSP
3 Pattern Options DFT
Frequency (kHz)
A
m
(
d
B
W
N
)0
-30
-60
-90
0 400 300 200 100 500
30
A/D
DSP
3 Pattern Options
The randomized concatenation of longer patterns
certainly breaks up periodic error
Some concentration of energy near f
s
/11 and its harmonics
(especially 5f
s
/11) is still visible
Noise below 50kHz is significantly lower than that of
the sample-by-sample random sequences of slide 9
The noise shaping obtained with 3 pattern options benefits
low frequencies at the expense of increased quantization
error at high frequencies
A/D
DSP
3 Pattern Options DFT
Frequency (kHz)
A
m
(
d
B
W
N
)
0
-30
-60
-90
0 400 300 200 100 500
30
A/D
DSP
5 Pattern Options
Lets add two more patterns to our set of pattern options:
[1 +1 1 +1 1 +1 1 +1 1 +1 1 +1 1 +1 +1]
[1 +1 1 +1 1 +1 +1]
Selection of 7, 9, 11, 13, and 15 term sequences at
random preserves the +1/11 average
Think of this process as a sort of time-variant dither
DFT follows
A/D
DSP
3/5 Pattern Options
Frequency (kHz)
A
m
(
d
B
W
N
)
0
-30
-60
-90
0 400 300 200 100 500
30
3 options
5 options
A/D
DSP
5 Pattern Noise Shaping
Noise vs. frequency still follows the general upward
tilt of the periodic error harmonics
5 pattern options further reduce the f
s
/11 bump
The 5f
s
/11 component remains large
The model that quantization error is uncorrelated with
the input signal becomes reasonable with only 5
pattern options
Such reasonableness is required for small-signal analysis of
the sigma-delta modulator
A/D
DSP
Sigma- Delta Modulators
Analog 1-Bit modulators convert a continuous time
analog input v
IN
into a 1-Bit sequence d
OUT
H(z)
+
_
v
IN
d
OUT
+1 or -1
Loop filter 1b Quantizer (a comparator)
f
s
A/D
DSP
Sigma-Delta Modulators
The loop filter H can be either a SC or continuous time
SCs are easier to implement and scale with the clock rate
Continuous time filters provide anti-aliasing protection
Can be realized with passive LCs at very high frequencies
H(z)
+
_
v
IN
d
OUT
+1 or -1
f
s
A/D
DSP
1
st
Order Modulator
In a 1
st
order modulator, the loop filter is an integrator
+
_
v
IN
d
OUT
+1 or -1
H(z) =
z
-1
1 z
-1
A/D
DSP
1
st
Order Modulator
Properties of the first-order modulator:
Analog input range is the d
out
times the DAC reference
The average value of d
OUT
must equal the average value of v
IN
+1s (or 1s) density in d
OUT
is an inherently monotonic function of v
IN
linearity is not dependent on component matching
Alternative multi-bit DAC (and ADCs) solutions reduce the quantization error
but loose this inherent monotonicity
+
_
v
IN
d
OUT
+1 or -1
-/2v
IN
+/2
DAC
-/2 or +/2
A/D
DSP
Simulation
0 10 20 30 40 50 60
-1.5
-1
-0.5
0
0.5
1
1.5
Time [ t/T ]
A
m
p
l
i
t
u
d
e
X
Q
Y
3
Y
2
Q
1
X
Sine Wave
z
-1
1-z
-1
Discrete Filter Comparator
see L19_level1
A/D
DSP
1
st
Order , +1/11 dc Input
Lets continue our +1/11 dc input example with the
modulator sampling frequency of 1MHz
A 1024 sample DFT plot appears on the following
slide
A/D
DSP
1
st
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
Frequency [ f/f
s
]
A
m
p
lit
u
d
e

[

d
B
W
N

]
Looks familiar?
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Time [t/11]
A
m
p
lit
u
d
e
A/D
DSP
1
st
A check of the time samples confirms the
obvious: the 1
st
order modulator produces
the minimum error 11 term sequence:
[1 +1 1 +1 1 +1 1 +1 1 +1 +1]
Of course, with this modulator model we can
look at much more interesting inputs than
dc
A/D
DSP
1
st
Order , Sinewave Input
v
IN
(k) = 0.99sin(2 0.100001 t)
d
OUT
= [ +1 1 +1 +1 +1 +1 1 1 1 1 ]
0 0.1 0.2 0.3 0.4 0.5
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
Frequency [ f/f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
W
N

]
A/D
DSP
1
st
Order , Sinewave Input
The modulator output for the undistorted sinewave
input produces huge distortion, suggesting the need
for dither
Well add a dither signal q at the comparator input:
+
_
v
IN
d
OUT
+
q
A/D
DSP
Dithered 1
st
Order
0 0.1 0.2 0.3 0.4 0.5
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
Frequency [ f/f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
W
N

]
single DFT
average
q: = /2
A/D
DSP
Dithered 1
st
Order
1Vrms Gaussian dither is difficult if not impossible to
produce on mixed-signal ICs
On-chip digital circuitry adds excessive non-Gaussian
interference to analog noise generators
First-order modulators are too prone to limit cycles to
be of much practical use
They do provide the basis for higher-order s
A/D
DSP
1
st
Order Noise Shaping
If q(k) and v
IN
(k) are uncorrelated, we can compute the signal and noise
transfer functions independently:
How do we model the quantizer?
+
_
v
IN
d
OUT
+
q
H(z) =
z
-1
1 z
-1
( )
( )
( )
( )
( )
( )
in in
out
z V
z Q
z NTF
z V
z D
z STF = =
A/D
DSP
Nonlinear elements like comparators are frequently
modeled by some sort of linearized effective gain, G
One measure of effective gain thats proven itself
useful for analysis is:
The value of G depends on the input signal and can
be determined with simulation
E.g. for the simulation in slide 30, G=0.7 (-3.1dB)
1
st
Order Noise Shaping
G
rms value of the comparator output
rms value of the comparator input
A/D
DSP
1
st
Order Noise Shaping
The input q models both dither, if added, andthe
input-referred noise of the comparator
+
_
v
IN d
OUT
+
q
H(z)
G
A/D
DSP
1
st
Order Noise Shaping
+
_
v
IN
d
OUT
+
q
H(z)
G
) ( 1

) ( 1
) (
z GH
G
V
Q
NTF
z GH
z GH
V
D
STF
in in
out
+
= =
+
= =
When H(z) is large, this is approximately 1.
A/D
DSP
1
st
Order Noise Shaping
+
_
v
IN
d
OUT
+
q
H(z)
G
) ( 1

) ( 1
) (
z GH
G
V
Q
NTF
z GH
z GH
V
D
STF
in in
out
+
= =
+
= =
For large H(z), this is 0.
A/D
DSP
Noise Transfer Function, NTF
0 0.1 0.2 0.3 0.4 0.5
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
Frequency [ f/f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
W
N

]
Output Spectrum
NTF
A/D
DSP
Integrated Noise
J ust as we did for thermal noise, lets look at
the integrated noise at the output of the
modulator
In the discrete time case, noise integrals are
summations, but the result is called
integrated noise nonetheless
A/D
DSP
Noise Summations
Integrated noise is computed from the
energy theorem (N even):
a
rms
= A
0
/ N , M=0
a
rms
=
m=1
M
2A
m
2
1
N
A
0
+
2
, 0<M<N/2
a
rms
=
m=1
N/2-1
2A
m
2
1
N
A
0
+
2
, M=N/2 A
N/2
+
2
A/D
DSP
Integrated Noise
0 0.1 0.2 0.3 0.4 0.5
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
Frequency [ f/f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
W
N

]

/

I
n
t
e
g
r
a
t
e
d

N
o
i
s
e

[
d
B
V
]
Output Spectrum
Integrated Noise
The total noise at
the modulator
output with no input
sums to 0dB
This is consistent
with a binary signal
A/D
DSP
Integrated Output
The total power still
sums to 0dB
Only little
quantization noise
at low frequency
0 0.1 0.2 0.3 0.4 0.5
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
Frequency [ f/f
s
]
A
m
p
l
i
t
u
d
e

[

d
B
W
N

]

/

I
n
t
e
g
r
a
t
e
d

N
o
i
s
e

[
d
B
V
]
Output Spectrum
Integrated Noise
A/D
DSP
Oversampling and Noise Shaping
modulators have interesting characteristics
Unity gain for the the input signal V
IN
Large attenuation of quantization noise injected at q
Much better than 1-Bit noise performance is possible if were
only interested in frequencies <<f
s
ADCs which sample their inputs at much higher
frequencies than the Nyquist rate minimum are called
oversampling ADCs
A/D
DSP
Oversampling and Noise Shaping
Higher order loop filters consisting of several integrators
provide much better noise shaping than 1
st
order realizations
They are also less prone to limit cycles or need less dither
If a 1-Bit DAC is used, the converter is inherently linear
independent of component matching
References
J . C. Candy and G. C. Temes, Oversampling Methods for A/D and D/A Conversion, Oversampling
Delta-Sigma Data Converters: Theory, Design, and Simulation, 1992, pp. 1-25.
S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters, Theory, Design, and
Simulation,IEEE Press, 1997.
A/D
DSP
Estimating Quantization Noise
+
_
v
IN
Y
+
q
H(z)
G
( )
) ( 1 z GH
G
z NTF
+
=
( )
( ) ( )
=
=
=
B
B
e z
Q Y
s
Q
df z NTF f S S
f
f S
jfT
2
2
2
12
1

A/D
DSP
Example: 1
st
Order Modulator
( )
( )
( ) ( ) ( )
( )( )
fT
T
z z
z z
z NTF z NTF z NTF
z z NTF
G
z
z
z H
sin 2
cos 2 2
1 1
1 1
1
1
1
1
1
1
2
1
1
1
=
=
+ =
=
=
=
=
( ) ( )
( )
12
1
3
sin 2
12
1
2
3
2
2
2
2
2
=
M
df fT
f
df z NTF f S S
M
s
f
M
s
f
jfT
s
B
B
e z
Q Y

A/D
DSP
Example: Dynamic Range
3
2
2
3
2
2
2
9
12
1
3
1 input, sinusoidal
2 2
1
power noise peak
power signal peak
M DR
M
S
STF S
S
S
DR
Y
X
Y
X
=
=

=
= =
M DR
16 33 dB
32 42 dB
1024 87 dB
A/D
DSP
Dynamic Range
DR increases 9dB for each doubling of M
1
st
order modulators require very high M for >10-Bit resolution
higher order filters improve this tradeoff substantially
Analysis is based on assumption that the quantization noise is
white
not true in practice, especially for low-order modulators
practical modulators suffer from other noise sources also
(e.g. thermal noise)
Next time well design an oversampled audio ADC with better
than 16-Bit resolution
EECS 247 Lecture 20: 5th Order Architecture 2002 B. Boser 1
A/D
DSP
Overview
Building behavioral models in stages
A 5
th
-order, 1-Bit modulator
Noise shaping
Complex loop filters
Stability
Voltage scaling
A/D
DSP
Building Models in Stages
When modeling a complex system like a 5
th
-order
modulator, model development proceeds in stages
Each stage builds on its predecessor
The design goal is to detect and eliminate problems
at the highest possible level of abstraction
Each successive stage consumes progressively more
engineering time
A/D
DSP
Rework and reverification of early stage models
because of problems found in later stages is
expensive
Defective silicon is much more expensive
(and often fatal)
Dont launch a multistage rework cycle every time
you find a single bug
A/D
DSP
Our model development proceeds in
stages:
Stage 0 gets to the starting line
Stage 1 develops a practical system built with
ideal subcircuits
Stage 2 models key subcircuit nonidealities and
translates the results into real-world subcircuit
performance specifications
A/D
DSP
Real-world model development includes a critical
stage 3:
Adding elements to earlier stages (hopefully only stage 2) to
model significant surprises found in silicon
The previous lecture introduced much of the stage 0
model and 1-Bit quantization background
What other steps are needed to arrive at a successful
design?
A/D
DSP
Stage 0
Collect references
Important references
Readable references
Talk to veterans to find them and sort them
Understand the readable references
Build a simple model of what you think you understand
Start building diagnostic infrastructure
A/D
DSP
Stage 0 Models
You cant just talk about stage 0 models with
veterans and look at their stage 0 simulations
Youve got to exercise and think with the model until you can
begin to explain surprises by yourself
Then, in stage 1, you can ask a veteran more intelligent
questions
Stage 0 model code (download code used for last
lecture) is 20% modulator loop code, 80%
diagnostics
This ratio holds for all stages of modeling
A/D
DSP
Stage 1
In stage 1, well study a model for a practical
modulator topology built with ideal blocks
Stage 1 model focus
Signal amplitudes
Stability
Worst-case inputs
Unstable systems cant graduate to stage 2
Quantization noise shaping
A/D
DSP
Stage 1 Models
Building the infrastructure to generate worst-case inputs
and analyze model responses is of critical importance in
stage 1
You must tap into your organizations technical wisdom to
learn what those worst-case real world inputs are
Models can only tell you the right answers if you ask
them the right questions!
A/D
DSP
Modulator Filter Design
Procedure
Establish requirements
Design noise-transfer function, NTF
Determine loop-filter, H
Synthesize filter
Evaluate performance, stability
Ref: R. W. Adams and R. Schreier, Stability Theory for Modulators,
in Delta-Sigma Data Converters, S. Norsworthy et al. (eds), IEEE
Press, 1997, pp. 141-164.
A/D
DSP
Modulator Specification
Example: Audio ADC
Dynamic range DR 16 Bits
Signal bandwidth B 20 kHz
Nyquist frequency f
N
44.1 kHz
Modulator order L 5
Oversampling ratio M =f
s
/f
N
64
s
2.822 MHz
The oversampling ratio M chosen based on
SQNR >120dB (20dB below thermal noise)
Experience (e.g. Figure 4.14 in Adams & Schreier)
A/D
DSP
Modulator Block Diagram
H(z)
+
_
v
IN
d
OUT
+1 or -1
Loop filter
Gain Block
g
A/D
DSP
Noise Transfer Function, NTF(z)
% stop-band attenuation ...
% reduce if design is not stable
Rstop = 80;
[b,a] = cheby2(L, Rstop, 1/M, 'high');
% normalize (for causality)
b = b/b(1);
NTF = filt(b, a, 1/fs);
% check stability (mag < 1.5)
[mag] = bode(NTF, pi*fs)
>> mag = 1. 32
10
4
10
6
-100
-80
-60
-40
-20
0
20
Frequency [Hz]
N
T
F

[
d
B
]
A/D
DSP
Loop-Filter, H(z)
H = inv(NTF) - filt(1, 1, 1/fs);
% check causality y(1) should be 0
y = impulse(H);
y = y(1)
>> y = 0
10
4
10
6
-20
0
20
40
60
80
100
Frequency [Hz]
L
o
o
p
f
i
l
t
e
r

H

[
d
B
]
A/D
DSP
Filter Topology
7
Q
6
I_5
5
I_4
4
I_3
3
I_2
2
I_1
1
Y
b2
b2
b1
b1
a1
a5
a3
a4
a3
a3
a2
a2
a1
a1
k5z
-1
1-z
-1
I5
k4z
-1
1-z
-1
I4
k3z
-1
1-z
-1
I3
k2z
-1
1-z
-1
I2
k1z
-1
1-z
-1
I1
Dither
Comparator
1
X
A/D
DSP
Rounded Filter Coefficients
a1=1;
a2=1/2;
a3=1/4;
a4=1/8;
a5=1/8;
k1=1;
k2=1;
k3=1/2;
k4=1/4;
k5=1/8;
b1=1/1024;
b2=1/16-1/64;
Ref: Nav Sooch, Don Kerth, Eric Swanson, and Tetsuro Sugimoto, Phase
Equalization System for a Digital-to-Analog Converter Using Separate Digital
and Analog Sections, U.S. Patent 5061925, 1990, figure 3 and table 1.
A/D
DSP
5
th
-Order Noise Shaping
Frequency [kHz]
A
m
(
d
B
W
N
)

o
r
I
n
t
e
g
r
a
t
e
d

N
o
i
s
e

(
d
B
V
)
0
-40
-120
-160
0 1200 900 600 300 1500
40
-80
100mVrms, 30kHz input
30000 point DFT
30 averages
Thats noise shaping! lets look closer
A/D
DSP
5
th
Frequency [kHz]
A
m
(
d
B
W
N
)

o
r
I
n
t
e
g
r
a
t
e
d

N
o
i
s
e

(
d
B
V
)
0
-40
-120
-160
0 40 30 20 10 50
40
-80
3 Q
noise
zeroes
only 82nVrms from
DC to 20kHz
A/D
DSP
5
th
Frequency [kHz]
A
m
(
d
B
W
N
)

o
r
I
n
t
e
g
r
a
t
e
d

N
o
i
s
e

(
d
B
V
)
0
-40
-120
-160
0 40 30 20 10 50
40
-80
output noise after this digital
filter is applied to the 1-Bit
data is only 82nVrms
A/D
DSP
5
th
The 1Vrms 1-Bit quantization noise is shaped
to sum to only 82nVrms in the audio band
Thats over 140dB of dynamic range
modulators are usually designed so that
their quantization noise is negligible in the
frequency band of interest
Thermal noise sources dominate
Lets look at the loop filter transfer function
A/D
DSP
5
th
-Order Loop Filter
Frequency [kHz]
G
a
i
n

(
d
B
)

o
r

P
h
a
s
e

(

)
200
100
0
- 100
- 200
0 1200 900 600 300 1500
Lots of low frequency gain
0dB gain at 378kHz
A/D
DSP
5
th
-Order Loop Filter
Frequency [kHz]
G
a
i
n

(
d
B
)

o
r

P
h
a
s
e

(

)
200
100
0
- 100
- 200
0 40 30 20 10 50
upward phase jumps imply
poles just outside the unit circle
A/D
DSP
5
th
-Order Loop Filter
Frequency [kHz]
G
a
i
n

(
d
B
)

o
r

A
m
(
d
B
W
N
)

200
100
0
- 100
- 200
0 40 30 20 10 50
But is this noise shaping
too good to be true?
|H(z)| maxima provide
Qnoise minima
A/D
DSP
5
th
-Order Loop Filter
The fact that H(z) has poles outside the unit
circle doesnt mean that the entire
modulator is unstable
The modulators stability depends on its closed
loop poles
All loop variables ( 1, 2, 3, 4, 5) have the
same closed loop poles
If one is stable, they all are
A/D
DSP
Modulator Root-Locus
The nonlinear modulator system operates at some
effective gain G between points A and B:
H(z)
+
_
v
IN
d
OUT
+1 or -1
A
B
g
v
B
v
A
G
A/D
DSP
G may be a function of both v
IN
and g
The modulator closed loop poles are the zeroes of
the function 1+HG:
Well plot closed loop poles in the z-plane as G varies
from 0.1 to 10 in equal log steps
D
OUT
(z)
V
IN
(z)
HG/g
1 + HG
=
A/D
DSP
unit circle
A/D
DSP
unit circle
start (G=0.1) unstable
A/D
DSP
unit circle
stop (G=10) stable
A/D
DSP
unit circle
Closed-loop poles move
inside the unit circle for
G > 0.4
A/D
DSP
Effective Gain
If our linearized model is valid (a big if)
For G >0.4, the modulator system is stable
For G <0.4, its unstable
Presumably, the noise shapes in slides 18 and 23
were produced by a stable system
Well evaluate G for 5kHz and 20kHz sinusoidal inputs
varying in amplitude from 30dBV to +5dBV
While were at it, well capture minimum and maximum signal
levels throughout the modulator
A/D
DSP
Sinewave Input Effective Gain
Input Amplitude [dBV]
E
f
f
e
c
t
i
v
e

G
a
i
n
2
1.5
1
0.5
0
-30 -5 -10 -15 -25 0 -20 +5
Both 5kHz and 20kHz look
DC like to a 3MHz modulator
A/D
DSP
Effective Gain
As the input amplitude increases, the signal at the
quantizer input grows, and G falls
J ust over 1Vrms, G falls to below 0.4, and
The system becomes unstable
Loop variables grow without bound
(opamps in a real analog circuit will just run up to power
supply rails)
Noise shaping is lost
A/D
DSP
Effective Gain
Its highly unlikely that audio sinewaves provide the
worst case inputs for stability
To evaluate any model, youve got to know what the worst
case inputs are
Lets look at inputs that arent dc-like and arent
sinusoidal (square waves)
A/D
DSP
300kHz Input Effective Gain
Sinewave Input Amplitude [dBV]
E
f
f
e
c
t
i
v
e

G
a
i
n
2
1.5
1
0.5
0
-30 -5 -10 -15 -25 0 -20 +5
Equal P-P inputs:
300kHz sinewave
300kHz square wave
A/D
DSP
Modulator Stability
The sensitivity of modulators to high frequency
square wave inputs was first discovered on
breadboards
No one thought to provide such inputs to early modulator
simulations
Worst-case square wave frequencies are roughly
equal to the frequency of the highest Q pole in the
noise shape
A key job of the antialiasing filters used in front of
modulators is to reduce out-of-band signals to safe levels
A/D
DSP
Modulator Stability
5000 point simulations such as those in the previous
slides dont guarantee stability
Sometimes millions of time points are required before an
unstable modulator blows up
When it explodes, G falls very quickly
Square wave tolerance is a fast, effective basis for
comparing the relative stability of different modulator
topologies
A/D
DSP
Voltage Scaling
Given that the modulator is stable for 1Vrms inputs,
lets move on to look at the state variable voltages
under various input conditions
Loop state variables and the filter output are labeled green
on the next slide
Peak signal levels and signal standard deviations are
easy to obtain in MATLAB
Well examine voltages for a 5kHz sinusoidal input
A/D
DSP
5
th
-Order Loop Filter
_
k
1
1-z
-1
+ +
_
+
b
1
a
2
b
2
a
1
a
3
a
4
a
5
IN
(from
summer)
OUT (to comparator)
k
2
z
-1
1-z
-1
k
3
z
-1
1-z
-1
k
4
z
-1
1-z
-1
k
5
z
-1
1-z
-1
1 2 3 4
5
Q
A/D
DSP
5kHz Input Loop Voltages
L
o
o
p

P
e
a
k

V
o
l
t
a
g
e
s

[
V
]
40
20
0
-20
-40
-30 -5 -10 -15 -25 0 -20 +5
Positive Peaks
Negative Peaks
1
2
3
4
5
Q
A/D
DSP
5
th
-Order Loop Filter
_
k
1
1-z
-1
+ +
_
+
b
1
a
2
b
2
a
1
a
3
a
4
a
5
IN
(from
summer)
k
2
z
-1
1-z
-1
k
3
z
-1
1-z
-1
k
4
z
-1
1-z
-1
k
5
z
-1
1-z
-1
1 2 3 4
5
Q
Only the sign of Q matters,
so we can make k
1
whatever we want
without changing the 1-Bit data at all
A/D
DSP
5kHz Input Loop Voltages
If we scale k
1
by 0.1,
All state variables and Q scale by 0.1
But since the comparator output is fixed, G increases 10X
The change in k
1
doesnt change the shape of the
root locus, either
The effective gain for each root position is increased 10X
G >4 is now required for stability
A/D
DSP
5kHz, k
1
=0.1 Effective Gain
E
f
f
e
c
t
i
v
e

G
a
i
n
20
15
10
5
0
-30 -5 -10 -15 -25 0 -20 +5
A/D
DSP
k
1
=0.1 Loop Voltages
L
o
o
p

P
e
a
k

V
o
l
t
a
g
e
s

[
V
]
4
2
0
-2
-4
-30 -5 -10 -15 -25 0 -20 +5
Positive Peaks
Negative Peaks
1
2
3
4
5
Q
A/D
DSP
Loop Voltage Scaling
Before we scale k
1
down any lower, we note
that 3, 4, and 5 have substantially larger
swings than 1 and 2
J ust about any filter topology allows scaling
tricks which change internal state variable
amplitudes without changing the filter output
The next slide shows an example
A/D
DSP
Scaling Example
_
k
1
1-z
-1
+ +
_
+
B
1
/S
a
2
Sb
2
a
1
a
3
/S
a
4
a
5
IN
(from
summer)
k
2
z
-1
1-z
-1
Sk
3
z
-1
1-z
-1
k
4
z
-1
/S
1-z
-1
k
5
z
-1
1-z
-1
1 2 S3 4
5
Q
A/D
DSP
Input Range Scaling
Slides 40 and 44 indicate inadequate stability
margins for 1Vrms sinewave inputs
Scaling the DAC output levels adjusts the modulator
input range
If V
IN
and the DAC outputs are scaled up by the same factor
g, the 1-Bit data is completely unchanged
Of course, increasing the range also increases the
quantization noise the dynamic range and peak SQNR
stay the same!
If the DAC output levels are increased and the analog full
scale is held constant, the stability margin improves at the
expense of reduced SQNR
A/D
DSP
Input Range Scaling
Increasing the DAC levels by g reduces the analog to
digital conversion gain:
H(z)
+
_
v
IN
d
OUT
+1 or -1
g
D
OUT
(z)
V
IN
(z)

1
g
increasing v
IN
, g by the same factor leaves 1-Bit data unchanged
=
H
1+gH
A/D
DSP
Stage 1 Modulator
Well increase g from 2.5 to 3.0 to provide a 2dB
increase in stability margin for a 1Vrms full scale
input
Well also implement the loop voltage scaling
changes suggested in slide 45
The result is our first-pass stage 1 modulator, and its
performance appears on the following slides
A/D
DSP
Modulator Effective Gain
E
f
f
e
c
t
i
v
e

G
a
i
n
20
15
10
5
0
-30 -5 -10 -15 -25 0 -20 +5
5kHz sinewave input
Gain scaling:
g=2.5
g=3.0
A/D
DSP
Loop Voltages
L
o
o
p

P
e
a
k

V
o
l
t
a
g
e
s

[
V
]
-30 -5 -10 -15 -25 0 -20 +5
VLSI-compatible voltages!
1
2
3
4
5
C
4
2
0
-2
-4
EECS 247 Lecture 21: Oversampled ADC Implementation 2002 B. Boser 1
A/D
DSP
Tones
5
th
order modulator
DC inputs
Tones
Dither
kT/C noise
A/D
DSP
5
th
Order Modulator
7
Q
6
I_5
5
I_4
4
I_3
3
I_2
2
I_1
1
Y
b2
b2
b1
b1
a5
a5
a4
a4
a3
a3
a2
a2
a1
a1
k5z
-1
1-z
-1
I5
k4z
-1
1-z
-1
I4
k3z
-1
1-z
-1
I3
k2z
-1
1-z
-1
I2
k1z
-1
1-z
-1
I1
Comparator
1
X
see L20_L5_sim.mdl and L20_L5.m
+1 / -1
Stable input range ~ -0.3 +0.3
1/10 1 1/4 1/4 1/8
1/512 1/16-1/64
1 1/2 1/2 1/4 1/4
A/D
DSP
5
th
Order Noise Shaping
Input: 0.1V, sinusoid
2
15
point DFT
30 averages
0 5 10 15
x 10
5
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]

/

I
n
t
.

N
o
i
s
e

[
d
B
V
]
Output Spectrum
Integrated Noise (30 averages)
Tones at f
s
/2-Nf
in
exceed input
A/D
DSP
In-Band Noise
0 1 2 3 4 5
x 10
4
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]

/

I
n
t
.

N
o
i
s
e

[
d
B
V
]
Output Spectrum
In-Band quantization noise:
120dB !
A/D
DSP
5
th
Order Noise Shaping
Input: 0.1V, sinusoid
2
15
point DFT
30 averages
0 5 10 15
x 10
5
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]

/

I
n
t
.

N
o
i
s
e

[
d
B
V
]
Output Spectrum
150dB stopband attenuation needed
to attenuate unwanted f
s
/2-Nf
in
components
down to the in-band quantization noise level
A/D
DSP
Out-of-Band vs In-Band Signals
A digital (low-pass) filter with suitable coefficient precision can
eliminate out-of-band quantization noise
No filter can attenuate unwanted in-band components without
attenuating the signal
Well spend some time making sure the components at f
s
/2-Nf
in
will not mix down to the signal band
But first, lets look at the modulator response to small DC inputs
(or offset)
A/D
DSP
Tones
2mV DC input
(1V full-scale)
Simulation technique:
A random 1
st
input
randomizes the noise
and enables
averaging. Without the
small tones are not
visible.
0 1 2 3 4 5
x 10
4
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]

/

I
n
t
.

N
o
i
s
e

[
d
B
V
]
Output Spectrum
6kHz
12kHz
A/D
DSP
Limit Cycles
Representing a DC term with a 1/+1 pattern e.g.
Spectrum
+ + + + + +
4 4 4 4 4 4 4 4 4 3 4 4 4 4 4 4 4 4 4 2 1
4 4 4 4 4 4 4 4 3 4 4 4 4 4 4 4 4 2 1
3 2 1 3 2 1 3 2 1 3 2 1 3 2 1
11
1
0
5 4 3 2 1
1 1 1 1 1 1 1 1 1 1 1
11
1
K
11
3
11
2
11
s s s
f f f
A/D
DSP
Limit Cycles
Fundamental
Tone velocity
kHz 6
1V
2mV
MHz 3
=
=
=
DAC
DC
s
V
V
f f
kHz/V 3 =
=
DAC
s
DC
V
f
dV
df

A/D
DSP
Tones
1.47 1.475 1.48 1.485 1.49 1.495 1.5
x 10
6
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]

/

I
n
t
.

N
o
i
s
e

[
d
B
V
]
Output Spectrum
6kHz
A/D
DSP
Tones
Tones follow the noise shape
The fundamental of a tone that falls into a
quantization noise null disappears
mV 5 . 3
MHz 3
kHz 5 . 10
V 1
=
=
=
s
FB DC
f
f
V V

A/D
DSP
Tones
0 1 2 3 4 5
x 10
4
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]

/

I
n
t
.

N
o
i
s
e

[
d
B
V
]
Output Spectrum
3.5mV DC input
A/D
DSP
Tones
In-band tones look like signals
Can be a big problems in some applications
E.g. audio even tones with power below the quantization noise
floor can be audible
Tones near f
s
/2 can be aliased down into the signal band
Since they are often strong, even a small alias can be a big
problem
We will look at mechanisms that alias tones in the next lecture
First lets look at dither as a means to reduce or eliminate in-
band tones
A/D
DSP
Dither
DC inputs can of course be represented by many
possible bit patterns
Including some that are random but still average to
the DC input
The spectrum of such a sequence has no tones
How can we get a SD modulator to produce such
randomized sequences?
A/D
DSP
Dither
The target DR for our audio SD is 16 Bits, or 98dB
Lets choose the sampling capacitor such that it limits
the dynamic range:
( )
( )
( )
V 9 pF 5 . 50
V 1
10
2
2
2
1
8 . 9
2
2
1
2
2
1
= = = =
=
=
C
T k
v
T k
V
T k
DR C
C
T k
V
DR
B
n
B
FS
B
B
FS
A/D
DSP
Dither
0 1 2 3 4 5
x 10
4
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]
No dither
With dither
2mV DC input
A/D
DSP
Dither
1.47 1.475 1.48 1.485 1.49 1.495 1.5
x 10
6
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]
No dither
With dither
Dither at an amplitude
which buries the in-
band tones has
virtually no effect on
tones near f
s
/2
A/D
DSP
kT/C Noise
So far weve looked at noise added to the
input of the SD modulator, which is also the
input of the first integrator
Now lets add noise also to the input of the
second integrator
Lets assume a 4pF sampling capacitor
This gives 1.4 x 32V rms noise
(two uncorrelated 32V samples per clock)
A/D
DSP
kT/C Noise
2mV DC input
Noise from 2
nd
integrator
smaller than 1
st
integrator noise
shaped
Why?
0 1 2 3 4 5
x 10
4
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]

/

I
n
t
.

N
o
i
s
e

[
d
B
V
]
No noise
1st Integrator
2nd Integrator
A/D
DSP
kT/C Noise
Noise from 1
st
integrator is added directly to the input
Noise from 2
nd
integrator is first-order noise shaped
Noise from subsequent integrators is attenuated even further
Especially for high oversampling ratios, only the first 1 or 2 integrators
add significant thermal noise. This is true also for other imperfections.
7
Q
6
I_5
5
I_4
4
I_3
3
I_2
2
I _1
1
Y
b2
b2
b1
b1
a5
a5
a4
a4
a3
a3
a2
a2
a1
a1
k5z-1
1-z-1
I5
k4z -1
1-z -1
I4
k3z-1
1-z-1
I3
k2z-1
1-z-1
I2
k1z-1
1-z-1
I1
Comparator
2
vn2
1
X
A/D
DSP
Dither
No practical amount of
dither eliminates the
tones near f
s
/2
1.47 1.475 1.48 1.485 1.49 1.495 1.5
x 10
6
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]

/

I
n
t
.

N
o
i
s
e

[
d
B
V
]
No noise
1st Integrator
2nd Integrator
A/D
DSP
Full-Scale Inputs
With practical levels of thermal noise added, lets try
a 5kHz sinusoidal input near full-scale (0.3V)
No distortion is visible in the spectrum
1-Bit modulators are intrinsically linear
But tones exist at high frequencies
to the oversampled modulator, a sinusoidal
input looks like two slowlyalternating DCs
hence giving rise to limit cycles
A/D
DSP
Full-Scale Inputs
0 1 2 3 4 5
x 10
4
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]
Output Spectrum
A/D
DSP
Full-Scale Inputs
0 5 10 15
x 10
5
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]
Output Spectrum
A/D
DSP
V
ref
Interference
Dither successfully removes in-band tones that would corrupt
the signal
The high-frequency tones in the quantization noise spectrum will
be removed by the digital filter following the modulator
What if some of these strong tones are demodulated to the
base-band before digital filtering?
Why would this happen?
A/D
DSP
AM Modulation
x
2
(t)
x
1
(t) y(t)
( ) ( )
( ) ( )
( ) ( ) ( ) ( ) [ ] t t t t
X X
t x t x
t X t x
t X t x
2 1 2 1
2 1
2 1
2 2 2
1 1 1
cos cos
2
cos
cos

+ + =
=
=
A/D
DSP
AM Modulation in DAC
DAC y(t)
v(t)
V
ref
( )
( ) ( )
/2 f at spectrum of 0.05%
l fundamenta
wave square /2 f mV 1 V 1
1
s
s
+
= =
+ =
= =
ref
ref
out
V t y t v
V
D t y
A/D
DSP
AM Modulation in DAC
0
f
s
/2
f
s
D
OUT
spectrum
V
ref
spectrum
interferer
convolution yields sum of red and green,
mirrored tones and noise appear in band
A/D
DSP
V
ref
Interference
0 1 2 3 4 5
x 10
4
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]0V
1e-006V
0.001V
60dB (1 dB/dB)
A/D
DSP
V
ref
Interference
Simulation are for specified amounts of f
s
/2 interference in the
DAC reference
As predicted interference demodulates the high-frequency tones
Since the high frequency tones are strong, a small amount
(1V) of interference suffices to create huge base-band tones
Stronger interference (1mV) rises the noise floor also
Amplitude of demodulated tones is proportional to interference
A/D
DSP
V
ref
Interference
Symmetry of the spectra at f
s
/2 and DC confirm that this is AM modulation
1.47 1.48 1.49 1.5
x 10
6
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]
0V
1e-006V
0.001V
0 1 2 3 4 5
x 10
4
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]0V
1e-006V
0.001V
A/D
DSP
V
ref
Tone Velocity
0 1 2 3 4 5
x 10
4
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]0.006V
0.012V
0.5kHz/mV
V
in
= 6mV / 12mV DC
V
ref
= 1V DC
+ 1mV f
s
/2 square wave
A/D
DSP
V
ref
Tone Velocity
The velocity of AM demodulated tones is half that of
the native tone
Such differences help debugging of real silicon
How clean does the reference have to be?
A/D
DSP
V
ref
Interference
0 1 2 3 4 5
x 10
4
-150
-100
-50
0
50
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
W
N
]

/

I
n
t
.

N
o
i
s
e

[
d
B
V
]
Output Spectrum
Tone dominates noise floor
w/o thermal noise
A/D
DSP
V
ref
Interference
120dB of clock-to-V
ref
isolation is not sufficient for digital audio
applications
Achieving this level of performance requires careful engineering
Getting an accurate requirement is the first (and an essential) step
See
E. Swanson, N. Sooch, and D. Knapp, Method for
Reducing Effects of Electrical Noise in Analog-to-Digital
Converter, U.S. Patent 4746899, 1988
for more ideas
A/D
DSP
Summary
Our stage 2 model can drive almost all capacitor sizing
decisions
Gain scaling
kT/C noise
Dither
Dither removes effectively in-band tones
Actual tonality determined by demodulation of limit cycles near f
s
/2
Next we will add relevant component imperfections, e.g.
Real capacitors arent perfect
Real opamps arent ideal
Well model nonlinearities in the system next time
EECS 247 Lecture 22: Sigma-Delta Nonlinearities 2002 B. Boser 1
A/D
DSP
Modeling Nonlinearities
Many component nonlinearities contribute negligible
errors
Dont waste CPU cycles modeling the voltage coefficient of
every capacitor in the loop
Unnecessarily complex models reduce the chance to find
relevant problems, and, perhaps, solutions
As with all nonidealities, model one at a time
Expect errors from the 2
nd
integrator to be reduced by
the gain of the 1
st
integrator
Errors further downstream are even less significant
A/D
DSP
Capacitor Voltage Coefficient
Ideal capacitor
Practical capacitor (1
st
order model)
Typical voltage coefficients
Poly-poly capacitors 10 ppm/V
Metal-metal capacitors 1 10 ppm/V
( )
( )V V C V Q
V V C Q
o
K + + =
=
1 ) (
h wit
CV Q =
A/D
DSP
Integrator 1
1D
C
IN

2
v
1OUT
C
FB
v
IN
2
v
CM
2
v
CM
1
C
R1

2
D
V
REF
2
v
CM
1
C
R2
V
REF
v
CM
2
D
v
1N
C
IN
s voltco causes initial
charge to vary nonlinearly
with v
IN
harmonic
distortion
A/D
DSP
Integrator 1
1D
C
IN

2
v
1OUT
C
FB
v
IN
2
v
CM
2
v
CM
1
C
R1

2
D
V
REF
2
v
CM
1
C
R2
V
REF
v
CM
2
D
v
1N
The voltage coefficients of
C
R1
and C
R2
only generates a
(small) offset negligible
A/D
DSP
Integrator 1
1D
C
IN

2
v
1OUT
C
FB
v
IN
2
v
CM
2
v
CM
1
C
R1

2
D
V
REF
2
v
CM
1
C
R2
V
REF
v
CM
2
D
v
1N
The effect of C
FB
s voltco is
non-obvious, so well have to
analyze it
A/D
DSP
C
IN
Voltage Coefficient
From charge conservation (V
CM
=0, C
R1
=C
R2
=C
R
):
( ) ( )
( ) ( )
4 43 4 42 1
4 4 4 4 4 4 3 4 4 4 4 4 4 2 1
43 42 1
feedback bit - 1
input converter
2
n integratio
1 1
1 1
1
REF
FB
R
FB
IN
IN
FB
IN
OUT OUT
V
C
C
D
k V
C
C
k V
C
C
k V k V
IN
+ +
=

A/D
DSP
C
IN
Voltage Coefficient
0 1 2 3 4 5
x 10
4
-200
-150
-100
-50
0
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
F
S
]

/

I
n
t
.

N
o
i
s
e

[
d
B
V
]
Frequency [Hz]
Output Spectrum
Integrated Noise
V
in
=V
FS
=1V
Spectrum scaled for V
FS
0dB
(window lowers peak)
Noise integral excludes
DC, fundamental
=10 ppm/V
2
nd
harmonic at 103dB
dominates noise!
Lets characterize it
A/D
DSP
C
IN
Voltage Coefficient
2
nd
harmonic increases
1dB per 1dB increase of
0 1 2 3 4 5
x 10
4
-200
-150
-100
-50
0
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
F
S
]
=10 ppm/V
=1 ppm/V
20dB
A/D
DSP
C
IN
Voltage Coefficient
2
nd
harmonic increases
2dB per 1dB increase of
the input signal amplitude
0 1 2 3 4 5
x 10
4
-200
-150
-100
-50
0
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
F
S
]
A = 1V
A = 0.1V
20dB
40dB
A/D
DSP
C
FB
Voltage Coefficient
Lets look next at the voltage coefficient of the feedback capacitor in the
1
st
integrator
We turn off all other nonidealities C
IN
voltage coefficients, noise, etc.
Makes it easier to find the effect of C
FB
on the modulator
Downside: we miss potential interactions between nonidealities
Often they are negligible: nonidealities (like voltage coefficients) produce
small errors linear superposition applies
Of course its a good idea to run a complete verification at the end
And well get to diagnose the real thing soon enough without the insight
gained from such idealized simulations its next to impossible to diagnose a
complex chip
Evaluating the effect of the C
FB
voltage coefficient requires solving a
quadratic equation, see next slide
A/D
DSP
C
FB
Voltage Coefficient
( )
2
4
1 1
1
1 1
1
FB
FB
OUT FB
FB
OUT
C
Q
V C
Q
V
+ +
=
=
( ) ( )
) integrator linear from output as (same
1
REF R IN IN FB FB
V DC V C k Q k Q + + =
A/D
DSP
C
FB
Voltage Coefficient
7
Q
6
I_5
5
I_4
4
I_3
3
I_2
2
I_1
1
Y
3
g
1/16-1/64
b2
1/512
b1
0.25
a5
0.25
a4
0.5
a3
0.5
a2
1
a1
(sqrt(1 + 4*alpha*u(1)) - 1) / 2 / alpha
Nonlinear CFB
0.125z -1
1-z -1
I5
00.25
1-z -1
I4
0.25z -1
1-z-1
I3
z-1
1-z-1
I2
0.1z -1
1-z -1
I1
Comparator
1
X
Q
FB
(linear)
V
FB
A/D
DSP
C
FB
Voltage Coefficient
Effect less pronounced than
for C
IN
Noise remains zero at DC
First order noise for large
Nonlinearities operating on
shaped noise change the
shape of the noise
No linear model can
predict this
No harmonics why?
0 1 2 3 4 5
x 10
4
-200
-150
-100
-50
0
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
F
S
]
FB1
= 10 ppm/V
FB1
= 1000 ppm/V
A/D
DSP
1
st
Integrator Output
The input signal appears
much attenuated at the
output of the 1
st
Integrator
(by its gain)
This signal appears across
C
FB
and since it contains
no strong tones it produces
no harmonics
Or does it?
0 1 2 3 4 5
x 10
4
-200
-150
-100
-50
0
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
F
S
]
Modulator Output
Output of 1st Integrator
A/D
DSP
DC Input
For =1000 ppm/V, tones
produced by C
FB
are much
larger than native tones, but
move with the same
velocity as native tones
(1kHz/mV)
Where are these tones
coming from?
0 1 2 3 4 5
x 10
4
-200
-150
-100
-50
0
Frequency [Hz]
O
u
t
p
u
t

S
p
e
c
t
r
u
m

[
d
B
F
S
]
5mV DC
8mV DC
A/D
DSP
C
FB
Voltage Coefficient
Tones appear near f
s
/2,
as expected
Apparently these are
folded to the base-
band
How?
=10 ppm/V
1.45 1.46 1.47 1.48 1.49 1.5
x 10
6
-200
-100
0
O
u
t
p
u
t

[
d
B
F
S
]
0 1 2 3 4 5
x 10
4
-200
-100
0
O
u
t
p
u
t

[
d
B
F
S
]
Frequency [Hz]
140dB linearity requirement
A/D
DSP
Quantization Noise Nonlinearity
Native tones at a frequency f
D
close to fs/2 have
much higher power than in-band tones
When this tone passes a nonlinearity in the
modulator loop filter, it produces distortion
2 2

f f
f
s
D
=
( ) ( ) [ ] t f t f
D D
2 2 cos
2
1
2
1
2 sin
2
=
A/D
DSP
Quantization Noise Nonlinearity
( ) ( ) [ ] t f t f
D D
2 2 cos
2
1
2
1
2 sin
2
=
In the sampled data system,
maps to f
Small nonlinearities applied to aggressively shaped

quantization noise can produce big tone problems
f f f
s D
= 2
A/D
DSP
Out-of-Band Tones
In principle, the digital filter removes out-of-band tones
Except their distortion components, caused by nonlinearities in the
modulator loop filter
Except components that are mixed down to DC due to noise in the
DAC reference
The C
FB1
voltage coefficient adds only a small nonlinearity to the
quantization noise path
Fortunately this nonlinearity is applied to the integral of the
quantization noise and sees only a small signal component
Nonlinearities in the amplifier are much more serious
Including those in the model is left as an exercise
Maintaining extremely high levels of linearity in H(z) is the
biggest transistor-level design challenge of modulators
EECS 247 Lecture 23: Decimation Filters 2002 B. Boser 1
A/D
DSP
Todays Lecture
Decimation filters for ADCs
Digital decimation filters
Aliasing in the analog domain
Aliasing in the digital domain
Coefficient precision and gain scaling
Digital arithmetic throughput calculations
One-stage decimation
Linear phase implications
A/D
DSP
Analog-to-Digital Converters
A Analog-to-Digital Converter ( ADC)
combines
An analog modulator which produces an
oversampled output stream of 1-bit digital samples
A digital decimation filter which takes the 1-bit
modulator output as its input and
Filters out out-of-band quantization noise
Filters out unwanted out-of-band signals present in the
modulators analog input
Lowers the sampling frequency to a value closer to 2X
the highest frequency of interest
A/D
DSP
ADCs
Commercial DSPs arent designed to handle 1-bit
input samples at oversampled data rates
A 400Mip DSP only executes 133 instructions per 3MHz
sample
In 2001, the 32X32b multiply-accumulate cost is 5/Mip,
independent of the number of active bits/word (ref. 1)
DSPs are designed to handle 16+bit wide data
words at Nyquist-like sampling frequencies
decimation filters bridge the speed/resolution gap
A/D
DSP
Aliasing in the Analog Domain
Well continue using the 3MHz, 1-bit modulator
and its audio application as the basis for decimation
filter analysis
Sampling action at the modulator input inherently
results in aliasing
2980 and 3020kHz alias to 20kHz
2999 and 3001kHz alias to 1kHz
No digital filter can separate frequency components
that have aliased on top of one another
A/D
DSP
1
st
-order RC filters usually provide adequate
antialiasing protection for ADCs
A 30kHz LPF provides only 40dB of attenuation at 3MHz,
But microphones and other audio transducers produce
negligible outputs at 3MHz
Transducer loss is an important factor in all real-
world antialiasing filter specifications
Talk to veterans about the level of transducer loss you can
count on in your application
Or measure it
A/D
DSP
Protecting high-order modulators from instability-
provoking square wave inputs provides additional
justification for an RC antialiasing filter
Remember that any RC antialiasing filter adds kT/C
noise
Almost all of this noise is in the band of interest
Lets review a 600, 10nF LPF
A/D
DSP
kT/C Noise
kT/C noise of a 10nF
capacitor is 0.64Vrms
ADC noise from 0-
20kHz is 6.68Vrms
Sum of squares
addition yields
6.71Vrms
600
10nF
v
IN
ADC
A/D
DSP
Aliasing in the Digital Domain
The digital filters well develop for audio applications
will lower the sampling frequency from 3MHz to
46.875kHz
Thats called decimating by 64 or 64X decimation
Aliasing can occur in the digital domain whenever
sampling frequencies decrease
Digital filters which precede the decimation step attenuate
signals and noise which would otherwise alias into the
0-20kHz band
A/D
DSP
Aliasing in the Digital Domain
Stopband attenuation specifications for decimation
filters are based on the need to attenuate tones
near f
S
/2 down to levels 30dB below the 0-20kHz
integrated noise
Lets plot on the same dBFS scale:
A full scale 1Vrms, 5kHz input with modulator thermal noise
added (plotted from 0-50kHz)
Tones for a 5mV dc input (plotted from 1450-1500kHz)
A/D
DSP
Stopband Attenuation Analysis
[kHz]
0
-40
-120
-160
40
-80
0 40 30 20 10 50
integrated tone bins
0-20kHz integrated noise30dB
A
m
p
l
i
t
u
d
e

/
I
n
t
e
g
r
a
t
e
d

N
o
i
s
e

[
d
B
F
S
]
1450 1490 1480 1470 1460 1500
135dB
A/D
DSP
Stopband Attenuation Analysis
135dB of stopband attenuation is required for aliased
tone suppression
24b FIR filter coefficients are a likely choice given the
6dB/bit estimate (see lectures on digital filters)
135dB of stopband attenuation results in negligible
aliased non-tonal quantization noise
Where should the stopband begin?
Given our decimation filter output word rate of 46.875kHz,
23kHz seems a safe choice
A/D
DSP
Decimation Filter Synthesis
Well call our ideal decimation filter Filter #1
0.000.01dB gain from 0-20kHz
135dB stopband attenuation from 23-2977kHz
Linear phase
The target magnitude response appears on the
following slide
Dont try this with an analog filter!
A/D
DSP
Filter #1 Target Response
[kHz]
D
e
c
i
m
a
t
i
o
n

F
i
l
t
e
r

G
a
i
n

(
d
B
)
0
-40
-120
-160
40
-80
0 40 30 20 10 50
5mV dc input
noise shape
A/D
DSP
Decimation Filter Synthesis
Well use MATLABs implementation of the
Parks-McClellan algorithm to synthesize this
filter (remez)
After crunching for a while, MATLAB returns a
5612 tap FIR filter with the following
response
A/D
DSP
Filter #1 Actual Response
D
e
c
i
m
a
t
i
o
n

F
i
l
t
e
r

G
a
i
n

(
d
B
)
0
-40
-120
-160
40
-80
0 40 30 20 10 50
5612 taps!
Is this practical?
[kHz]
A/D
DSP
Filter #1
A classical 5612-tap, f
S
=3MHz FIR filter would require
a 5612*3MHz=16.8GHz multiply-accumulate rate
However, in a decimation filter application, we never
waste power to compute filter output samples that we
immediately decimate away
The required multiply-accumulate rate is reduced by
the decimation ratio to 263MHz
A/D
DSP
Filter #1
The second key factor that makes this FIR filter
unusual is that it needs no hardware multiplier at all
Input data is only 1-bit wide
The multiplier merely adds or subtracts coefficients from
the accumulator
263MHz begins to seem reasonable, but we can use
another simple trick to reduce power further
A/D
DSP
Linear phase filter coefficients are symmetric around
the middle of the impulse response
Wed never waste ROM to store all 5612 coefficients
when only 2806 are unique
A 5612x1b data memory allows us to exploit
coefficient symmetry to reduce multiply-accumulate
rates by another 2X
A/D
DSP
Our 5612 coefficients look like this:
A/D
DSP
Each time we fetch a coefficient from ROM, we fetch both1-bit
samples that need it from the 5612x1b data memory:
+1
or
-1
+1
or
-1
data memory contents
shown in red
A/D
DSP
We only have two data states, +1 and 1
If we add the data before multiplying, only 3 results
are possible:
+2 if both 1b samples are +1
-2 if both 1b samples are 1
0 if 1b samples are 1,+1 or +1,-1
Our multiplier adds, subtracts, or does nothing
Multiply-accumulate in this application requires only
an accumulator operating at 132MHz!
A/D
DSP
Filter #2
While the throughput requirements of Filter #1 are not
outrageous, audio applications economize further
Modulator input signals that alias into frequencies
above 20kHz are inaudible
Most people cant hear 20kHz full-scale sinewaves
Who would ever record that anyway?
So, unless youre interested in marketing your audio
ADC to dogs (dogs can hear up to 30kHz, supposedly),
consider Filter #2
A/D
DSP
Filter #2 Target Response
[Hz]
D
e
c
i
m
a
t
i
o
n

F
i
l
t
e
r

G
a
i
n

(
d
B
)
0
-40
-120
-160
40
-80
0 40 30 20 10 50
Filter #1
Filter #2
0-20kHz passband ripple 0.01dB for both filters
A/D
DSP
Filter #2
With this filter specification, an input signal at 24kHz
will alias to 46.875-24kHz =22.875kHz without
anywhere near 135dB attenuation
Neither 24kHz nor 22.875kHz is audible
Exploiting the audibility of aliased components allows
us to widen the transition band
The most critical factor in determining filter order
Lets see what MATLAB cooks up
A/D
DSP
Filter #2 Actual Response
[kHz]
D
e
c
i
m
a
t
i
o
n

F
i
l
t
e
r

G
a
i
n

(
d
B
)
0
-40
-120
-160
40
-80
0 40 30 20 10 50
2406 taps
A/D
DSP
Filter #2
Using the same coefficient symmetry trick that helped
Filter #1, Filter #2s accumulate rate drops to
2406/5612*132MHz =57MHz
Performance compromises are inaudible
Most companies refuse to pay extra for aliasing
purity, if the extra costs of purity bring no perceptible
benefits
Thats just good engineering
A/D
DSP
FIR Arithmetic Throughput
Length-N FIR decimation filters which take input
samples at a sampling frequency f
SIN
and produce
output samples at a sampling frequency f
SOUT
,
f
SOUT
<f
SIN
, require multiply-accumulate rates of
Linear phase FIRs which exploit data addition before
multiplication reduce this to
f
MA
=
Nf
SOUT
f
MA
= Nf
SOUT
2
A/D
DSP
FIR Arithmetic Throughput
FIR filters with 1-bit input data dont need traditional
hardware multipliers
Use add/subtract/do nothing accumulators
How wide should these accumulators be?
What coefficient precision is needed?
What output resolution should we use?
Lets look at a Filter #2 implementation
A/D
DSP
FIR Implementation
Digital filters usually come with bit-width that are
multiples of 4
16-bits results in unwanted digital quantization noise
So lets try a 20-bit filter for our 16-bit ADC
2
20
=1048576
Each LSB is 1ppm of the ADC input range
Lets look at the mapping of our 1Vrms full scale
sinewave into digital output values
Before we set filter gain levels, we need to review modulator
outputs
A/D
DSP
Modulator Outputs
H(z)
+
_
v
IN
d
OUT
+1 or -1
g
D
OUT
(z)
V
IN
(z)

1
g
g=3
=
H
1+gH
1
3
=
A/D
DSP
Modulator Outputs
Positive and negative peaks of a 1Vrms full-scale
sinewave correspond to levels shown below:
H(z)
+
_
v
IN
d
OUT
+1 or -1
g
g=3
+1.414V
-1.414V
+0.4714V
-0.4714V
A/D
DSP
Decimation Filter Gain
Gain scaling in the decimation filter maps the
0.4714 modulator average output at signal peaks to
the 20-bit digital full-scale range of 2
19
Ideal decimation filter dc gain is 1112000=120.9dB
To allow for offsets, etc., well use a slightly smaller gain of
2
20
=120.4dB
An FIR filters dc gain equals the sum of its
coefficients
Lets adjust Filter #2s coefficients accordingly
A/D
DSP
Filter #2 Response
[kHz]
D
e
c
i
m
a
t
i
o
n

F
i
l
t
e
r

G
a
i
n

(
d
B
)
120
80
0
-40
160
40
0 40 30 20 10 50
multiplying all coefficients
by a constant doesnt change
response shape at all
A/D
DSP
Filter #2 Response
The gain adjustment is correct, but
coefficients are still floating point
Rounding these coefficients to the nearest
integer using MATLABs round() function
yields the following response
A/D
DSP
Filter #2 Responses
[kHz]
D
e
c
i
m
a
t
i
o
n

F
i
l
t
e
r

G
a
i
n

(
d
B
)
120
80
0
-40
160
40
0 40 30 20 10 50
integer coefficients
floating point
coefficients
A/D
DSP
Filter #2 Responses
The stopband attenuation is horrible, much less than the 135dB
requirement, and the problem is obviously coefficient precision
Check the integer coefficients
The biggest one is +15715
The smallest one is 3332
Thats only 14-15b of coefficient precision, and <90dB of worst-
case stopband attenuation
When 2406 coefficients sum to 2
20
, the biggest coefficient is
pretty small
A/D
DSP
Filter #2 Bit Map
Lets look at the digital scaling in our defective filter :
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 17 18 19
0
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1b data
rounded coef.
accumulator
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 17 18 19
ADC output
A/D
DSP
Filter #2 Bit Map
To add coefficient resolution, well add 8 coefficient bits
below the 2
0
point:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 17 18 19
0
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1b data
rounded coef.
accumulator
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 17 18 19
ADC output
-1 -2 -3 -4 -5 -7 -8 -6
-1 -2 -3 -4 -5 -7 -8 -6
round
A/D
DSP
Filter #2 Bit Map
Higher-precision coefficients are produced with a
simple coef=round(256*coef)/256 operation
The 23b fixed point coefficient magnitude response
appears on the following slide
Rounding of the 28b accumulator to produce the
20b ADC result adds 20b quantization noise
At -122dBFS, thats insignificant for a 103dB dynamic
range ADC
A/D
DSP
Filter #2 Responses
[kHz]
D
e
c
i
m
a
t
i
o
n

F
i
l
t
e
r

G
a
i
n

(
d
B
)
120
80
0
-40
160
40
0 40 30 20 10 50
floating point coefficients
23b coefficients
A/D
DSP
Intermediate Overload
With our properly scaled coefficients,
The sum of coefficients is 1.047e6
The sum of coefficient absolute values is 2.040e6
The accumulator can never reach a value outside the
(-2.041e6,+2.041e6) range
Two accumulator bits above the ADC output MSB provide
intermediate result overload protection
A 30b accumulator for a 20b ADC isnt unusual
A/D
DSP
Filter #2 Bit Map
The green accumulator bits (20 and 21) provide
complete overload protection:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 17 18 19
0
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1b data
rounded coef.
accumulator
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 17 18 19
ADC output
-1 -2 -3 -4 -5 -7 -8 -6
-1 -2 -3 -4 -5 -7 -8 -6
round
21 20
A/D
DSP
Intermediate Overload
Given the relatively low cost of this overload
protection, it hardly pays to evaluate whether or not
accumulator bit 21 can be reached by real-world ADC
input signals
Our first pass decimation filter design is complete
Well add this filter to our stage 2 modulator model next time
A/D
DSP
References
1. Texas Instruments, C2000 Series DSP datasheets, 2001.
2. R. E. Crochiere and L. R. Rabiner, Interpolation and
Decimation of Digital Signals A Tutorial Review, Proc.
IEEE, 69, pp. 300-331, March 1981.
3. Nav Sooch, Gain Scaling of Oversampled Analog-to-Digital
Converters, U.S. Patent 4851841, 1989.
EECS 247 Lecture 24: Multi-Rate Filters 2002 B. Boser 1
A/D
DSP
Todays Lecture
Modeling the ADC decimation filter
Decimated DFTs
Fixed and floating point comparisons
Troubleshooting and test modes
Multistage decimation filters
Parks-McClellan filters
Manual decimators
Hogenauer filters
Half-band filters
A/D
DSP
Filter #2 Responses
[kHz]
D
e
c
i
m
a
t
i
o
n

F
i
l
t
e
r

G
a
i
n

[
d
B
]
120
80
0
-40
160
40
0 40 30 20 10 50
floating point coefficients
23b coefficients
A/D
DSP
ADC Output DFT
[kHz]
A
m
p
l
i
t
u
d
e

o
r
I
n
t
e
g
r
a
t
e
d

N
o
i
s
e

[
d
B
F
S
]
0
-40
-120
-160
-80
0 20 15 10 5 25
5kHz, 1Vrms analog input
filter #2, 24b coefficients
f
SOUT
=46.875kHz
1000 point DFT
10 averages
A/D
DSP
ADC Output DFT
A
m
p
l
i
t
u
d
e
o
r
I
n
t
e
g
r
a
t
e
d

N
o
i
s
e

[
d
B
F
S
]
0
-40
-120
-160
-80
0 20 15 10 5 25 [kHz]
same as previous slide,
except floating point coefficients
Difference is negligible
start of decimation filter rolloff
A/D
DSP
Production Testing
Its obvious that decimation filters obscure many
details of modulator analog performance
Most of the shaped quantization noise is filtered
away
Was the modulator fabricated correctly? Are there
defects in a given chip?
At this stage, youve got to consider possible
production test modes
A/D
DSP
Test Modes
All ADC designs must provide at least the
following test modes:
Output unfiltered 1-bit modulator output samples
Insert test vectors at the decimation filter input
Any mixed-signal IC which includes any ADC must
provide for observability of unprocessed ADC output
samples
Think of it as fault coverage in the analog domain
Lets see how our decimation filter obscures a typical
modulator manufacturing defect
A/D
DSP
Test Modes
Suppose the modulator is built with an open fault in a
metal trace which connects up the switched capacitor
implementing the b
2
capacitor
b
2
sets one of the quantization noise zeroes
If the b
2
capacitor is missing, b
2
=0
In the real world, this defect will occur in 1-10ppm of
production units
The next two slides highlight the loop filter defect,
and show decimated DFTs with and without the
defect
A/D
DSP
Loop Filter Defect
_
k
1
1-z
-1
+ +
_
+
b
1
a
2
b
2
a
1
a
3
a
4
a
5
IN
(from
summer)
OUT (to comparator)
k
2
z
-1
1-z
-1
k
3
z
-1
1-z
-1
k
4
z
-1
1-z
-1
k
5
z
-1
1-z
-1
b
2
=0 defect
A/D
DSP
ADC Output DFT
A
m
p
l
i
t
u
d
e

(
d
B
F
S
)
0
-40
-120
-160
-80
0 20 15 10 5 25 [kHz]
f
SOUT
=46.875kHz
1000 point DFT
10 averages
b
2
nominal
b
2
=0 defect
A/D
DSP
Test Modes
The small increase in noise above 20kHz would
probably be missed in production test
Dynamic range is specified to include only noise from 0-
20kHz
Should we ship the defective unit?
Absolutely not
The metal shrapnel pattern associated with the defect is
unknown, and it may lead to a catastrophic failure later
(reliability problem)
Lets see if a 1-bit test mode can detect the fault
A/D
DSP
ADC 1-bit Test Mode
A
m
p
l
i
t
u
d
e

(
d
B
F
S
)
0
-40
-120
-160
-80
0 120 90 60 30 150 [kHz]
30000 point DFT
20 averages
b
2
nominal
b
2
=0 defect
10dB shift in noise is easy to detect
without averaging
A/D
DSP
ADC 1-bit Test Mode
A
m
p
l
i
t
u
d
e

(
d
B
F
S
)
0
-40
-120
-160
-80
0 120 90 60 30 150 [kHz]
30000 point DFT
20 averages
b
2
nominal
b
2
=0 defect
many other loop filter defects lead
to visible changes in the highest Q
pole in the noise shape
A/D
DSP
Test Modes
Models can analyze whether or not a specific defect
is observable with a given test mode
Many defect-observability analyses are required to improve
quality levels from 100ppm defective to <10ppm defective
These models improve over the production life of a
chip and from generation-to-generation
If big customers detect a quality defect, they demand
corrective action to improve tests so that units with the same
defect wont be shipped again
Without 1-bit test modes, youre sunk!
A/D
DSP
Multitone Tests
As long as were on the subject of testing,
lets examine a fast, effective method to look
at the frequency response of a filter or ADC
This method is used extensively in production
tests of both analog filters and ADCs
It is not a substitute for classic, fault coverage
testing of digital filters
A/D
DSP
Multitone Tests
IC testers can add sinewaves at many different
frequencies in the digital domain
The digital sum is sent to a test system DAC which
generates the analog input for a device under test
Frequency response at many different input frequencies can
be determined with one test
Lets see how our ADC responds to an input
which is a sum of 20, 21, 22, 23, 24.375, 25.375,
26.375, and 27.375kHz sinewaves
A/D
DSP
ADC Multitone DFT
A
m
p
l
i
t
u
d
e

(
d
B
F
S
)
0
-40
-120
-160
-80
0 20 15 10 5 25 [kHz]
Multitone analog input
filter #2, 24b coefficients
f
SOUT
=46.875kHz
1000 point DFT
10 averages
A/D
DSP
ADC Multitone DFT
A
m
p
l
i
t
u
d
e

(
d
B
F
S
)
0
-40
-120
-160
-80
15 23 21 19 17 25 [kHz]
20 21
22
23
aliased 26.375
aliased 25.375
aliased 24.375
27.375kHz alias
buried by noise!
A/D
DSP
Multitone Tests
Note how elegantly the multitone output
amplitudes trace the transition band of the
decimation filter
Total observation time (1000 ADC output
samples) must be long enough to resolve
each of the individual frequencies
Hz/bin is the reciprocal of the total observation
time
A/D
DSP
Multistage Decimation Filters
Decimation filter #2 can be realized with a accumulator rate of
57MHz, shift register, and coefficient ROM
Absolutely practical in todays CMOS processes
A multiplier is not needed
Multi-rate decimators can achieve the same result with even
lower processing cost
We will:
Illustrate how multistage decimation requires substantially lower
multiply-accumulate rates than single stage decimation
Introduce very specific filter architectures that are specialized just
for decimation/interpolation and can further reduce hardware
complexity
A/D
DSP
In multistage decimation, implement the
sharpest transition bands at the lowest
sampling frequency
For our 3MHz audio modulator, well
decimate by 64 in 3 stages
8X in the first stage
4X in the second stage
2X in the third stage
A/D
DSP
Datapath precision is important here
Stage 1 has 1-bit input data and doesnt need a hardware
multiplier
Intermediate rounding operations between stages 1 and 2
and between stages 2 and 3 add quantization noise which
must be modeled in a bit true fashion
Final rounding to the 20-bit ADC output adds negligible
noise
Coefficient precision is also important
24b precision for 135dB stopband attenuation
A/D
DSP
Parks-McClellan Decimation
In the first pass with synthesize the three
stages with the Parks-McClellan algorithm
and stick with floating point numbers
The results provide an estimate of aggregate
multiply accumulate rates
Each stage will specify 0.00000.0033dB
ripple from 0-20kHz
Passband ripple in the 3 stages may add
The goal is a faircomparison to filter #2
A/D
DSP
Stages 1 and 2 prevent decimation from aliasing noise
and tones into frequencies below 27kHz
Stage 1 stopbands:
37527kHz, 75027kHz, 112527kHz, 1473-1500kHz
Stage 2 stopbands:
93.7527kHz, 160.5-187.5kHz
Stage 3 stopband: 27-46.875kHz
For each stage we specify 135dB stopband attenuation
A/D
DSP
MATLABs Parks-McClellan front end doesnt
handle lowpass filters like stage 1 very easily
The low pass filter we want has a single
passband, multiple stopbands, and interspersed
dont care bands
Well waste zeroes and implement stages 1
and 2 as single-stopband LPFs:
Stage 1 stopband 348-1500kHz
Stage 2 stopband 66.75-187.5kHz
Stage 3 stopband still 27-46.875kHz
A/D
DSP
These Parks-McClellan designs yield:
Stage 1: Length 57 (21.375MHz)
Multiply-accumulate rates are shown in red
above
Total multiply-accumulate frequency is 30MHz
Exploiting linear phase coefficient symmetry can
reduce this to 15MHz
The filter #2 design required 57MHz
A/D
DSP
Stage 1 uses the most MAC cycles, but it doesnt
need a hardware multiplier
DSP conventional wisdom says you should always
decimate (or interpolate) in stages
ADC decimation filters with 1-bit inputs are hardly
conventional filters
Both single and multistage designs must be compared in
power and area
MACs required by unrelated DSP functions may have
free cycles available for decimation
A/D
DSP
Manual Decimators
Simple and effective first stage decimators spread
unit circle zeroes evenly in areas where aliasing must
be prevented
Start with about 5 zeroes per stopband
Add more if needed to reach 135dB in each band
Our manual decimator requires only Length=38 to
achieve specified performance
Zeroes at 350, 360, 370, 380, 390, 400, 726, 738, 750, 762,
764, 1101, 1113, 1125, 1137, 1149, 1476, 1488, and
1500kHz
A/D
DSP
Manual Decimator Response
G
a
i
n

(
d
B
)
0
-50
-150
-200
-100
0 1200 900 600 300 1500 [kHz]
12 zeroes
-148dB
10 zeroes
-136dB
10 zeroes
-152dB
5 zeroes
-152dB
A/D
DSP
Manual Decimators
This decimator uses no zeroes off the unit circle, so
its response droops (by 0.25dB) from dc to 20kHz
A Stage 3 Parks-McClellan filter can easily correct for this
droop with little or no increase in order
Manual zero placement reduces the Stage 1 MAC
rate to 14.25MHz, a 33% reduction vs. the first-pass
MATLAB solution (21.4MHz)
A/D
DSP
Clever Decimators
Two very clever decimation filter approaches
which are occasionally very useful are
Comb filters [1]
Implement (multiple) zeros on the unit circle very
efficiently
Half-band filters [2]
For very efficient 2X decimation/interpolation
A/D
DSP
Comb Filters
Lets look at the a rectangular transfer function,
This filter has N-1 evenly spaced zeros on the unit circle, except
at z=1 LPF
A N=8 rectangular window is the simplest filter candidate for a
decimate-by-8 stage 1 design
Of course, its performance is unimpressive relative to our
Length=38 manual decimator
At least the zeroes are in the right place
1
7 6 5 4 3 2 1
1
0
1
1
1
) (
=
+ + + + + + + + =
=
z
z
z z z z z z z
z z H
N
N
i
i
K
A/D
DSP
Comb Decimator
G
a
i
n

(
d
B
)
0
-50
-150
-200
-100
0 1200 900 600 300 1500 [kHz]
Length 8
Length 38
A/D
DSP
A single comb filter obviously will not meet the specification
but a cascade of K of them might
The resulting filter is not very good (significant in-band droop),
but a trick due to Hogenauer leads to an extraordinarily simple
implementation
Lets see how this looks in hardware
Comb Filters
[ ]
K
N
K
K
N
K
N
i
i
z
z
z
z
z z H
=

1
1
1
1
1
) (
1
1
1
0
A/D
DSP
Hogenauer Filter, K=5
1
1- z
-1
N
decimate
1
1- z
-1
1
1- z
-1
1
1- z
-1
1
1- z
-1
1- z
-1
1- z
-1
1- z
-1
1- z
-1
1- z
-1
The integrators operate at f
SIN
, the differentiators at f
SOUT
The decimate block throws away N-1 of every N integrator
output samples
z
-1
at f
SOUT
is equivalent to z
-N
at f
SIN
A/D
DSP
Hogenauer K=5 Cascade
G
a
i
n

(
d
B
)
0
-50
-150
-200
-100
0 1200 900 600 300 1500 [kHz]
Hogenauer 5-cascade
Manual decimator
A/D
DSP
Hogenauer Filters
The Hogenauer 5-cascade doesnt come close to
meeting our 135dB antialiasing specification near
375kHz
A higher value of K is needed (typically L+1 or more)
Hogenauer implementations arent without difficulty
The high-speed integrators integrate offsets to infinity and
must roll over gracefully
Word-width requirements grow through the cascade
Bit true simulations are a must
A/D
DSP
Half-band Filters
Half-band filters [2] are very specialized linear phase
low pass filters
Theyre useful only in decimate-by-2 (and interpolate-by-two)
stages
Theyre useful only when some aliasing can be tolerated (-
6dB gain at f
SOUT
/2)
Half the coefficients (almost) are zero
Zero coefficients require no MAC cycles!
Lets skip the derivation (see [2]) and look at an
example
A/D
DSP
Half-band Filters
The response of a half-band stage 3 filter F(z) is symmetric
(f
SIN
=93.75kHz):
If F(z)s gain is within 1 from 0-20kHz, its gain will be only from
26875-46875Hz
A good audio decimate-by-2 filter
The half-band filter inherently has 6dB gain at f
s
/4 =23437.5Hz
But how can we get the Park-McClellan algorithm to design a
half-band filter? The answer is in ref [2].
Lets look at the response
A/D
DSP
Half-band vs. PM Responses
G
a
i
n

(
d
B
)
0
-50
-150
-200
-100
0 40 30 20 10 50 [kHz]
Length=84 PM LPF
Half-band filter
(59 nonzero coefficients)
The half-band filter uses
30% fewer MAC cycles
and is at least as good!
A/D
DSP
References
[1] Eugene Hogenauer, An Economical Class of Digital Filters for
Decimation and Interpolation, IEEE Trans. Acoustics, Speech, and
Signal Processing, ASSP-29,April 1981.
[2] P. Vaidyanathn and T. Q. Nguyen, A Trick for the Design of FIR
Half-band Filters, IEEE Trans. Circuits Sys., CAS-34, pp. 297-300,
March 1987.
EECS 247 Lecture 25: Digital Data Receivers 2002 B. Boser 1
A/D
DSP
Data Receivers
Digital data receivers
Equalization
Data detection
Timing recovery
NRZ data spectra
Eye diagrams
Transmission line response
Think of it as another example for a 247 project
A/D
DSP
Digital Data Receivers
Way back in Lecture 1, we
looked briefly at the digital
communication problem
Everyone wants to send
bits as far as they can, as
fast as they can, through
the cheapest possible
media, until recovery of
those bits is a complex
signal processing problem
Cheap, noisy
Channel
Data
Transmitter
Clock
Input
Data
Input
Clock
Output
Data
Output
Data
Receiver
A/D
DSP
Also, since nobody wants
to invest in a separate
channel to send a clock
alongside the data, timing
recovery is a second key
responsibility of digital
data receivers
Today, data detection /
timing recovery is the
biggest mixed-signal
processing market there is
Cheap, noisy
Channel
Data
Transmitter
Clock
Input
Data
Input
Clock
Output
Data
Output
Data
Receiver
A/D
DSP
Well examine digital communications using
high-speed digital video over coaxial cable as
our underlying example
300Mb/s over distances of 200m
It illustrates many key principles of data detection
and timing recovery [2, 3]
A/D
DSP
NRZ Data Spectrum
NRZ (Non Return to Zero) data is a
complicated-sounding name for a very simple
two-level transmission scheme
The data transmitter produces two output levels,
and holds the appropriate binary level for a full bit
period
Well assume the two levels are +1 and 1
Whats the spectrum of random NRZ data?
A/D
DSP
Ideal NRZ Data Spectrum
We looked at random 1b sequences in
Lecture 15 (slides 15.4-15.5)
Random sequences yield white noise
An ideal NRZ data transmitter convolves (in
time) digital data impulses with a zero-order
hold function (slides 12.11-12.12)
The resulting spectrum is the product of the digital
datas white spectrum and the zero-order holds
sinx/x response:
H(f) = Te
-jfT
sin(fT)
fT
A/D
DSP
A
m
[
d
B
W
N
]
0
-30
-60
-90
0 400 300 200 100 500
30
A/D
DSP
Communication channels are not sampled
data systems
The digital data is passed through a ZOH
Lets look at 300Mb/s NRZ data
Expect nulls at multiples of 300MHz (from sinc)
A/D
DSP
A
m
p
l
i
t
u
d
e

(
d
B
W
N
)
40
-40
-20
0
20
10
7
10
8
10
10
10
9
10
11
[Hz]
zeroes at
m*300MHz
Log frequency scale!
A/D
DSP
A
m
p
l
i
t
u
d
e

(
d
B
W
N
)
40
-40
-20
0
20
10
7
10
8
10
10
10
9
10
11
[Hz]
-20dB/decade
slope
H(f) = Te
-jfT
sin(fT)
f T
A/D
DSP
Averaging can provide a better
indication of long term bin amplitudes
30 averages here produce a DFT plot
based on 900 unique transmitted bits
Results conform much more closely to the
sinx/x response
Well return to our more customary
linear frequency scale for DFT plots at
1GHz and below
A/D
DSP
A
m
p
l
i
t
u
d
e

(
d
B
W
N
)
40
-40
-20
0
20
0 250 750 500 1000 [MHz]
300Mb/s NRZ data
30000 point, 300GHz DFT
30 averages
A/D
DSP
Non-Zero Transition Times
The zero-order hold NRZ spectrum assumes
zero transition times between binary levels
All real-world NRZ data drivers take some
time to switch from one level to the other
How does this change the ideal NRZ data
spectrum?
A/D
DSP
Well shape the edge rate of the ideal NRZ signal via a
low pass filter
The low pass filter well use is a Gaussian LPF,
commonly used in digital signal analysis applications [4]
A Gaussian filters magnitude response is given by:
( )
56 . 2

2
2
2 s rise
f
f t
e f H =


A/D
DSP
Lets check the effect of a Gaussian Filter
Set the 10% to 90% rise times (and fall times) of
the NRZ signal to 100psec
100psec transitions times are still very fast relative
to our 3.3nsec data period
The filtered NRZ data spectrum appears in
redon the following slide
A/D
DSP
Ideal vs. Filtered Data Spectra
A
m
p
l
i
t
u
d
e

(
d
B
W
N
)
40
-40
-20
0
20
10
7
10
8
10
10
10
9
10
11
[Hz]
300Mb/s NRZ data
30000 point, 300GHz DFT
30 averages
0 risetime
100psec risetime
A/D
DSP
The frequency at which the ideal and filtered NRZ
spectra begin to diverge (by 6.8dB, in fact) is called
the knee frequency, f
knee
Knee frequencies depend only on transition times, not NRZ
data rates
Theres not enough energy above f
knee
to have much effect
on even the simplest data receiver (a CMOS inverter)
For digital signals with 10/90 transition times:
rise
knee
t
f
2
1
=
A/D
DSP
A
m
p
l
i
t
u
d
e

(
d
B
W
N
)
40
-40
-20
0
20
10
7
10
8
10
10
10
9
10
11
[Hz]
t
R
=100psec
f
knee
=5GHz
0 risetime
100psec risetime
A/D
DSP
NRZ Data in the Time-Domain
20 nsec/div
0
.
8

V
/
d
i
v
t
R
=100psec
A/D
DSP
Isolated +1 Data Bit
1 nsec/div
0
.
8

V
/
d
i
v
t
R
=100psec
A/D
DSP
Filtered NRZ Data
In high-speed communications applications,
the transition times are usually comparable to
the bit period
Then, filtered outputs reach the full +1 and 1
levels only if 2 consecutive data bits are identical
Isolated +1 and 1 pulses yield smaller swings
Lets see what happens when t
R
=3nsec
f
knee
=167MHz
A/D
DSP
30 Bit Periods
20 nsec/div
0
.
8

V
/
d
i
v
t
R
=3nsec
A/D
DSP
Eye Diagrams
Random NRZ data patterns are difficult to study in
the time domain
Every data set is different
Finding isolated pulses is a pain
In 1962, J ohn Mayo at Bell Laboratories found a
better way [5]
Scope traces are launched using the transmit clock as an
external trigger
The resulting oscillogramoverlays every data-pattern-
dependent variation of the filtered NRZ spectrum
For obvious reasons, these are called eye diagrams
A/D
DSP
300Mb/s Eye Diagram
2 nsec/div
0
.
8

V
/
d
i
v
t
R
=3nsec
A/D
DSP
300Mb/s Eye Diagram
2 nsec/div
0
.
8

V
/
d
i
v
t
R
=100psec
A/D
DSP
Eye Diagrams
Eye opening is an important indicator of the health of
a NRZ channel
Eyes close completely if the channel bandwidth is insufficient
to support the NRZ data rate
An eye diagram for t
R
=10nsec appears on the next slide
Closed eyes dont mean that all hope for digital
communications is lost
The receiver can do some filtering prior to deciding what the
transmitted bit was
A high pass equalizer added to a data receiver can
compensate for a low pass channel
A/D
DSP
300Mb/s Eye Diagram
2 nsec/div
0
.
8

V
/
d
i
v
t
R
=10nsec
A/D
DSP
Transmission Lines
Now that we know something about the 300Mb/s
NRZ signal were sending into a coaxial transmission
line, its time to figure out what that signal will look
like coming out the other end of the line
Well summarize a few key characteristics of
transmission lines first
A/D
DSP
Transmission Lines
Transmission lines are
characterized by distributed
electrical parameters
specified on a per unit length
basis
R: series resistance per
meter (/m)
L: series inductance per
meter (H/m)
C: shunt capacitance per
meter (F/m)
G: shunt conductance per
meter (
-1
/m)
Rdx Ldx
Gdx Cdx
v
IN
v
OUT
length=dx
v
IN
v
OUT
A/D
DSP
Transmission Lines
At high frequencies, the characteristic impedance of
a transmission line is given by
Transmission lines should be terminated with their
characteristic impedance
Reflections caused by impedance mismatches are common
sources of bad lab data
Or non-working systems
Z
0
=
L
C
A/D
DSP
Transmission Lines
The Belden 8281 cable used in our example application is
specified with (ref. 7):
L=379nH/m
C=67.3pF/m
Z
0
=75.0
For lossless transmission lines (R=G=0), all frequency
components present in an input signal move down the cable at a
velocity given by:
v =
1
LC
2.0x10
8
m/s for 8281 cable
(2/3 the speed of light)
A/D
DSP
Transmission Lines
A bit that we transmit into the cable at t=0 will start to
come out of the end of a 200m cable 1sec later
2/3 speed-of-light delays range from zero (short links) to 300
bit periods (at 200m)
The linear phase (fixed time delay) component of cable
response doesnt distort pulse shapes and cause trouble
Is the lossless model reasonable for Belden 8281
cable?
A/D
DSP
Transmission Lines
Resistor R and conductance G at losses to the cable
model
G0
R=0.0354/m
The impedance of the 8281 cable series inductance
dominates the cables series resistance once
frequencies exceed 15kHz
Lossless models seem appropriate for f>>15kHz
A/D
DSP
Skin Effect
Unfortunately, at frequencies > 1MHz another
loss mechanism comes into play
The skin effect causes a cables series
resistance to increase with frequency (f )
The skin effect is the dominant coaxial cable loss
mechanism at frequencies above 1MHz [7]
A/D
DSP
Transmission Lines
The transfer function (excluding the linear phase
component) of a length=L section of transmission line
properly terminated with its characteristic impedance
is given by
For Belden 8281 cable, k=1.023e-6
( )
( ) f j kL
C
e f H
+
=
1
A/D
DSP
NRZ Data and Filter Responses
G
a
i
n

(
d
B
)
20
-60
-40
-20
0
10
6
10
7
10
9
10
8
10
10
[Hz]
t
R
=100psec Gaussian
t
R
=0 NRZ
t
R
=3nsec Gaussian
A/D
DSP
Belden 8281 Cable Response
G
a
i
n

(
d
B
)
20
-60
-40
-20
0
10
6
10
7
10
9
10
8
10
10
[Hz]
Cable lengths:
50m
100m
150m
200m
A/D
DSP
Belden 8281 Cable Response
Cable attenuation is a strong function of length L
Especially at 200m its worse than 3ns rise/fall times
times
Its reasonable to expect severely degraded eye patterns at
100m and complete eye closure at 200m
Lets take a look at the 100m and 150m eye diagrams
A/D
DSP
100m8281 Cable Eye Diagram
2 nsec/div
0
.
8

V
/
d
i
v
300Mb/s
A/D
DSP
2 nsec/div
0
.
8

V
/
d
i
v
300Mb/s
A/D
DSP
Coaxial cable bandlimiting of the NRZ data signal
results in complete eye closure by 150m
And inadequate margins at 100m
Well have to do some signal processing on the
degraded NRZ signal before deciding what bits were
sent
That signal processing is called equalization, and
well examine equalization and noise next time
A/D
DSP
References
1. Andrew Viterbi, CDMA: Principles of Spread Spectrum Communications, 1995.
2. Alan Baker, An Adaptive Cable Equalizer for Serial Digital Video Rates to 400Mb/sec, ISSCC
Dig. Tech. Papers, 39, 1996, pp. 174-175.
3. David Potson and Alan Buchholz, A 143-360Mb/sec Auto-Rate Selecting Data-Retimer Chip
for Serial-Digital Video Signals, ISSCC Dig. Tech. Papers, 39, 1996, pp. 196-197.
4. Howard J ohnson and Martin Graham, High-Speed Digital Design: A Handbook of Black Magic,
1993, chapter 1 and appendix B.
5. J ohn Mayo, Bipolar Repeater for Pulse Code Modulation Signals, Bell System Technical
J ournal, 41, J an. 1962, pp. 25-47.
6. J ohn Kraus and Keith Carver, Electromagnetics, 1973, chapter 13.
7. Bell Laboratories, Transmission Systems for Communications, 5
th
Edition, 1982,
chapters 5 and 30.
8. Belden Electronics, Type 8281 75 Precision Video Cable datasheet, 2001.
9. National Semiconductor (Comlinear division), CLC014 and CLC016 datasheets, 1998.
EECS 247 Lecture 26: Equalization 2002 B. Boser 1
A/D
DSP
Equalization
Isolated pulse responses
Pulse spreading
Group delay variation
Equalization
Magnitude equalization
Phase equalization
The Comlinear CLC014 Equalizer
Equalizer bandwidth and noise
Bit error probabilities
A/D
DSP
Isolated Pulse Responses
Another way of looking at NRZ waveform degradation
is to examine transmission line response to an
isolated pulse
For purely random binary data, the pattern
[0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0]
appears, on average, once in every 2
20
20b patterns
Thats once every 20e6 bits
The transmission line output to this pattern is shown on the
following slide
A/D
DSP
2 bit periods/div
0
.
8

V
/
d
i
v
8281 cable length:
0m
50m
100m
150m
200m
A/D
DSP
2 bit periods/div
0
.
8

V
/
d
i
v
bit error at 100m for this pattern
(by chance it didnt show up in
the 100b eye pattern)
A/D
DSP
Pulse widths increase as the NRZ signal moves
down the cable
A common measure of pulse width is the Full Width at Half
Maximum, or FWHM
Isolated pulse width after 200m of cable is 2.2 bit periods are
shown in the next slide
They are a sure sign of group delay variation with
frequency
If all frequency components receive the same delay, pulses
cant spread out
Pulse widths of multiple bit periods obviously wreak havoc
on eye diagrams and data recovery
A/D
DSP
2 bit periods/div
0
.
8

V
/
d
i
v
FWHM is 2.2 bit periods at 200m
A/D
DSP
Transmission Line Group Delay
Cable transfer function:
Group delay
GR
-d()/d:
( )
( ) f j kL
C
e f H
+
=
1
( )
( )
f
kL
f
kL
GR
4
2
=
=
A/D
DSP
Belden 8281 Cable Group Delay
G
r
o
u
p

D
e
l
a
y

(
n
s
e
c
)
20
0
5
10
15
10
6
10
7
10
9
10
8
10
10
[kHz]
8281 cable length:
50m
100m
150m
200m
one bit
period
A/D
DSP
Transmission Line Group Delay
Note that each 50m cable segment adds the same
amount of group delay at each frequency
Consider each 50m segment of cable as a filter
Group delays of cable lengths in series add just like group
delays for filters in series
NRZ spectral density is constant below 10
8
Hz
Increasing amounts of low frequency group delay are
applied to decreasing amounts of signal energy
A/D
DSP
Equalization
Equalization is a pretty simple concept
If the cable response is:
A perfect equalizer built into the data receiver will have response:
So that
( )
( ) f j kL
C
e f H
+
=
1
( )
( ) f j kL
E
e f H
+ +
=
1
1 =
E C
H H
A/D
DSP
Equalization
In a world of perfect equalizers, wed never
need to worry about channel response
The receivers equalizer output would match the
signal transmitted into the cable
In the real world, equalizers arent perfect
Modeling their nonidealities is essential
Lets look at the significance of several
equalizer nonidealities
A/D
DSP
Equalization
Nonidealities to consider:
Equalizer bandwidth limitations
Imperfect gain equalization
Imperfect phase equalization
Noise
Our tool of choice for evaluating equalizer
effectiveness will be the eye diagram
The eye diagram for the receiver input after 100m
of Belden 8281 cable appears on the next slide
A/D
DSP
100m 8281 Cable Eye Diagram
2 nsec/div
2

V
/
d
i
v
300Mb/s
L=100m
A/D
DSP
Ideal Equalization (#1)
e
-af
2
H
E1
(f) = e
+kLf
e
+ jkLf
magnitude phase
A/D
DSP
Equalizer #1 Eye Diagram
2 nsec/div
2

V
/
d
i
v
L=100m
A/D
DSP
Gain Equalization (#2)
In order to assess the relative importance of gain and
phase equalization, well look at the 100m eye
diagram for a perfect magnitude equalizer which
ignores phase completely
Note that if you use a Parks-McClellan linear phase FIR gain
equalizer, you ignore nonlinear phase completely
Equalizer #2:
e
-af
2
H
E2
(f) = e
+kLf
A/D
DSP
2 nsec/div
2

V
/
d
i
v
L=100m
A/D
DSP
Phase Equalization (#3)
Next, well check out the 100m eye diagram for a
perfect phase equalizer which ignores magnitude
completely
Note that the 100psec Gaussian response is still
there to limit bandwidth
e
-af
2
H
E3
(f) = e
+ jkLf
A/D
DSP
2 nsec/div
2

V
/
d
i
v
L=100m
Equalizer #3 output is smaller,
because no gain compensates
for the cable loss
A/D
DSP
2 nsec/div
0
.
5

V
/
d
i
v
L=100m
Scope gain adjusted to compare
with Equalizers #1 and #2
A/D
DSP
Gain and Phase Equalization
If anything, phase equalization alone produces better
eye patterns than gain equalization alone
Gain equalizers are high pass filters and produce
spikey, high amplitude outputs
Scale analog signals to avoid clipping
Both gain and phase must be considered in channel
equalization
A/D
DSP
Equalizer #4
In the real world, nobody can afford equalizer #1
Reasonably robust approximations to the inverse of cable
transfer functions can be built with surprisingly simple analog
circuits
Lets see how Comlinears Alan Baker [1] built an
analog domain equalizer (equalizer #4) using just 6
analog poles
A/D
DSP
Equalizer #4
While Comlinears approach seems to violate our 5-pole analog signal
processing limit, Baker gets a waiver because he cascades two
identical 3-pole stages
Only one adjustable parameter is needed to equalize cable lengths
from 0m-300m
Each of the two identical stages compensates for 0-150m of cable loss
Only one adjustable parameter is needed to equalize cable lengths from
0m-300m
Each of the two identical stages compensates for 0-150m of cable loss
A/D
DSP
Equalizer #4 3-Pole Section
h
1
(s)=s/(s+p
1
) 0.21
h
2
(s)=s/(s+p
2
) 0.62
h
3
(s)=s/(s+p
3
) 12.1

v
OUT v
IN
= 0.19 for L=100m

= 1.00 for L=300m
[ p
1
p
2
p
3
] = 2 [ 0.62MHz 14.1MHz 282MHz]
A/D
DSP
2 nsec/div
2

V
/
d
i
v
=0.19
L=100m
An overequalized eye, but not bad
A/D
DSP
2 nsec/div
2

V
/
d
i
v
=1.00
L=300m
A beautiful eye at 300m!
A/D
DSP
Equalizer #4
While not approaching the ideal equalizer #1
response, equalizer #4 demonstrates the eye
quality youll see in real-world data receivers
Lets compare the equalizer #1 and #4
responses in the frequency domain
This provides an idea of how closely responses
have to match for the observed eye quality
A/D
DSP
100m Magnitude Responses
G
a
i
n

(
d
B
)
40
-40
-20
0
20
10
6
10
7
10
9
10
8
10
10
[Hz]
100m cable response
equalizer #1 response
1dB error OK
A/D
DSP
G
a
i
n

(
d
B
)
40
-40
-20
0
20
10
6
10
7
10
9
10
8
10
10
[Hz]
100m cable response
#4 is more highpass
than #1, leading to an
overequalized eye
A/D
DSP
Adaptive Equalization
Now that we know something optimal
equalization, how can a data receiver learn
what equalization to apply?
Cable lengths vary from 0-300m in the Comlinear
application
How does the CLC014 determine ?
Adaptive equalization is a complex topic, with
many different methods used in practice
A/D
DSP
Equalizers may be trained at data link startup, or they
may be continuously adaptive
Cable lengths dont change often, and service is interrupted
when they do
Adaptive analog methods include
Mapping equalizer p-p input voltage to (J ohn Mayos
method, [4])
Finding the value of that minimizes equalizer output jitter
Finding the value of that minimizes the difference between
the decision circuit output and the equalizer output
(Comlinears method)
A/D
DSP
Adaptive digital methods include Decision Feedback
Equalization and many others
DFE builds adaptive digital FIR filters whose coefficients
adjust to eliminate signal in bit periods N+1, N+2, thats
correlated with the signal in bit period N
Minimization of intersymbol interference leads to optimal
equalization
Digital-domain processing requires either a DAC or
an ADC
Excessive converter resolution can make DSP expensive or
infeasible at high data rates
A/D
DSP
Analog-digital adaptive hybrids are usually found in
IC data receivers
Minimal analog-domain pre-equalization reduces ADC (or
DAC) resolution and DSP datapath width (and digital power)
Maximal digital-domain adaptive FIR equalizers finish the job
29%/yr DSP cost reduction leads to steady migration
of equalization functions from the analog to digital
domain
In the limit, analog signal processing becomes a low Q
antialiasing filter and an ADC
A/D
DSP
Equalizer Models
Use equalizer behavioral models to understand
Communication channel variations
Analog equalizer component sensitivities
Analog signal swings
Adaptive equalization algorithms
Digital datapath specifications (bit-true, cycle-true DSP
models)
Equalizers are filters, so theres another important
performance consideration
NOISE
A/D
DSP
Equalizer Noise
For 300m cable lengths, the CLC014
equalizer provides lots of high frequency gain
to compensate for cable loss
The 300m equalizer magnitude response
appears on the following slide
A/D
DSP
G
a
i
n

(
d
B
)
60
-20
0
20
40
10
6
10
7
10
9
10
8
10
10
[Hz]
300m cable response
A/D
DSP
Equalizer Noise
Right at the input to the equalizer, theres bound to
be a thermal noise source with a transfer function to
the equalizer output equal to the equalizer transfer
function itself
Well assume that this noise source is equivalent to
that of a single 1k resistor; that is, 4nV/Hz
The integrated noise at the equalizer #4 output
appears on the next slide
A/D
DSP
G
a
i
n

(
d
B
)
60
-20
0
20
40
10
6
10
7
10
9
10
8
10
10
[Hz]
300m cable response
300m Equalizer Integrated Noise
10
-1
10
-2
10
-3
10
-4
10
-5
I
n
t
e
g
r
a
t
e
d

N
o
i
s
e

(
V
r
m
s
,

l
o
g

s
c
a
l
e
)
>10mVrms!
A/D
DSP
Equalizer Noise
10mVrms noise is a lot of noise!
Look at that noise on a scope and youll see 60mV of peak
to peak noise
Remember that this is the noise from just one 1k source
Real world circuits have lots of noise sources
Can we reliably detect digital bits with signal to noise
ratios of 40dB?
Absolutely!
Lets find out why
A/D
DSP
Equalizer Noise
Suppose that we have an eye opening at the equalizer output of
2v
OPEN
Lets also suppose that our timing recovery system samples the
equalizer output at the point where the eye is opened the widest
2v
OPEN
A/D
DSP
Equalizer Noise
If the instantaneous noise voltage is greater than +v
OPEN
when
were trying to detect a 1, a bit error results
If the instantaneous noise voltage is less than
v
OPEN
when were trying to detect a +1, a bit error results
To first order, the spectral distribution of the noise doesnt matter
Only the total integrated noise counts (its sampled!)
If the noise is Gaussian, error probabilities are a well understood
statistical problem
A/D
DSP
Bit Error Probabilities
The bit error probability is [5]:
erfc(x) is the complementary error function and v
INT
is the
total rms integrated noise
A plot of P
E
vs. v
OPEN
/v
INT
appears on the following
slide
=
INT
OPEN
E
V
V
erfc P
2 2
1
A/D
DSP
Bit Error Probability Plot
v
OPEN
/v
INT
l
o
g
1
0
P
E
0
-5
-10
-15
-20
0 8 6 4 2 10
10
-10
P
E
at v
OPEN
/v
INT
=6.4
A/D
DSP
Equalizer Noise
Error probability is an extremely strong function of
integrated noise
Integrated noise is a strong function of cable length and
equalizer bandwidth
Error probability is an extremely strong function of
eye opening
Eye opening is a strong function of equalization quality
Lots of high sensitivities are a characteristic of data
communication
A/D
DSP
Equalizer Noise
Before you start gloating over how easy it is to get a
P
E
of 10
-10
, talk to an analog designer
The analog designer tells you that
A 1k noise resistor is about 4X too low for a power-efficient
equalizer (v
INT
>20mV)
Signal-swings in continuous time equalizers built in low
voltage CMOS should be <100mVp-p (v
OPEN
<50mV)
A/D
DSP
Equalizer Noise
This digital communications system is closer to
practical IC design limits than one might think
Future give-and-take sessions with the analog designer may
pick up a dB or two of >100mV swings or <20mV noise
Every dB counts in the P
E
business
You resolve to apply one of the cardinal rules of
analog design to your equalizer:
Never use more bandwidth than you really need
A/D
DSP
Equalizer Noise
Raising channel risetime from 500psec to 2nsec doesnt change
the equalized v
OPEN
much
2v
OPEN
t
R
=500psec
t
R
=2nsec
A/D
DSP
G
a
i
n

(
d
B
)
60
-20
0
20
40
10
6
10
7
10
9
10
8
10
10
[Hz]
300m Equalizer Integrated Noise
10
-1
10
-2
10
-3
10
-4
10
-5
I
n
t
e
g
r
a
t
e
d

N
o
i
s
e

(
V
r
m
s
,

l
o
g

s
c
a
l
e
)
11mVrms
2.5mVrms
t
R
=500psec (solid)
t
R
=2nsec (dashed)
A/D
DSP
Equalizer Noise
Equalizer integrated noise grows linearly with
bandwidth
Excess bandwidth can limit your range
Optimizing both signals and noise is the real
art of equalization (or any other filtering)!
Well examine the rest of the data recovery
story next time
A/D
DSP
References
1. Alan Baker, An Adaptive Cable Equalizer for Serial Digital Video Rates to
400Mb/sec, ISSCC Dig. Tech. Papers, 39, 1996, pp. 174-175.
2. National Semiconductor (Comlinear division), CLC014 and CLC016
datasheets, 1998.
3. Belden Electronics, Type 8281 75 Precision Video Cable datasheet,
2001.
4. J ohn Mayo, Bipolar Repeater for Pulse Code Modulation Signals, Bell
System Technical J ournal, 41, J an. 1962, pp. 25-47.
5. Bell Laboratories, Transmission Systems for Communications, 5
th
Edition,
1982, chapter 30.
EECS 247 Lecture 27: Offset Control 2002 B. Boser 1
A/D
DSP
Offset Control
Offset control in data receivers
dc offset
ac coupling
Baseline wander
Quantized feedback
Decision circuits
A/D
DSP
Equalizer Gain
h
1
(s)=s/(s+p
1
) 0.21
h
2
(s)=s/(s+p
2
) 0.62
h
3
(s)=s/(s+p
3
) 12.1

v
OUT v
IN
= 1.00 for L=300m

p
3
= 2 (282MHz)
A/D
DSP
Equalizer Gain
Comlinears cable equalizer uses 2 of the 3-pole
sections in cascade
the highest value of equalizer gain appears to approach
12.1
2
=43dB at high frequencies
In practice, equalizer bandlimiting is required to limit
noise and achieve acceptable bit error rates
maximum equalizer gain falls to about 32dB
A/D
DSP
G
a
i
n

(
d
B
)
60
-20
0
20
40
10
6
10
7
10
9
10
8
10
10
300m Equalizer Response
10
-1
10
-2
10
-3
10
-4
10
-5
I
n
t
e
g
r
a
t
e
d

N
o
i
s
e

(
V
r
m
s
,

l
o
g

s
c
a
l
e
)
t
R
=500psec (solid)
t
R
=2nsec (dashed)
A/D
DSP
Equalizer Offsets
Almost all data equalizers provide gain to
compensate for channel losses
This gain also gains up offsets arising from device
mismatches in amplifier stages
Typical high-speed amplifier stages have 10mV input-
referred offsets
Most implementations of the Comlinear equalizer
provide that gain (43dB) also to dc offsets
Left uncorrected, a 10mV input-referred offset becomes a
1.5V output offset
A/D
DSP
Offset Eye Diagrams
2 nsec/div
2

V
/
d
i
v
=1.00
L=300m
Eye quality doesnt matter if offsets
cause us to miss the data completely!
0V
A/D
DSP
Equalizer Offsets
Even modest offsets can reduce the effective eye
opening significantly
The resulting effect on P
E
can be severe
The offset in the next slide results in a substantial
bias in favor of -1+1 errors
A/D
DSP
Offset Eye Diagrams
2 nsec/div
2

V
/
d
i
v
=1.00
L=300m
Offset causes a 2dB reduction in v
OPEN
0V
A/D
DSP
Equalizer Offsets
Offset control is an important and under-
appreciated component of data receiver
architecture
The catch is that offsets must be controlled without
slowing down the signal path
Offset control schemes often take as much design
time as equalization itself
Initial design schedules typically underestimate this effort
by wide margins
A/D
DSP
ac Coupling
ac coupling between
amplifier stages is an
obvious form of offset
control:
Where should we set
the HPF corner
frequency?
R
C v
IN v
OUT
A
1
A
2
H(s) =
s
s +
P
A/D
DSP
Comlinear 3-Pole Section
h
1
(s)=s/(s+p
1
) 0.21
h
2
(s)=s/(s+p
2
) 0.62
h
3
(s)=s/(s+p
3
) 12.1

v
OUT v
IN
p
1
= 2 (620kHz)
phase equalization provided by p
1
ends below 62kHz
A/D
DSP
ac Coupling
A 10M, 2.5pF ac coupling network (=RC=25sec)
can remove dc offsets from the Comlinear equalizer
without much effect on its phase response above
62kHz
The large resistorcan be realized with a long, narrow FET
Does the high pass filters own frequency response
create any new problems in the NRZ data receiver?
The answer is yes
The problem is called baseline wander
A/D
DSP
Baseline Wander
Suppose our NRZ data
stream comes from a
sparsely populated binary
file with lots of consecutive
zeros in it
Well model the data stream
as
100sec of random 1V
data at 300Mb/s
100sec of a fixed 1V level
(models 30000 zeros in a
row)
R
C v
IN
v
OUT
A
1
A
2
H(s) =
s
s +
P
A/D
DSP
Sparse HPF Input Data
2V
1V
0V
-1V
random data
30000 consecutive zeroes (100sec)
A/D
DSP
HPF Output
2V
1V
0V
-1V
the HPF output baseline decays to 0 (=25sec)
A/D
DSP
Baseline Wander
The high pass filter causes the middle of the data eye
to wander with low frequency components in the NRZ
data stream
Common data idling patterns move decision thresholds to
the edges of the data eye
With disastrous consequences for bit error rates
Localized concentrations of 1s or +1s lasting on the order
of 0.05 reduce eye opening 0.5dB
Substantially increasing bit error rates
What can we do about it?
A/D
DSP
Baseline Wander
Data scrambling can reduce the probability of perverse patterns
Common sparse sequences are mapped to transition-rich
sequences
With 1:1 mapping, some irregular sequence will still map to a
perverse baseline sequence, and the resulting baseline wander will
cause errors
Coding tricks can add extra bits to the data stream to ensure
transition density
An 8b-9b code maps 8 data bits to 9 transmitted bits, with sparse
patterns omitted from the 9b patterns
NRZ data throughput is reduced by the 8/9 factor
A/D
DSP
Quantized Feedback
The problem is that the HPF assumes the data
sequence has zero mean
If we knew the data sequence, we could of course
calculate this mean and add it to the HPF output
Do we?
It appears at the output of the receiver
A/D
DSP
Quantized Feedback
Quantized feedback combines a decision circuit (a comparator)
and an ac coupling network in an ingenious way [2]:
R
C
v
IN
v
OUT
LPF
A/D
DSP
Quantized Feedback
The comparator is designed to produce the same p-p
output swing as v
IN
:
R
C
v
IN
v
OUT
LPF
1V swings
A/D
DSP
Quantized Feedback
How should we set the bandwidth of the LPF?
Model the quantizer as a gain (=1)
We want V
OUT
=V
IN
Solve
R
C
v
IN
v
OUT
H(s)
1
P
s
s
+
( )
P
P
s
s H
+
=
A/D
DSP
Quantized Feedback
Quantized feedback uses a low pass filtered version of the
decision circuit output to eliminate the high pass function
dc offset is blocked
R
C
v
IN
v
OUT
C
R
A/D
DSP
Quantized Feedback
C
v
IN
v
OUT
R
Though not as simple to visualize, the simplified
circuit below does precisely the same thing
A/D
DSP
Quantized Feedback Output
2V
1V
0V
-1V
30000 consecutive zeroes (100sec)
A/D
DSP
Digital Quantized Feedback
Analog-digital hybrids can also
provide baseline wander
correction
The H(z) block maps a logic-
level v
OUT
to channel signal
levels
6-7 DAC bits span the full v
IN
range
Startup andv
IN
-v
OUT
level
mismatches must be carefully
modeled
R
C
DAC
v
IN
H(z)
v
OUT
A/D
DSP
Decision Circuits
Decision circuits generate square wave outputs at the
output of the receiver
The square wave outputs typically drive a clocked, cross-
coupled CMOS latch which produces full logic level swings [4]
Decision circuits convert all sources of vertical eye
degradation into horizontal eye degradation
A decision circuits output transitions between two binary levels
at a process-limited (NOT a data rate-limited) speed
A/D
DSP
Decision Circuit Eye Diagram
2 nsec/div
1

V
/
d
i
v
=1.00
L=300m
The eye is now horizontal!
latch data valid at
A/D
DSP
Decision Circuit Eye Diagram
Obviously the bit error rate depends critically
on the position of the green arrows
Those are generated by the clock recovery circuit
Typically those use an analog or digital PLL
We will leave that for 142!
A/D
DSP
The End
Weve looked at filters, converters, communication
circuits
But especially we looked at how to model them
To come up with good architectures
To invent at the architecture level
To evaluate system performance at a high level where
changes are manageable
Good luck and good circuits, and thanks for taking
my class!
A/D
DSP
References
1. Alan Baker, An Adaptive Cable Equalizer for Serial Digital Video Rates
to 400Mb/sec, ISSCC Dig. Tech. Papers, 39, 1996, pp. 174-175.
2. F. D. Waldhauer, Quantized Feedback in an Experimental 280Mb/s
Digital Repeater for Coaxial Transmission, IEEE Trans. on
Communications, COM-22, J anuary 1974, pp. 1-5.
3. Dave Pietruszynski, J ohn Steininger, and E. J . Swanson, A 50Mbit/sec
CMOS Monolithic Optical Receiver, IEEE J SSC, SC-23, December
1988.
4. Akira Yukawa, A CMOS 8-Bit, High-Speed A/D Converter IC, IEEE
J SSC, SC-20, J une 1985.

Merge

Caricato da

Informazioni sul documento

Descrizione originale:

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Merge

Caricato da

Copyright:

Formati disponibili

EECS 247 Lecture 1: Overview 2002 B.

Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com

Distance from origin in s-plane:

Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com

Note: Always represent transfer functions as a product of a gain

EECS 247 Lecture 4: Dynamic Range 2002 B. Boser 16

Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com

Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com

EECS 247 Lecture 7: Finite Bandwidth 2002 B. Boser 4

Q enhancement peaking in response (or instability)

Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com

Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com

0 0.1 0.2 0.3 0.4 0.5

SC filters have comparable or

EECS 247 Lecture 10: SC Filter Frequency Response 2002 B. Boser 16

EECS 247 Lecture 10: SC Filter Frequency Response 2002 B. Boser 22

EECS 247 Lecture 11: Digital Filters 2002 B. Boser 16

Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com

Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com

0 0.5 1 1.5 2 2.5 3

Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com

EECS 247 Lecture 15: Sampling 2002 B. Boser 6

Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com

EECS 247 Lecture 19: Oversampling 2002 B. Boser 46

EECS 247 Lecture 21: Oversampled ADC Implementation 2002 B. Boser 10

Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com

Small nonlinearities applied to aggressively shaped

Simpo PDF Merge and Split Unregistered Version - http://www.simpopdf.com

= 0.19 for L=100m

= 1.00 for L=300m

Potrebbero piacerti anche