A New Poly-Si Triple-Gate Thin-Film Transistor

(TG-TFT) with Diminished Pseudo-Subthreshold

Region: Theoretical Investigation and Analysis
IEEE Trans. on Electron Devices, Vol.52, pp.1815-1820, August 2005

Ali A. Orouji1 Member, IEEE and M. Jagadesh Kumar2 Senior Member, IEEE
Department of Electrical Engineering,
Indian Institute of Technology, Delhi,
Hauz Khas, New Delhi – 110 016, INDIA.
Email: mamidala@ieee.org Fax: 91-11-2658 1264

1
Ali A. Orouji is a Ph.D. scholar at the Indian Institute of Technology, Delhi and is sponsored by Semnan
University, Semnan, IRAN.
2
Corresponding author
Abstract- In this paper, we have proposed a new poly-Si Triple-Gate thin-film transistor (TG-

TFT) where the front gate consists of two materials and three sections in order to reduce the OFF

state leakage current without affecting the ON state voltage. We have used one and three grain-

boundaries in the channel for analyzing the electrical characteristics of the poly-Si TG-TFT. The

key idea in this work is to make the dominant conduction mechanism in the channel to be

controlled by the accumulation charge density modulation by the gate (ACMG) and not by the

gate-induced grain barrier lowering (GIGBL). As a result, we demonstrate that the TG-TFT

exhibits a highly diminished pseudo-subthreshold region resulting in a substantial OFF state

leakage current without any significant change in the ON voltage when compared to a

conventional poly-Si TFT (C-TFT). Using two-dimensional and two-carrier device simulation,

we have examined various design issues of the TG-TFT and provided the reasons for the

improved performance.

Index Terms- Polysilicon, thin film transistor, pseudo-subthreshold, leakage current, grain

boundary, traps, two-dimensional (2-D) simulation.

 I. INTRODUCTION

Poly-Silicon thin film transistors (TFTs) have been studied extensively in recent years for

their application in flat panel active matrix liquid crystal displays (AMLCD) [1], [2]. For these

applications, scaled-down poly-Si TFTs with high performance and high reliability are required

[3]. One of the problems of poly-Si TFTs is the large OFF state leakage current due to the

presence of the grain boundaries in the channel [4] resulting in poor switching characteristics.

Various solutions such as the offset gate, the p-n-p gate and the lightly doped drain (LDD) poly-

Si TFT structures have been proposed to reduce the OFF state leakage currents [5-8].

In keeping with the general trends of the CMOS technology, the channel lengths of the

poly-Si TFTs are now aggressively scaled down to submicron lengths [9, 10]. Also, by scaling

the channel of the device down to a length comparable to the poly-Si grain size, using modern

metal-induced lateral crystallization (MILC) or excimer laser annealed (ELA) methods to control

the grain growth, it is possible to create devices where only a single or small number of discrete

grain boundaries exist in the channel of the poly-Si TFT [11, 12]. This ability to control the grain

size to form the well-arranged grains in the channel has resulted in high performance polysilicon

TFTs [13-15] typically with one or fewer grain boundaries in the channel [11,15]. However, the

off-state leakage currents in these advanced poly-Si TFTs are orders of magnitude larger than

those observed in conventional single-crystal SOI MOSFETs.

The conventional SOI MOSFET exhibits a steep subthreshold slope and a clear turn-on

region in its transfer characteristic. The dominant conduction mechanism is due to the inversion

charge density modulated by the gate (ICMG) [16]. On the other hand, there are two regions in

the transfer characteristic of a poly-Si TFT as shown in Fig.1. The region below threshold
condition (Vt) is called the subthreshold region and the region between Vt and the turn-on

condition (VON) is called the pseudo-subthreshold region. Unlike in the case of SOI MOSFETs,

in which the log(ID)-VGS curve is very sharp and quickly becomes linear, in the case of poly-

TFTs, the transition from the exponential to the linear region is much more gradual [17, 18]. The

dominant conduction mechanism below the turn-on region (VON) is due to the gate-induced grain

barrier lowering (GIGBL) and is not controlled by the accumulation charge density modulation

by the gate (ACMG) [17]. The challenge that we have addressed in this paper, therefore, is to

examine if we can convert the dominant conduction mechanism in a poly-Si TFT with fewer

grain boundaries, from gate-induced grain barrier lowering (GIGBL) to accumulation charge

density modulation by the gate (ACMG) so that the pseudo-subthreshold region is significantly

diminished in the transfer characteristic. In this paper, therefore, we have considered only one

and three grain boundaries in the channel of the poly-Si TFT [11-15]. If we succeed in realizing a

diminished pseudo-subthreshold region, the poly-Si TFT should behave almost like the

conventional single-crystal SOI MOSFET with a steep subthreshold slope resulting in a

significant reduction in the OFF state leakage current.

Based on the above idea, the aim of this paper is therefore to propose for the first time, a

new device structure called the Triple Gate poly-Si TFT (TG-TFT) in which the front gate

consists of two side gates on both sides of the main gate. The work function of the side gates is

different from that of the main gate resulting in a modified channel potential. Using two-

dimensional simulation [19], we demonstrate that this leads to highly diminished pseudo-

subthreshold region in the transfer characteristics of the TG-TFT resulting in a significantly

reduced OFF state leakage current compared to the conventional poly-Si TFT (C-TFT). The

effects of varying the side gate parameters, trap density at the grain boundaries, number of grain
boundaries in the channel and temperature of the device are investigated. Our results demonstrate

that the proposed TG-TFT exhibits significantly reduced leakage current thus making it a more

reliable device configuration than the C-TFT for high performance poly-Si TFT circuit

applications.

II. TG-TFT STRUCTURE

A schematic cross-sectional view of the TG-TFT implemented in the 2-D device

simulator MEDICI is shown in Fig.2. The gate region consists of p+-poly and n+-poly for the side

gates and the main gate, respectively. The channel of the device is undoped poly-Si with a single

grain boundary (GB) in the center. The regions on both sides of GB are assumed to be

completely defect-free meaning all the defect states are localized in the GB. The capture and

emission processes are handled by the simulator using Shockley-Read-Hall recombination model

and a conventional drift-diffusion method is used to model the carrier transport. Also, we have

employed the Caughey-Thomas model [20] for the mobility based on the work of Kitahara et al

[21].

The doping in the n+ source/drain regions is kept at 1×1019 cm-3. The effective trapping

density at the grain boundary is taken to be 1×1013 cm-2 and the trap energy relative to the

conduction and valence bands are 0.51 eV and 0.51 eV for electron and hole traps, respectively.

The capture rate for electrons and holes are identical and equal to 1×10-8 cm3/sec [9]. It is

assumed that the trap density of the acceptor-like states and donor-like states are identical. The

donor-like state is defined as a trap state that is positively charged when holes are captured and

the acceptor-like state is negatively charged when electrons are captured. The width of the GB

(i.e. distance between the two grains) is 10 nm [22]. The silicon thin film and the gate oxide

thicknesses are 50 and 10 nm, respectively. The main gate and the side gate lengths (LM and LS)
are identical and the channel length L (=2LS+LM) is kept constant at 0.4 μm in our simulations.

The work functions of the p+-poly and the n+-poly gates are chosen as 5.25 eV and 4.17 eV,

respectively. All the device parameters of the TG-TFT are equivalent to those of the C-TFT

unless mentioned. A similar simulation approach has been used by Walker et al [9] to prove the

validity of their model. The polarity between source and drain in poly-Si TFTs in AMLCD

applications is required to be altered to reduce the DC stress of liquid crystals [23]. Therefore,

for such applications it is advantageous to have a symmetrical Poly-Si TFT structure by having

identical side gates on both sides of the main gate as suggested in the proposed TG-TFT.

III. SIMULATION RESULTS AND DISCUSSION

A. Modifying Channel Potential Distribution:

The key idea behind the TG-TFT operation is to modify the channel potential so that the

channel conduction is controlled by the accumulation charge density modulation by the gate

(ACMG) and not by GIGBL. A typical MEDICI simulated 2-D conduction band potential

distribution for TG-TFT and C-TFT structures for the drain to source voltage VDS = 0 V is shown

in Fig. 3. It can be seen from Fig. 3(a) that a potential barrier (central barrier) is formed at the

GB because the carriers are immobilized by the traps due to the strain and the dangling bonds

located at the grain boundary [24, 25]. Therefore, the dominant conduction mechanism of the C-

TFT is determined by GIGBL. But, in the proposed TG-TFT due to its triple-gate structure, in

addition to the central barrier, two extra barriers (side barriers) are created in the side gate

regions due to the work function difference between the side gate and the main gate as shown in

Fig. 3(b) in which the side and central barriers not only differ in their height but also in their

shape. Therefore, the dominant conduction mechanism of the TG-TFT should now be controlled

by the side barriers since the central barrier does not play any significant role. In that case, we
should have a steep subthreshold slope in the transfer characteristic of the device just as observed

in a typical single crystal SOI MOSFET. With increasing gate voltage, however, the height of the

side barrier will decrease and at some critical gate voltage(VCGS), the side barrier height will

become equal to the central barrier height as shown in Fig. 3 (c) for VGS = 0.52 V. After this

critical gate voltage (VCGS) condition is reached, the channel conduction mechanism will be

determined by GIGBL.

B. Diminished Pseudo-Subthreshold Region:

In Fig. 4, the transfer characteristics of the TG-TFT are compared with that of the C-TFT

and the single crystal SOI MOSFET. We notice from this figure that as speculated above, for all

gate voltages less than the critical gate voltage VCGS (= 0.52 V), the subthreshold slope of the

TG-TFT is very steep similar to that commonly observed in SOI MOSFETs. For gate voltages

greater than VCGS, the transfer characteristic of the TG-TFT matches with that of the C-TFT

since now the height of the central barrier is larger than that of the side barriers. Therefore, it is

clear that because of the steep subtrheshold slope, the TG-TFT will have several orders of

magnitude lesser off-state leakage current when compared to the C-TFT. This has become

possible by nullifying the effect of the central barrier associated with the grain boundary on the

channel conduction mechanism so that the pseudo-subthreshold region is almost eliminated.

C. Effect of Side Gate Work Function on VCGS:

The value of critical gate voltage VCGS at which the central barrier height becomes equal to

the side barrier height is very important in controlling the pseudo-subthreshold region and hence

the reduction in the off-state leakage current. If the critical gate voltage VCGS is near to zero or

negative, the TG-TFT structure is not very useful in improving leakage current and will behave

like the C-TFT. An important parameter that determines the value of VCGS is the work function of
the side gate (ϕMsg). Fig.5 shows the transfer characteristic of the TG-TFT for different work

functions of the side gate region. It can be seen from the figure that as the work function of the

side gate decreases, the critical gate voltage VCGS will reduce forcing the behavior of TG-TFT

approach that of the C-TFT. This is because if the work function of the side gate decreases for a

given work function of the main gate, the height of the side barriers will also decrease.

Therefore, it is very important to choose appropriate work function for the side gate for given

main gate work function (ϕMmg).

D. Effect of Channel Length:

Fig. 6 shows the transfer characteristics of the TG-TFT compared with that of the C-TFT

for channel lengths ranging from 0.3 μm to 1.0 μm. Just as is commonly observed in the case of

the single crystal SOI-MOSFET [16], the slope of the subthreshold region will improve as the

channel length increases. What is important to note is that there is no significant change in the

critical voltage VCGS with increase in the channel length because the interaction between side and

central barriers will reduce as the channel length increases. However, it is important to note that

the short channel effects in the TG-TFT structure need to be investigated further to understand

how the improvement will hold good for shorter channel versions of TG-TFT.

E. Effect of Trap Density:

The conductivity in polycrystalline TFT is strongly dependent on the trap density at the

GBs and has been described by many authors [24-27]. Fig. 7 shows the transfer characteristics of

TG-TFT and C-TFT structures for different trap densities. It can be seen from the figure that the

pseudo-subthreshold region will be more gradual with increasing trap density at the GB and

VCGS will increase. However, the subthreshold slope of the TG-TFT remains unchanged giving
rise to a substantial reduction in the off-state current even if the trap density is large.

F. Effect of Temperature:

One of the important concerns in the operation of poly-Si TFTs is the temperature

dependence of their performance. Due to the gradual subthreshold slope, the C-TFTs show

stronger temperature dependence compared to the conventional SOI MOSFETs. Fig. 8 shows the

temperature dependence of the TG-TFT and the C-TFT structures. We notice that even at 400 K,

the off-state current of the TG-TFT is much smaller and the subthreshold slope is steeper than

that of the C-TFT. This is an important advantage of the TG-TFT over that of the C-TFT at

higher ambient temperatures.

It is worth noting that in a real device it is difficult to control the position of the GB

relative to the source and drain and therefore the position dependence of the GB in the channel is

very important in conventional poly-Si TFTs. However our simulation results suggest that there

is no significant change in the transfer characteristic of TG-TFT even if there is a 20 percent shift

in the position of the GB with respect to the center of the channel.

IV. DESIGN ISSUES OF TG-TFT

A. Choice of Side Gate Length:

In all our simulations above, we have chosen the main gate length LM equal to the side

gate length LS as proposed by Kumar et al for the dual material gate (DMG) SOI MOSFET [28-

31]. They showed that if the side gate length is equal to the main gate length, the off-state

leakage current is very small. To examine the effect of the side gate length on the leakage

current, we have compared the transfer characteristic of the TG-TFT for different side gate
lengths as shown in Fig. 9. As can be seen from the figure, there is no significant change in the

critical gate voltage VCGS when the side gate length is reduced with respect to the main gate

length. However, we conclude that the subthreshold slope is steeper and the leakage current is

the lowest when the side gate length is equal to the main gate length for the fixed channel length.

B. Effect of Multiple Grain Boundaries:

To examine the behavior of the TG-TFT in the presence of multiple grains in the channel,

we have investigated the performance of the TG-TFT structure with three GBs in the channel.

Fig. 10 shows a comparison of the transfer characteristic of the TG-TFT with the C-TFT with

three GBs present in the main channel and for different distances between these grains. Three

conclusions can be drawn from the figure. First, the TG-TFT structure works very well even in

the presence of multiple grain boundaries in the channel. Second, when the distance between the

GBs is large, due to an increase in the interaction between the side barriers and the trap barriers,

the slope of transfer characteristic of the TG-TFT will increase. However, even in this case, the

transfer characteristic of the TG-TFT is significantly better than that of the C-TFT. Third, in the

presence of multiple GBs in the channel, the pseudo-subthreshold slope in the C-TFT further

deteriorates.

For the chosen LS and LM values, if the distance between grain boundaries further

increases, it is quite possible that GBs may appear under the side gates as shown in Fig. 11.

Even in this case, we observe that by choosing appropriate LS and LM values, we can still realize

diminished pseudo-subthreshold region in the TG-TFT making its subthreshold slope very steep

as can be seen from the transfer characteristic shown in Fig. 11.

 V. CONCLUSIONS

To reduce the leakage current and for improving the performance of poly-Si TFT in

AMLCD or other applications, we have proposed a novel Triple-Gate poly-Si TFT (TG-TFT). In

this structure, two side gates on either side of the main gate whose work functions are different

from the main gate are used so that the dominant conduction mechanism in the channel is

controlled by the accumulation charge density modulation by the gate (ACMG) and not by the

gate-induced grain barrier lowering (GIGBL). The performance of the proposed TG-TFT has

been evaluated using two-dimensional simulation and compared with that of a conventional

poly-Si TFT. Based on our simulation results, we demonstrate that due to the presence of side

barriers which are more dominant than the central potential barrier associated with the grain

boundaries, the pseudo-subthreshold region is significantly diminished resulting in several orders

of magnitude reduction in the OFF state leakage current with no detectable change in the ON

voltage. We have also studied the different aspects of the device design such as the effect of

varying the channel length, number of grain boundaries, trap density at the grain boundaries,

temperature and the work function of the gate material, and the reasons for the improved

performance are presented. The significantly reduced leakage current in the TG-TFT due to the

diminished pseudo-subthreshold region is expected to provide the incentive for experimental

verification.
 REFERENCES

[1] T. Tanaka, H. Asuma, K. Ogawa, Y. Shinagawa, and N. Konishi, “An LCD

addressed by a-Si:H TFTs with peripheral poly-Si TFT circuits,” IEDM Tech.
Dig., pp. 389-392, 1993.
[2] T. Aoyama, K. Ogawa, Y. Mochizuki, and N. Konishi, “Inverse staggered poly-Si
and amorphous Si double structure TFTs for LCD panels with peripheral driver
circuit integration,” IEEE Trans. Electron Devices, vol. 43, pp. 701-705, May
1996.
[3] A. Hara, Y. Mishima, T. Kakehi, F. Takeuchi, M. Takei, K. Yoshino, K. Suga, M.
Chida, and N. Sasaki, “High performance poly-Si TFTs on a glass by a stable
scanning CW laser lateral crystallization,” IEDM Tech. Dig., pp. 747-750, 2001.
[4] J. G. Fossum, A. Oritz-Conde, H. Shichijo, and S. K. Banerjee, “Anomalous
leakage current in LPCVD polysilicon MOSFETs,” IEEE Trans. Electron
Devices, vol. ED-32, pp. 1878-1884, 1985.
[5] A. Kohno, T. Sameshima, N. Sano, M. Sekiya, and M. Hara, “High performance
poly-Si TFT fabricated using pulsed laser annealing and remote plasma CVD with
low temperature processing,” IEEE Trans. Electron Devices, vol. 42, pp. 251-257,
Feb. 1995.
[6] M. Yazaki, S. Takenaka, and H. Oshima, “Conduction mechanism of leakage
current observed in metal-oxide-semiconductor transistors and poly-Si thin-film
transistors, “ Jpn. J. Appl. Phys. vol. 31, pp. 206-209, 1992.
[7] B. Min, C. Park, and M. Han, “A Novel Polysilicon Thin-Film Transistor with a p-
n-p Structured Gate Electrode,” IEEE Electron Device Lett., vol. 17, pp. 560-562,
Dec. 1996.
[8] Z. Xiong, H. Liu, C. Zhu, and J. K.O. Sin, “Characteristics of High-k Spacer
Offset-Gated Polysilicon TFTs,” IEEE Trans. Electron Devices, vol. 51, pp. 1304-
1308, Aug. 2004.
[9] P. M. Walker, H. Mizuta, S. Uno, Y. Furuta and D. G. Hasko, “Improved off-
current and subthreshold slope in aggressively scaled poly-Si TFTs with a single
grain boundary in the channel,” IEEE Trans. Electron Devices, vol.51, pp. 212-
219, Feb. 2004.
[10] S. D. Brotherton, C. Glasse, C. Glaister, P. Green, F. Rohlfing, and J. R. Ayres,
“High-speed, short-channel polycrystalline silicon thin film transistors,” J. Appl.
Phys. Lett., vol. 84, pp. 293-295, 2004.
[11] J.-H. Jeon, M.-C. Lee, K.-C. Park, and M.-K. Han, “A new polycrystalline silicon
TFT with a single grain boundary in the channel,” IEEE Electron Device Lett.,
vol.22, pp. 429-431, Sep. 2001.
[12] C.-H. Oh and M. Matsumura, “A proposed single-boundary thin-film transistor,”
IEEE Electron Device Lett., vol. 22, pp. 20-22, Jan. 2001
[13] H.-C. Cheng, L.-J. Cheng, C.-W. Lin, Y.-L Lu, and C.-Y. Chen, ’High
performance low-temperature processes polysilicon TFTs fabricated by excimer
laser crystallization with recessed-channel structure,” AMLCD Tech. Dig. P.281,
2000.
[14] L. Mariucci, R. Carkuccio, A. Pecora, V. Foglietti, G. Fortunato, P. Legagneux, D.
Pribat, D. Della Sala, and J. Stoemenos, “Lateral growth control in excimer laser
crystallized polysilicon,” Thin Solid Films, vol. 337, pp. 137-142, 1999.
[15] M. A. Crowder, P. G. Carey, P. M. Smith, R. S. Sposili, H. S. Cho, and J. S. Im,
“Low-temperature single-crystal Si TFTs fabricated on Si films processed via
Sequential lateral solidification,” IEEE Electron Device Lett., vol. 19, pp. 306-
308, 1998.
[16] J.-P. Colinge, Silicon-On-Insulator Technology: Material to VLSI, Amsterdam,
Kluwer Academic Publishers, 2004.
[17] T.-S. Li and P.-S. Lin, “On the pseudo-subthreshold characteristics of
polycrystalline-silicon thin-film transistors with large grain size,” IEEE. Electron
Device Lett., vol. 14, pp. 240-242, May 1993.
[18] M. D. Jacunski, M. S. Shur, and M. Hack, “Threshold voltage, Field effect
mobility, and gate-to channel capacitance in polysilicon TFTs,” IEEE Trans.
Electron Devices, vol.43, pp.1433-1440, Sep. 1996.
[19] MEDICI 4.0, Technology Modeling Associates, Palo Alto, CA, 1997.
[20] D. M. Caughey and R. E. Thomas, “Carrier mobilities in silicon empirically
related to doping and field,” Proc. IEEE, vol. 55, pp. 2192-2193, 1967.
[21] Y. Kitahara, S. Takagi, and N. Sano, “Statistical study of subthreshold
characteristics in polycrystalline silicon thin-film transistors,” J. Appl. Phys., vol.
94, pp. 7789-7795, Dec. 2003.
[22] F. M. Hossain, J. Nishii, S. Takagi, A. Ohtomo, and T. Fukumura, “Modeling and
simulation of polycrystalline Zno thin-film transistors,” J. Appl. Phys. vol. 94, pp.
7768-7777, Dec. 2003.
[23] K. Suzuki, “Pixel design of TFT-LCD’s for high quality images,” SID Symposium
Dig., pp. 39-42, 1992.
[24] J. Y. W. Seto, “The electrical properties of polycrystalline silicon films,” J. Appl.
Phys., vol. 46, pp. 5247-5254, Dec. 1975.
[25] G. Baccarani, B. Ricco, and G. Spadini, “Transport properties of polycrystalline
silicon films,” J. Appl. Phys., vol. 49, pp. 5565-5570, Nov. 1978.
[26] M. Kimura, S. Inoue, T. Shimoda, and T. Sameshima, “Device simulation of grain
boundaries in lightly doped polysilicon films and analysis of dependence on defect
density,” Jpn. J. Appl. Phys. vol. 40, pp. 49-53, Jan. 2001.
[27] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M.
Rider, “Conductivity behavior in polycrystalline semiconductor thin film
 transistors,” J. Appl. Phys. vol. 53, pp. 1193-1202, Feb. 1982.
[28] M. J. Kumar and A. Chaudhry, “Two-Dimensional analytical modeling of Fully
Depleted DMG SOI MOSFET and evidence for diminished SCEs,” IEEE Trans.
Electron Devices, vol. 51, pp. 569-574, Apr. 2004.
[29] A. Chaudhry and M. J. Kumar, “Investigation of the novel attributes of a Fully
Depleted Dual-Material Gate SOI MOSFET,” IEEE Trans. Electron Devices, vol.
51, pp. 1463-1467, Sep. 2004.
[30] A. Chaudhry and M. J. Kumar, "Controlling short-channel effects in deep
submicron SOI MOSFETs for improved reliability: A Review", IEEE Trans.
Device and Materials Reliability, Vol.4, pp.99-109, March 2004.
[31] G. V. Reddy and M. J. Kumar, "A New Dual-Material Double-Gate (DMDG)
Nanoscale SOI MOSFET – Two-dimensional analytical modeling and
simulation," IEEE Trans. Nanotechnology, vol.4, pp.260-268, March 2005.
 Figure Captions

Fig. 1 Typical transfer characteristic of a conventional poly-Si TFT operated in

linear region [18].
Fig. 2 Cross-sectional view of the TG-TFT.
Fig. 3 Conduction band potential distribution for a) C-TFT (VGS = 0 V), b) TG-
TFT (VGS = 0 V), and c) TG-TFT (VGS = 0.52 V) with VDS = 0 V.
Fig. 4 A comparison of the transfer characteristics of TG-TFT, C-TFT, and C-
SOI structures.
Fig. 5 Transfer characteristic of TG-TFT structure for different work functions
of side gates.
Fig. 6 Transfer characteristics of TG-TFT and C-TFT for different channel
lengths.
Fig. 7 Transfer characteristics of TG-TFT and C-TFT for different grain
boundary trap densities.
Fig. 8 Transfer characteristics of TG-TFT and C-TFT for different
temperatures.
Fig. 9 Transfer characteristics of TG-TFT for different side gate lengths. LM and
LS are the main and side gate lengths, respectively.
Fig. 10. Transfer characteristics of TG-TFT and C-TFT for three grain boundaries
in the channel with all three grain boundaries present under the main
gate.
Fig.11. Transfer characteristics of TG-TFT and C-TFT for three grain boundaries
in the channel with one grain boundary present under each side gate.
 -4
VON
-6
Log (ID, A)

Vt
-8
-10 Pseudo-
Subthreshold
-12 Region
-14
-2 0 2 4 6 8
VGS (V)

Fig. 1.
 Gate

p+ n+ p+
Source LS LM LS Drain

n+ n+

Grain Boundary

Metal SiO2 Cry. Si Poly-Si

Fig. 2.
Central Barrier

Drain

Source

Fig. 3. (a)
Side Barriers

Central
Barrier

Fig. 3. (b)
 Central Barrier
Side Barriers

Fig. 3. (c)
 1E-5
1E-6
1E-7
1E-8
1E-9
Drain Current (Amp)

1E-10
1E-11
1E-12
1E-13
1E-14
1E-15
1E-16 L=LM+2LS=0.4μm C-SOI
VDS=0.01V C-TFT
1E-17
VCGS=0.52V TG-TFT
1E-18
-1 0 1 2 3
Gate Voltage (Volts)

Fig. 4.
 1E-5
L=LM+2LS=0.4μm
1E-6 VDS=0.01V
1E-7
1E-8
1E-9
Drain Current (Amp)

1E-10
1E-11
1E-12
1E-13
1E-14 C-TFT
1E-15 TG-TFT (φMsg=5.25eV)
TG-TFT (φMsg=5.15eV)
1E-16
TG-TFT (φMsg=5.05eV)
1E-17
TG-TFT (φMsg=4.95eV)
1E-18
-1 0 1 2 3

Gate Voltage (Volts)

Fig. 5.
 1E-5 VDS=0.01V
1E-6 LS=LM
1E-7
1E-8
1E-9
Drain Current (Amp)

1E-10
1E-11
1E-12 C-TFT (L=1μm)
C-TFT (L=0.6μm)
1E-13
C-TFT (L=0.4μm)
1E-14 C-TFT (L=0.3μm)
1E-15 TG-TFT (L=1μm)
1E-16 TG-TFT (L=0.6μm)
TG-TFT (L=0.4μm)
1E-17
TG-TFT (L=0.3μm)
1E-18
-1 0 1 2 3
Gate Voltage (Volts)

Fig. 6.
 1E-5 L=LM+2LS=0.4μm
1E-6 VDS=0.01V
1E-7
1E-8
1E-9
Drain Current (Amp)

13 -2
1E-10 C-TFT (NT=0.5x10 cm )
13 -2
1E-11 C-TFT (NT=10 cm )
13 -2
C-TFT (NT=2x10 cm )
1E-12 13 -2
C-TFT (NT=5x10 cm )
1E-13 14 -2
C-TFT (NT=10 cm )
1E-14 TG-TFT (NT=0.5x10 cm )
13 -2

13 -2
1E-15 TG-TFT (NT=10 cm )
13 -2
1E-16 TG-TFT (NT=2x10 cm )
13 -2
TG-TFT (NT=5x10 cm )
1E-17 14 -2
TG-TFT (NT=10 cm )
1E-18
-1 0 1 2 3
Gate Voltage (Volts)

Fig. 7.
 1E-5 L=LM+2LS=0.4μm
1E-6 V =0.01V
DS
1E-7
1E-8
1E-9
Drain Current (Amp)

1E-10
1E-11
1E-12
1E-13
C-TFT (T=300 K)
1E-14
C-TFT (T=350 K)
1E-15
C-TFT (T=400 K)
1E-16 TG-TFT (T=300 K)
1E-17 TG-TFT (T=350 K)
TG-TFT (T=400 K)
1E-18
-1 0 1 2 3
Gate Voltage (Volts)

Fig. 8.
 1E-5 VDS=0.01V
1E-6 L=2LS+LM=0.4μm
1E-7
1E-8
1E-9
Drain Current (Amp)

1E-10
1E-11
1E-12
1E-13 C-TFT (LS=0)
1E-14 TG-TFT (LS=LM)
1E-15 TG-TFT (LS=0.9LM)
1E-16
TG-TFT (LS=0.8LM)
TG-TFT (LS=0.7LM)
1E-17
TG-TFT (LS=0.6LM)
1E-18
-1 0 1 2 3
Gate Voltage (Volts)

Fig. 9.
 1E-5 VDS=0.01V
1E-6 L=2L +L =0.4μm
S M
1E-7 LS=LM
1E-8
1E-9
Drain Current (Amp)

1E-10
1E-11
1E-12
1E-13
C-TFT (g=20nm)
1E-14
C-TFT (g=40nm)
1E-15 C-TFT (g=60nm)
1E-16 TG-TFT (g=20nm)
1E-17
TG-TFT (g=40nm)
TG-TFT (g=60nm)
1E-18
-1 0 1 2 3
Gate Voltage (Volts)

Fig. 10.
 1E-5 VDS=0.01V
1E-6 L=2L +L =0.4μm
S M
1E-7 g=90nm
1E-8
1E-9
Drain Current (Amp)

1E-10
1E-11
1E-12
1E-13
1E-14
1E-15
1E-16 C-TFT (LS=0)
TG-TFT (LS=LM)
1E-17
TG-TFT (LS=0.5LM)
1E-18
-1 0 1 2 3
Gate Voltage (Volts)

Fig. 11.