Steps for CMOS Inverter layout design:-

1. Login to Xmanager3
2. Create a directory of layout by following these steps
[your name@mentor ~] $ cd work
[your name@mentor work] $ mkdir layout
[your name@mentor work] $ csh
[your name@mentor work] $ source homesoftwarecshrcams!""#$cshrc
[your name@mentor work] $ adk%ic
&hen '() is open
3. *pen a new layout
4. +ut name of of layout design,- Like inverter1
+rocess,-$A!"te#$nology"i#"pro#ess"a%i&'
.ules,- $A!"te#$nology"i#"pro#ess"a%i&'.rules
+ress O!
'. Layout editor window will appear on your screen
(. /elect /etup0'rid
1nd /et the grid coordinates accordingly
). 'o to )C palettes on right-bottom toolbar
/elect *dit+,-. 2for ruler selection it will help measuring dimensions of
layout3
/. 4ow from layer palette choose different layers$ 1n e5ample of first layer design is
here same step is following to drag the different layers with different dimensions
and positions$
/elect CO01AC121O2AC1I3* with path width of 2.&

4. Length of contact to acti6e !7 i$e$ /i8e of !9!
1&. /elect edit and flatten this block$ )f you want you can use this option at each stage
after design a block$
11. 4ow select :;&1L< of si8e =9=

12. Copy both block by selecting and paste by press C at a distance of >$"
13. ?raw AC1I3* block of si8e 1/54 and copy this block because these steps are
common for both pmos and nmos
14. 4ow for 4mos 2the lower one 3
?raw 0267-S2S*7*C1 of si8e 22513 and 628*77 of si8e 2(51)
1'. 4ow for +mos 2the upper one 3
?raw 6267-S2S*7*C1 of si8e 22513 and 628*77 of si8e 3&521
1(. 4ow draw a 6O79 link of width !$" between the pmos and nmos of same
distance i$e$ <$" from acti6e block
1). 4ow draw a M*1A721 link of width 3$" for right side for connecting acti6e of
both pmos and nmos
1/. 4ow draw a M*1A721 block of si8e <"9= for making output contacts and in the
same way for input draw block of <=9= according to figure
14. 4ow draw a M*1A721 block of width of 1&.& abo6e the +:*/ and below the
4:*/
2&. 4ow draw a M*1A722 block of si8e =9= according the figure 2> places37upper
and lower metal%! block should be abo6e and below of pmos and nmos
21. 4ow draw a M*1A721 block of width 3$" for connecting acti6e and metal%! of
pmos and nmos
22. 4ow draw a 6O79 block of si8e=9= at the input side
23. 4ow draw a 3IA block of si8e !9! for connecting metal%< and metal%!
according the figure 2> places3
24. 4ow draw a CO01AC121O26O79 block of si8e !9! for connecting metal%<
and poly according the figure 2< place3 at the input side
2'. press space on screen and type n:# for n-well contact and making contact of n-
well and metal%<$)n the same way type p:# for p-well contact$
2(. 'o to right bottom side IC26alettes select A!2*I1 and select M;6ort
for port declaration$ 1nd for 6iew port name select 6ort 1e<t

+ort type direction
@dd +ower )n
'nd +ower )n
@in /ignal )n
6out /ignal *ut

2). 'o to &ools0Calibre0.un ?.C 2Aor ?esign .ule Checking3
2/. Cancel .unset Aile +ath $ click on the rules and pro6ide the following path for
rules 2you can also browse by folder3
"$o%e"soft:are"=O-0,9"ad;321"te#$nology"i#"pro#ess"a%i&'.rules
24. ,un ,C
)n the abo6e e5ample we find no errors$ )f any error is found in layout according to
design rule you can click on that and correct the layout accordingly7 then sa6e the layout
and check for ?.C again until it found no errors$
3&. 1ools+Cali>re+,un 6*?
31. /et the rules
"$o%e"soft:are"=O-0,9"ad;321"te#$nology"i#"pro#ess"a%i&'.rules
32. *utput set to 7A9O-1 according to figure and finally ,un 6*?
33. *utput set to 7A9O-1 according to figure and finally ,un 6*?
1 +;X file is generated as shown in figure
34. &his is a pre generated file which used for arranging the position of @?? '4?
)4 and *(&
99999999999999999999999999999999999999
9 Aile, in6erter$pe5$netlist$sp
9 Created, Ari :ar <B <=,!",>! !"<!
9 +rogram CCalibre 5.CC
9 @ersion C6!"<"$<%3"$!>C
99999999999999999999999999999999999999
$L)D homesoftwareA*(4?.Eadk3%<technologyicmodelsami"=$mod
$temp !# 9 /et *perating temperature to !# degree celcius
$global @?? '4?
@A*.C;%%@?? @?? '4? dc =
$C*44;C& '4? "
$option post
99999999999999999999999999999999999999
9)4CL(?; C1L)D.; 4;&L)/&
99999999999999999999999999999999999999
$include Cin6erter$pe5$netlistC
99999999999999999999999999999999999999
91?? &*+ L;@;L /):(L1&)*4 4;&L)/&
99999999999999999999999999999999999999
X< '4? )4 @?? *(& )4@;.&;.
99999999999999999999999999999999999999
9 )4+(& /&):(L(/
99999999999999999999999999999999999999
@< )4 '4? pulse2" = !="n <n <n !="n =""n3
99999999999999999999999999999999999999
9 141LE/)/
99999999999999999999999999999999999999
$tran <"ns <"""ns
3'. .un the command on linu5 window
gedit in6erter<!$pe5$netlist
2put your design name in place of in6erter<!3
&he below screen will appear7 change the location in this file according to abo6e
pre-generated file$ 1nd for transient analysis add in this file
@< )4 '4? pulse2" = !="n <n <n !="n =""n3
3(. .un the command
g6im in6erter<!$pe5$netlist$sp
3). .un the command
eldo inverter12.pe<.netlist.sp
1nd gi6e command e@:ave in linu5 window
3/. +lot the @)4 and @*(&
&his process is of transient analysis$ Eou can do other analysis by gi6ing other inputs$
;5it the tool after completing the process$