FPGA Based Ultra Fast Signed Multiplier

Rajkumar Chinthala and Indra Gupta

Email:rajchpee@iitr.ernet.in,indrafee@iitr.ernet.in

Abstract implemented with significant savings in hardware

resources and has faster response compared to parallel
This paper presents hardware implementation of signed multiplier.
parallel signed multiplier and ultra fast signed
multiplier on FPGA using Verilog. Performance 2. Parallel signed multiplier
Comparison of both the developed multipliers is
carried out. Ultra fast signed multiplier is faster and The common multiplication method is to add and
utilises less resources of target device compared to shift. The same technique is applied in the functioning
parallel signed multiplier. The model for both the of parallel signed array multiplier. If the numbers of
multipliers is created and simulated in ISE foundation partial products to be added are more, then the speed of
design tool. the multiplier reduces and the number of slices utilized
on Field Programmable Gate Array increases. The
1. Introduction number of partial products to be added depends on the
operands size [6].
Multipliers, adders, multiplexers and memories are
the basic building blocks which are playing an
important role in today’s digital signal processing and
in almost all other applications. With advances in
technology multipliers are designed with high speed,
low power consumption and compact VLSI
implementation. If the multiplier which is the primary
element is faster than whole the process will be faster.
Implementation of multiplication can be done in many
ways but the general choice of industry is towards the Figure 1 Parallel signed multiplier
multiplier circuit which has high sped, compact and
consumes less power [1]. Considering a 4-bit parallel signed multiplier as
There are many ways of implementations of shown in Figure 1.This module contains multiplicand
multiplier circuits mentioned in the literature [2-4]. and multiplier are of 4 bit each. The product which will
Array multipliers and multipliers based on the result is of maximum of 8 bits. One bit sign signal is
modified Booth’s algorithm have been popular among used in the model to indicate whether it is signed
the different types of multipliers. In array multipliers, multiplication or unsigned multiplication. Both
partial products are generated by AND gate cells and positive and negative operands are to be properly sign
are added to give the product where as in case of extended whenever needed. When the multiplier or/and
multipliers based on the modified Booth’s algorithm, multiplier is/are negative, it is represented in signed 2's
three-bit strings of the multiplier are scanned and
complement; each 1 added in front due to the sign
appropriate operations are carried out on the
extension requires an addition of the multiplicand to
multiplicand [5].
the partial product. However, one only needs to
In this paper hardware implementation of ultra
consider enough bits to guarantee 8 bits required in the
fast multiplier is proposed and is compared with the
result. One bit ready signal is added to the module to
conventional parallel signed multiplier in respects of
indicate the busy status of the circuit. The model is
speed and device utilization. Comparison is based on
described in behavior level abstraction in Verilog.
the synthesis results obtained by synthesizing the
After the design entry in the ISE (Integrated Software
multipliers architecture towards Xilinx FPGA device.
Results denote that ultra fast signed multiplier is
Environment) design tool, the module to be designed
will look like Figure 2.
2.1. Simulation results

Simulation verifies the functionality of the circuit

that has to be implemented on the FPGA kit [4]. The
above circuit is simulated on ISIM (ISE simulator)
provided by the ISE (Integrated Software
Environment) foundation tool 10.1. Inputting
multiplier = 0;multiplicand = 0;sign = 0;clk = 0;#100;
multiplier = 4'hb;multiplicand = 4'he;sign = 1'b0;clk =
1'b1; in stimulus file yields following results shown in
Figure 3.
Figure 2 RTL schematic diagram of the
parallel signed multiplier

Figure 3 Simulation results of the parallel signed multiplier

2.2 Synthesis respectively. These reports are generated by the ISE

10.1(integrated software environment) design tool.
The target device for the synthesis of the above
mentioned circuit is Xilinx SPARTAN-3E FPGA Table 1 Timing report of parallel signed
board. There are two reports namely timing report and multiplier
Table 2 Device utilization report of parallel
Minimum period 6.271ns signed multiplier
Number of Utilization %Utilization
Minimum input arrival 3.739ns devices
time before clock Slices 40 out of 4656 0
Maximum output 6.059ns Slice Flip Flops 34 out of 9312 0
required time after 4 input LUTs 74 out of 9312 0
clock
IOs 19 -
device utilization report, which describes about the
synthesis of the circuit tabled in Table 1 and Table 2 bonded IOBs 19 out of 232 8
 GCLKs 1 out of 24 4 multiplicand and multiplier is of 4 bit each. The resultant
Number of 0 out of 20 0 product shall be of 8 bits.
BRAMs
The only disadvantage with this LUT based multiplier
is the memory requirement. The memory required
3. Ultra fast signed multiplier increases with the increase in size of multiplier and
multiplicand. After the design entry the module
In this multiplier, 256×8 ROM is used as look obtained is shown in Figure 5.
up table to store the result i.e., product of two 4-bit
operands namely multiplier and multiplicand. Here 4 bit
multiplier is considered although it can be of any size.
After fetching of the operands the circuit concatenates
two operands to give the address of memory location in
ROM containing desired result. So the product is just
one clock away.

Figure 5 RTL view of ultra fast signed

multiplier

3.1. Simulation results

. Considering same inputs which are applied for

Figure 4 Ultra fast signed multiplier
Ultra fast signed multiplier provides very fast result
and occupies less area of the target device comparatively
to parallel signed multiplier. This multiplier utilizes the
LUT (look up tables) to make the operation fast. Since
the retrieval of the data from the memory is the only
operation is has to do. The module of 4-bit Ultra fast
signed multiplier is shown in Figure 4 containing
parallel signed multiplier in the stimulus file of
ultrafast multiplier, the simulation results obtained are
shown in Figure 6.
3.2 Synthesis
For the same target device i.e., FPGA, synthesis
of the ultra fast multiplier is carried out. The synthesis
report is tabled in Table 3 and Table 4.
Figure 6 Simulation results of ultra fast signed multiplier.
 Table 3 Device Measures”, [5] Sunder S.
utilization report of Ultra fast signed IEEE Kidambi,
ufm multiplier takes only one International Fayez El-
Number of clock pulse i.e., 0.144ns
Utilization Conference on Guibaly, and
devices to give the result where Microelectroni Andreas
Slices 0 out ofas 4656
the parallel multiplier cs, Antoniou,
takes 6.059ns after the Te “Area efficient
Slice Flip Flops 0 out ofclock
9312 pulse. In many hr Multipliers for
4 input LUTs 0 out ofdigital
9312 signal processing an Digital Signal
applications, there are Processing
IOs Oct.31-Nov2,
many tasks which need Applications”,
Bonded IOBs 17 out of 2 2000,pp.75-80.
repeated multiplication; IEEE
[2] Michael A.
GCLKs 1 out ofif 24 the conventional
Soderstrand,
International
multipliers are replaced Conference on
Number of 1 out ofwith20 “Csd
ultra fast Circuits and
BRAMs Multipliers For
multipliers then fastness Systems,1996.
Fpga Dsp
of whole circuit can be [6] Rizwan
Table 4 Timing Applications”,
improved. Mudassir, H.
report of ufm IEEE
Device utilization El-Razouk and
Minimum period 0 reports of the two International
Z. Abid, ” New
Conference on
Minimum input arrival 0 multipliers presented in Designs of
Circuits and
time before clock Table1 and Table 3 Signed
Systems,
Maximum output 0 shows that Ultra fast mulltipliers”,
2003,pp. v-
required time after clock signed multiplier utilizes IEEE
469-v-472.
less resources on FPGA International
[3] Xiaohui
4. compared to the parallel Conference on
Yang ,Zibin
Conclusi multiplier. The only Circuits and
Dai , Xuerong
disadvantage with this Systems,2005,p
on kind of implementation
Yu , Jinhai
p. 259-262.
Su,“A Design
of multiplier is the
The two proposed of General
memory requirement. Rajkumar chinthala is
multipliers namely Multiplier in
Memory requirement pursuing M.tech in the
parallel signed GF_28_and
increases with the size specialization of System
multiplier and ultra fast FPGA
of multiplier and Engineering and
signed multiplier are Implementation
multiplicand. With the Operations Research in
designed and ”,IEEE
increase in size of the Electrical
implemented on the International
operand by one bit the Engineering Department
SPARTAN 3-E FPGA Symposium on
memory requirement of Indian Institute of
kit. By the timing Pervasive
increases by 4 times. Technology Roorkee,
reports of two Computing and
India. Previously he was
multipliers presented in Applications,20
the Table 5 it is clear 5. References 06,pp.503-507.
with Bharath Sanchar
Nigam Limted as
that ultra fast signed [4] S. Shah, A.J.
[1] S.Shah, A. J. Telecom Technical
multiplier is 43 times Al-khabb,
A-Khabb, D. Assistant for 5 years.
faster than the parallel “Comparision
AI-Khabb, His area of interests
multiplier. of 32-bit
“Comparison includes VLSI design,
Multipliers for
Process Control
Parallel signed Ultra fast Various
applications and Online
multiplier multiplier Performance
Control Applications.
Maximum time Measures”,
Indra Gupta is working
required to get 6.203ns 0.144ns IEEE
as an Associate
output International
professor in the
Conference on
of 32-bit Electrical Engineering
Microelectroni
Table 5 Comparison Multipliers for Department of Indian
cs,2000,pp.75-
of parallel multiplier Various Institute of Technology
80.
and ufm. Performance Roorkee, India. She
completed her Ph.D.
from I.I.T. Roorkee, in Control Applications,
year 1996. She has Microprocessor
published many papers Applications, ANN,
in reputed journals so Online Control
far. Her area of interests Applications and VLSI
includes Power System, design.
Simulation, Process