ABSTRACT

Very - Large-scale integration (VLSI) is the process of creating integrated circuits by

combining thousands of transistor-based circuits into a single chip. VLSI began in the
1970s when complex semiconductor and communication technologies were being
developed.

The first semiconductor chips held one transistor each. Subsequent advances added
more and more transistors, and as a consequence more individual functions or systems
were integrated over time. The microprocessor is a VLSI device.

The first "generation" of computers relied on vaccume tubes. Then came discrete
semiconductor devices, followed by integrated circuits. The first Small-Scale Integration
(SSI) ICs had small number of devicews on a single chip - diodes, transistors, resistors
and capacitors (no inductors though), making it possible to fabricate on or more logic
gates on a single device. The fourth generation consisted of Large-Scale Integration
(LSI), i.e., systems with at least a thousand logic gates. The natural successor to LSI was
VLSI (many tens of thousands of gates on a single chip). Current technology has moved
far past this mark and today's microprocessors have many millions of gates and hundreds
of millions of individual transistors.

As of mid-2006, billion-transistor processors are just on the horizon, with the first being
Intel's Montecito Itanium Server. This is expected to become more commonplace as
semiconductor fabrication moves from the current generation of 90 nanometer (90mm)
processes to the next 65mm and 45mm generations.

At one time, there was an effort to name and calibrate various levels of large-scale
integration above VLSI. Terms like Ultra-large-scale Integration (ULSI) were used.
But the huge number of gates and transistors available on common devices has rendered
such fine distinctions moot. Terms suggesting more than - VLSI levels of integration are
no longer in widespread use. Even VLSI is now somewhat quaint, given the common
assumption that all microprocessors are VLSI or better.
VLSI DESIGN :

Up until the 1950s, electronic active device technology was dominated by the
vaccume tube and, although a measure of miniaterization and circuit integration did
take place, the technology did not lend itself to miniaterization as we have come to
accept it today. Thus the vast majority of present day electronics is the result of the
invention of the transistor in 1947.

The invention of transistor by William B. Shockley, Walter H. Brattain & John

Bardeen of bell Tellphone laboratories was followed by the development of the IC. The
first IC emersed at the beginning of 1960 and since that time there have already been
four generations of ICS: SSI, MSI, LSI, VLSI. Now we are beginning to see the emergence
of the fifth generation, ULSI (Ultra Large Scale Integration). Which is charactirized by
complexities in excess of 3 million devices on a singleIC chip.

The complexity and capability of present day VLSI technology is entraordinary,

but current design techniques are still inadequate to meet all the challenges of VLSI
Techniques that may be satisfactory for high-volume applications will not be financially
competitive for small custom jobs, and future increases in the no. of active devices per
chip require highly refined and sophisticated approaches.

CAD:

To active the full potential of VLSI technology it is necessary to develop and use
computer aids that provide significant assistance in the design and analysis of complex
VLSI systems.

Computer aided design approaches make use of cell libraries consisting of tested
and debugged FE & BJT circuits. Conventional CAD systems use grphic design tools to
capture, edit and o/p the detailed physical description of the IC mask in a form that the
fabrication house can use. Captuting the physical, structural and behavioural of a VLSI
CKT is vital to correct design.

Important Points of VLSI technology:

Scalability: VLSI is a rapidly changing technology and the goal is to designchips in a
manner that facilitates the transition to small lay outs and more complex in the future.
Testability Enhancement: One of the most important steps in VLSI design is the
incorporation of measures to enhance testability. The ratio rate behind measures is to
provide circuit by that is well behaved.

Chip Regulation: A major problem at present is the devising of new design techniques
and methods to make the rapidly changing VLSI technology widely usable by the
electronics industry. Design methods have not always kept pace with the increased on -
chip complexity the technology is capable of, and it keeps taking more time and effort
to design, debug, and bring a complex VLSI system to production.

The major benefit of designing VLSI with regular structures is a decrease in lay
out time & effort, because the use of regular structures reduces the total no. of devices
that must be individually drawn and easier to debug. A measure of the effectiveness of
regular structuring in reducing lay out time cn be obtained by defining chip
resoluarization.

We willl start our study of VLSI design by learning about transistors and wires and
how they are fabricated. The basic properties of transistors are clearly important for
lagic design going beyond a minimally - functional logic circuit to a high performance
design requiry the consideration of paragitic ircuit elements (R, C).

Design Style:

System Specifications

Black Level

RTL Design
VLSI Design
Gate Level Design

CKT LEvel Design

Layout

Fabrication
VLSI Technology
Packaging
Silicon Planner Process:

The basic steps which are similar for fabricating any device on a silicon plane are
called Silicon Planner Process.

Silicon Water:

The basic material for fabricating any device is a Silicon wafer. These are circular
in shape. With the diameter equal to either 2", 4", 12", 20". Currently available maximum
diameter size is 12"-20" = 50 cm and the thicknes is in the c... of mm.

Raw material for preparing wafer is sand. From sand we prepare MGS (Metallurgical
Grade Silicon), from MGS we prepare EGS (Electrical Grade Silicon). This EGS is molten
at high temperature with in a cruicible at higher than the silicon molten temperature i.e.
(> 1420 0C), with the help of seed crystal.

The seed crystal and crucible are rotated in opposite directions inorder to produce
ingots of circular crossection with the help of seed crystal, by pull up process the molten
silicon crystal from the crusible and cooled it to form a solid Si.

Seed Crystal
Neck
Ingot

Cruicible

Epitaxial Growth:

The word epitaxi is derived from greek Epi means upon and taxy means orderly
formation. Therefore epitaxial means orderly formation of layers.

In old days the wafers are does not have required thickness, to improve the
thickness of the wafers, epitaxial growth is used. In this technique we are added impurities
to a certain level. This layer is known as epitaxi layer.
n-type epitaxy epitaxy
P - enlarged die

die
 So that the resulting layer is an extension of substract crystal structure. The basical
chemical reaction used for the epitaxial growth of pure silicon is the hydrogen reduction
of silicon tetrachloride.
1200 0C
SiCl4 + 2H2 Si + 4HCl

This process is carried out in a reaction chamber consisting of a long cylindrical

quartz tube encircled by RF induction coil.

Oxidation:

It is an important step in IC technology. It is used as a barrier for diffusing impurities

in unwanted areas.

It act as an isolation layer among devices.

It act as a passivation layer to prevent reaction with invironment.

A seperation between channel and gate terminal in MOSFET.

Dry Oxidation: Only O2 atoms are source gas.

1100 0C
Si + O2 SiO2

Wet Oxidation: H2O (Water) molecules are source gas.

1100 0C
Si + 2H2O SiO2 + 2H2

This Oxidation is called thermal oxidation because high temperature is used to

grow the oxide layer.

Photolithography: It involves two processes namely

i) Photographic mask.

ii) Photo etching.

It is the heart of the integrated circuit fabrication technology. In these we create

windows known as masks and which are placed on die for creating windows for diffusing
impurity areas.

The following steps are followed for photolithographic process.

Step a): Take die

Substrate

Step b): To cover entire surface of substant with SiO2 SiO2

Substrate
Step c): Apply photo resistance on the entire surface of the wafer upon SiO2 layer.
Photo Resistance
SiO2
Substrate
Step d): Prepare mask (window) and place it on top of the PR
Window

Photo Resistance
SiO2
Substrate
Step e): Expose the UV rays through the mask.
Window
UV - Rays
Photo Resistance
SiO2
Substrate

i) +Ve PR: In this exposed (UV rays) portion sof PR is washed away and the unexposed PR
is remains. Window

Photo Resistance
SiO2
Substrate

ii) - Ve PR: Un exposed portions of PR is washed away and exposed PR is remains present.
So we have another models like eptical - lithography, Non-optical lithography, electron-
lithography, Ion-lithography and X-Ray lithography.
Photo Resistance
SiO2
Substrate

Diffusion: This is the process of adding impurities to the die, in this process the die is
exposed to gaseous form of impurity atoms. Boron for p-type and phosphorous for n-
type.
Ion implantation: It is another technique used to introduce (add) impurities into a
silicon wafer. In this energy is used to diffuse the impurities instead of raising the
temperature. It has two important advantages.

i) It is performed at low temperature.

ii) In diffusion process, temperature has to be controlled over a large area where as in
ion implantation technique accelerating potential and the beam current are electrically
controlled from outside. This is for depletion mas.

Isolation Techniques: Since a no. of components are fabricated on the same IC chip,
it becomes necessary to provide electrical isolation between different components and
interconnections.

Various types of isolation techniques have been developed. Here we discuss only
two. Commonly used techniques namely

a) P-n Junction isolation

b) Dielectric isolation (oxide isolation)

a) P-n Junction Isolation: In this isolation technique, P+ type impurities are selectively
diffused into n-type epitaxial layer so as to reach p-type substrate as shown by the
figure.
n-epitaxy P+ n-epitaxy P+ n-epitaxy P+ n-epitaxy
Substrate

It produces islands surrended by p-type.

b) Dielectric or (Oxide isolation):

Here a layer of solid dielectric such as SiO2, there by producing isolation, both
electrical and physical.

Metalisation: This is the process of taking connections to the outside world.

The purpose of this process is to produce a thin metal film layer that will serve to
make interconnections of the various components on the chip. Alluminium is usually
used for metalisation of most ICs. It offers several advantages.
 It is relatively a good conductor.

It is easy to deposit Alluminium (Al) film using vaccum deposition.

Al makes good mechanical bonds with Si.

Al forms low resistance, non-rectifying contacts with P-type Silicon and the heavily
doped n-type Silicon.

Packaging: Each of the wafer processed contains several hundred chips, each being a
complete circuit. So, these chips must be seperated and individually packaged. There
are three different package configurations available.

The different package configurations are

1) -5 glass metal package

2) Ceramic flat package.

3) DIP (Dual-Inline-Package)

Example: The following Si planner process steps are using for the fabrication of nMOS
technology.

Silicon wafer Preperation: A thin wafer cut from a single crystal of Si of high purity
into which the required P-impurities are introduced as the crystal is grown (Crystal
Growth). ○

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Such wafers are critically 75-150 mm in the diameter and thickness is 0.4 mm
and are dopped with boron to impurity concentrations of 1015/cm3 to 1016/cm3, giving
resistivity in the approximate range 25 cm to 2 cm

Note: For P-type substrate dopped with Boron.

For n-type substrate dopped with Phosphorous.

Epitaxial growth: It improves the thickness or the substrate. If the substrate having
not required thickness resulting it extends the substrate.
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Oxidation: A layer of SiO2, typically ... thick, is grown allover the surface of the wafer to
protect the surface. It act as a

Barrier to doppers during processing.

Insulating layer, on to which other layers may be deposited and patterned.

It acts as passivation layer, it avoids the reaction b/w substrate and environment.

Photolithography:

Photographic mask: The entire surface is covered with

a PR which is deposited on to the wafer to achive on
SiO2 }1um
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even distribution of required thickness. P

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The PR (Photo resistive) layer is then exposed to

UV light through a mask which defines those regions PR

into which diffusion is to take place together SiO2 }1um

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with transistor channels.

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Ex: These areas exposed to UV radiation are polimerised (hardened). But that the areas
required for diffusion are shielded by the mask and remain uneffected.

Photo etching: UV
Rays

These areas are subsequently readily etched away Mask

PR
together with the underline SiO2. So, that the wafer
surface is exposed in the window defined by the mask.
SiO2 }1um
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Diffusion and Ion implantation: A thin layer of SiO2 (1un) means a thin layer of SiO2
is grown over the entire chip surface and then polysilicon is deposited on top of these to
form the gate structure. The polysilicon layer consists of heavily dopped polysilicon
deposited by chemical vapour deposition (CVD).
In the fabrication of fine pattern device,
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precise control of thickness, impurity concentration,

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and resistivity is necessary.

Polysilicon
123456789
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123456789 SiO2
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Further PR coating and masking allows the polysilicon 123456789
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to be patterned (in step 7). And the thin oxide is removed 12345678
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12345678 diffusion
(1um
to expose areas into which n-type impurities are to be deep)
P
diffused to form the sand D. Diffusion is achieved by
heating the wafer to a high temperature and passing a gas containing the designed n-
type impurity (Phosphorous) over the surface as shown in figure.

Isolation Technique: Since a no. of components are fabricated on the same IC chip, it
becomes necessary to provide electrical isolation between different components and
interconnect various types of isolation techniques have been developed they are P-n
junction isolation and dielectric isolation.

Packaging and Testing: Each of the wafer processed contains several hundred chips,
each being a complete circuit. So these chips must be seperated and then they are
individually packaged.

The information of how materializing design circuit designs in Si. Design process
are aided by simple concepts such as Stick diagram and layout (Symbolic) diagram.
The key role is a set of Design rules.

MOS layers: MOS Circuits are formed on four basic layer

1. N-diffusion layer

2. P-diffusion layer

3. Poly Silicon

4. Metal

The above layers are isolated from one nother by thick or thin silicon dioxide
insulating layers.

In some process ther may be a second metal layer and also, in some process, a
second poly silicon layer is used.

Layers may be hoincd to geather where contacts are formed.

Stick Diagram : Stick diagrames may be used to convey layer information through the
use of a colour code.

Ex:- The layout of N-Mos encoding scheme.

N-Diffusion Green

Polysilicon Red

Metal Blue

Implantation layer Yellow

Contact cuts Black or Brown

Component Colour Resistance Use

Metal1 Blue Low Power & Signal Wires

Metal 2 Purple Vely low Power & Signal Wires
Poly Silicon RED Low Transistor Gates and
signal wires
n-type diffusion Green amedium Signal Wires S & D
of transistors
P-type diffusion Yellow medium For the formation of
S & D of transistors
Contact cut black Black Very low Signal Connection
Via Very low Connecting b/ w
metal layers
Conclusion:

The information how materializing design circuit designs in Si. Design process
are aided by simple comcepts such as stick diagram and layout diagram. The kay role
is a set of Design rules. Following the above diagrams are on design any type of MOS
transistor by using VLSI design. And built no. of components on the single IC chip (Si).

By
VADLAMUDI SYAM BABU, III B-Tech (ECE),
Malineni Laxmaiah Engineering College,
SINGARAYAKONDA.
E-mail: inkbottle117@yahoo.co.in