1426 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO.

6, DECEMBER 1988

A 50-Mbit/s CMOS Monolithic

Optical Receiver
DAVID M. PIETRUSZYNSKI, MEMBER, IEEE, JOHN M. STEININGER, MEMBER, IEEE,
AND ERIC J. SWANSON, MEMBER, IEEE

Abstract -A general-purpose CMOS optical receiver that operates at
data rates from 1 to 50 Mbits/s has been fabricated in a 1.75-pm CMOS
process. The technology choice resulted in a high level of integration
compared with similar bipolar technology receivers. The measured mini-
mum signal current for a bit error rate (BER) at 50 Mbits/s is
48-nA rms. Automatic gain control (AGC) gives the receiver an electrical
input dynamic range of greater than 60 dB.The outputs are 'ITL compati-
ble and the chip dissipates less than 500 mW when switching at maximum
speed. The die area is 16 mm2. A comprehensive noise analysis of the
receiver front end provides insight into the design trade-offs of optical
receiver preamplifiers. A wide-band precision amplifier used in the linear
channel is discussed in detail. Finally, we describe a simple method for
recovering low-frequency signal information lost in ac coupling.
The discussion of t h s analog LSI receiver begins with
an overview of the technology and the circuit architecture.
A brief outline of thermal noise constraints on the design
of a simple MOS preamplifier follows. The entire circuit is
discused in more detail in separate sections describing the
preamplifier, linear channel, decision circuit, and auto-
matic gain control (AGC). Finally, the measured perfor-
mance on this data link is presented and discussed.
11. OVERVIEW

This receiver was fabricated in a 1.75-pm twin-tub dou-

I. INTRODUCTION ble-poly CMOS technology [5]. The top level of polysilicon
is silicided to achieve low sheet resistance and is used for
A NALOG LSI technology makes possible a new gen-
eration of single-chip optical data links where the
integrated circuit and the optical transducer can be housed
gates and nonsensitive interconnection. The lower level of
polysilicon is used primarily as the bottom plate of the
high-quality double-poly capacitors. The speed of this
in a single compact package. T h s new generation of mono-
technology can be characterized by an f, measurement of
lithic receivers requires no external components and
the n- and p-channel devices. Given a supply constraint of
can achieve high sensitivity and wide dynamic range with
+ 5 V, we have chosen the maximum practical gate-to-
logic-compatible outputs [l].In t h s paper we describe a
source voltage for a transistor in the signal path to be 2 V
1-50-Mbit/s CMOS optical receiver integrated circuit with
above the threshold of the device. In this bias condition
TTL-compatible outputs designed for a general-purpose
the f, of an n-channel device of minimum channel length is
optical data link.
greater than 2.5 GHz and the p-channel f, is about 1 GHz.
Because of the wide bandwidth and the h g h gain neces-
The f, of the device, as in bipolar transistors, is defined as
sary for sensitive data links, the optical receivers of the
the frequency at which the ac gate current is equal to the
past were fabricated in a high-speed bipolar technology
ac drain current.
[2]-[4]. Today, the device performance of fine-line MOS
CMOS technology offers some less obvious features that
technology makes the development of wide-band receivers
were exploited in the design of this receiver. For instance,
possible. Although strictly an analog device, the use of
the transimpedance preamplifier uses a resistively biased
CMOS allows a higher level of integration in this receiver
n-channel MOS device as the feedback element [6]. This
by removing external components normally used for ac
long-channel device combines high resistance with a low
coupling. Independent of the choice of technology, these
wide-bandwidth, high-gain receivers present a formidable shunt capacitance that eases the realization of a stable,
wide-band amplifier. Furthermore, long time-constant in-
isolation problem. Attention must be given to stray capaci-
tegrators and slowly decaying peak detectors used for
tance both on the integrated circuit and in the package
AGC are easily achieved. The combination of resistive
because of coupling from output to input, from the power
devices, high-impedance nodes, and double-poly capacitors
supply, and from the substrate.
with low parasitic capacitance to substrate permits on-chip
ac coupling between gain stages.
Manuscript received February 9, 1988; revised May 24, 1988. Fig. 1 shows a block diagram of the receiver. Signal
D. M. Pietruszynski and J. M. Steininger are with AT&T Bell Labora-
tories, Reading, PA 19612. current from the off-chip p-i-n diode optical detector flows
E. J. Swanson is with Crystal Semiconductor Corporation, Austin, TX into the preamplifier input. The transimpedance amplifier
78744.
IEEE Log Number 8823894. converts this signal current to an output voltage. Following

0018-9200/88/1200-1426$01.00 01988 IEEE

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 PIETRUSZYNSKI ef U/. : SO-MBIT/S CMOS MONOLITHIC OPTICAL RECEIVER 1427

qy/ry(*
PROCESSOR PROCESSOR
OUTPUT

Fig. 1. Block diagram of the optical receiver

-
-
~

-
the preamplifier is the linear channel which consists of a -

variable-gain amplifier under AGC control, and a postam- (b)

plifier that provides the additional voltage gain necessary Fig. 2. Simplified block diagram. (a) Ideal noiseless case. (b) With noise
generators added.
for the decision circuit to operate. The signal is then ac
coupled to the decision circuit to eliminate any potential
pulse-width distortion caused by the dc offset in the linear be
channel. The decision circuit consists of a hgh-speed com-
parator with low-frequency restore feedback circuit to
allow ac coupling in the linear channel. Two AGC loops
are used in this design. The first AGC loop limits the ' (l+A)
signal at the output of the preamplifier to withn the linear
range of its output stage, while the second AGC loop where
guarantees that the signal at the input of the decision CTr, = 'C
circuit is a constant value. Both AGC loops peak detect
7
the signal and compare the resulting voltage to a dc ~-
reference through an integrator with a large time constant. (1+ A ) - ' C A
In the preamplifier AGC loop, this control signal biases a
resistive MOS device that shunts excess signal current and
from the input, lowering the preamplifier transimpedance. A
The linear channel AGC loop controls the variable-gain --
(1+A) -A,
amplifier. Together these two loops provide almost 60 dB
of dynamic range without compromising the integrity of Equivalent thermal noise generators are added in Fig. 2(b).
the pulse width at the input of the decision circuit. Follow- The output noise is
ing the decision circuit are large CMOS output buffers
designed to drive TTL loads directly. A mute processor vout =---.Af { e , ( l + s7) - e , } .
detects the absence of signal and can be used to disable the 1+ STA
output buffers.
Equations (1)and (2) can be combined to yield the equiva-
lent input noise current ieq:

DESIGN
111. PREAMPLIFIER ANALYSIS
AND NOISE i,,=e,gf(1+sC,)+efg/=sC:,e,+g,(e,+e,) (3)

The preamplifier is the circuit that limits the sensitivity where sf =I/,.,. The Sources e , and e, are uncorrelated,
of the rsceiver, thus it is necessary to review the limitations and >> e,. linear channels typically limit the
that thermal noise imposes on the design [71. Here we noise bandwidth to 2fb/3, where f h is the maximum data
develop a noise model for a transimpedance amplifier rate. Integrating Over ths bandwidth yields
which consists of n identical cascaded gain stages. A
simplified block diagram of the amplifier is shown in Fig.
2(a). Here ii, is the signal current generated by the
J:/*/3izqdf = J2fb/3ea(2rf)2C:df
0
+ J2fb/3ejgjdf
0
reverse-biased off-chip p-i-n diode detector, C, is the total 2
=ei-r
32 fbCT2 +
2 3
.&$7 fh.
capacitance at the preamp input (the sum of the p-i-n (4)
81
diode and preamp input capacitances), and r, is the feed-
back resistance. The transfer function of this amplifier will The second term in (4)is the feedback resistor's contribu-

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 1428 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 6, DECEMBER 1988

tion to the noise. Of course, VDD

0 -

- 1 1 1
MOSFET VARIABLE
e; = 4kTrf. (5)
For optimal noise performance, rf must be kept as large as
possible. The maximum value of rf is determined by
bandwidth and stability requirements as shown below.
Assuming identical gain stages in the forward amplifier
and single pole response for each stage, the overall voltage
gain is

GND
0
MOSFET FEEDBACK
(6) RESISTOR
%*IN
gm
CELL
1+-
(a)
RDS12
Amplifiers in the linear channel will limit the overall
bandwidth of the receiver, therefore the minimum band-
width of the preamplifier must be at least f b . The closed-
loop bandwidth requirement is

Further, for adequate phase margn, the phase shift at f!

must be less than 45". Thus
-
-
(b)
Fig. 3. Preamplifier. (a) Complete schematic. (b) Simplified block dia-
gram with transimpedance reducing resistor.
We define the parameter f , as the maximum gain-band-
width product of a single loaded gain stage given by
noise contributions. Thus
f ,= Aofo. (9) - 8 1
The parameter f , is the technology speed indicator and it
reflects the fact that an increase in gain per stage comes at Substituting (13) into (12) gives
the expense of bandwidth. Equations (8) and (9) yield

f,
A,=-tan-. I?
(10)
fb 4n
This equation shows that as A, increases, the noise contri-
Further, (7) and (10) can be combined to give the maxi- bution from devices other than the input devices decreases.
mum transimpedance for a technology: Finally, substituting ( 5 ) and (14) into (4) produces the

rf =
[itan 4" comprehensive noise equation

?TfbCT '

With a cascade of identical gain stages and e:, repre-

senting the noise power of a single stage, where
fP 77

- -
e:=e:,( 1+ A
1
2+ +q.
A?-2 (12)
A,

One assumption made in this analysis is that the gain

= - tan

characteristic is constant over the entire linear channel

fh
-.
4n

The complete preamplifier schematic is shown in Fig. 3(a). bandwidth. In a multiple pole network where n > 1, peak-
For the FET gain cell consisting of devices M 7 - M 9 we ing in the preamplifier response can occur at high frequen-
include both input device ( M 7 ) and load device ( M 8 ) cies. In this case it appears that ( 1 5 ) is no longer valid

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PIETRUSZYNSKI el al. : So-MBIT/S CMOS MONOLITSIC OPTICAL RECEIVER
1429

T P h M W R E S I S TFEEDBACK
O R

CONTROL

Fig. 5. Circuit for minimizing temperature dependence of preamplifier

10-9 transimpedance.
lMIN C h i

Fig. 4. Noise current versus ,/ for one, three, and five gain stages.

since the gain now varies with frequency. Most of the noise
power is contained in the frequency band where the peak-
OUTP
ing occurs. However, to attain the maximum bandwidth OUTN

for a receiver in a given technology, the linear channel gain

stages following the preamplifier will typically band-limit
the response below the peaking frequency. Thus the flat
gain approximation is valid. Equation (15) can be used to
determine the number of gain stages necessary for the
minimum input-referred noise current. For example, a
receiver with fb = 50 MHz, C, = 3 pF, gm =1E-2 S, and
fp = 500 MHz has an rms input noise current that is equal
to 6 nA. Fig. 4 is a plot of input rms noise current versus fp
with one, three, or five gain stages ( n is odd for negative
feedback). Three gain stages give the minimum noise when
f p = 500 MHz. A faster technology with higher f, will
result in decreased input noise current. This theory agrees
with sensitivity measurements made on the actual receiver.
The preamplifier gain stage consists of a p-channel
current source supplying a common-source amplifier with
a folded n-channel load. Feedback ensures that the gate-
to-source voltages of both M7 and M8 are equal. Thus the
current split is determined by
The stage gain is given by
Fig. 3(a) shows the three cascaded gain stages and the
device M16 which is controlled by the AGC voltage [SI.
M16 is normally off until the input current to the pream-
plifier causes the output stage to exceed its linear range. At
this point M16 begins to shunt current away from the
feedback resistor and into the first stage output. This
circuit operation is illustrated in Fig. 3(b) where the trans-
IN -
-
Fig. 6 . Variable-gain amplifier.
impedance of the preamplifier with the AGC device on is
V,", 1
-=
l+Ao 1+Ai .
1 in ----
A03RDS16 AiRDS12
This AGC technique results in an increase of the preampli-
fier bandwidth when the input signal power is increased.
Although the noise bandwidth is increased when the AGC
circuit is functioning, and RDSl6 adds its own thermal
noise to the circuit, the signal-to-noiseratio is greater than
that required for a l o p 9 bit error rate (BER). The AGC
device is turned off and does not add noise when the signal
level approaches the sensitivity limit. The gate voltage of
device M12 is derived from the circuit shown in Fig. 5.
T h s circuit minimizes the temperature and power supply
dependence of the feedback resistance. A temperature-
independent constant dc current I, is passed through the
resistive device M14 identical to M12 in the preamplifier
circuit. The voltage source V I , is equal to the quiescent
voltage at the input to the preamplifier. The operational
amplifier A, with M15 and R , generates a current VB,/R,
which is fed to A , as shown. V,, is a bandgap-derived
voltage that is independent of temperature. This sets the
 1430
drain voltage of M14 at
The amplifier A , whose output voltage controls the gate of
M14 forces the source voltage to be VI,. Thus
If M14 and M12 are perfectly matched, the preamplifier
transimpedance is
IV. LINEARCHANNEL
CIRCUITRY
The preamplifier single-ended output is converted to a
fully differential form at the input to the linear channel.
This channel provides a gain controlled by a second inde-
pendent AGC loop, and it also provides the necessary
noise band-limiting. Dynamic range is limited throughout
the channel, hence the need for the second AGC loop to
ensure that the signal is a constant amplitude at the
channel output. The first block, namely the variable-gain
amplifier (Fig. 6), produces a signal amplitude that is
independent of the receiver input level. With the AGC
voltage held low, the gain is gm1/gm8.As the control
voltage increases, M5, M6, M9, and M10 reduce the gain
by a current diversion technique. This technique is achieved
by a cross-coupling arrangement, which keeps the quies-
cent current constant, assuring that g,, and gmll are
independent of the AGC voltage. The attenuation can be
varied from 0 to -40 dB.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 6 , DECEMBER 1988
The postamplifier (Fig. 7 )which follows the variable-gain
amplifier provides another 35 dB of gain. The input volt-
age is converted to a current by the input differential pair
( M l , M2). The current mirrors provide current gains that
are precisely controlled by ratioing device geometries. The
amplified signal current is converted back to a voltage
output in the last stage of the amplifier through the
diode-connected load devices MLOADl and MLOAD2.
Total voltage gain through the amplifier is given by
Since the current mirrors will multiply the dc bias current
as well as the signal current, interstage dc current subtrac-
tion (11- 14) is performed as shown. T h s technique pre-
vents excessive power dissipation yet enables a wide-band
signal current gain. Cascode devices M25, M26, M31,
M32, M37, and M38 are biased such that the output
devices of each mirror have the same dc drain-to-source
voltages as the input devices, thereby maintaining gain
precision. A requirement in the design of the preamplifier
and the linear channel was that a precise overall transim-
pedance be maintained over all processing, temperature,
and supply variations. T h s is achieved by controlling the
transimpedance of the preamplifier as well as the gain in
the postamplifier in a temperature- and process-indepen-
dent fashion. The technique used for loss of signal detec-
tion dictates the gain accuracy requirement. The loss-
of-signal detector checks for a situation in whch the
maximum gain available in both the preamplifier and the
postamplifier (with the variable gain amplifier at its maxi-
mum gain of 0 dB) is insufficient for maintaining a mini-
mum signal level at the input to the decision circuit.
 PIETRUSZYNSKI et d.: 50-MBIT/S CMOS MONOLITHIC OPTICAL RECEIVER 1431

VDD

z l PREAMP ATTENUATOR POSTAMP COMPARATOR

POSITIVE
PEAK
DETECTOR
w

NEGATIVE
PEAK
DETECTOR

- -
PEAK
COMPARE DIFFERENCE BUFFER
INTEGRATE AMPLIFIER DETECTORS

Fig. 9. Linear channel AGC loop.

tor output drives the AGC line in the variable-gain ampli-

fier circuit that was described in Section IV. This AGC
loop ensures that a constant signal voltage is fed to the
FREQUENCY
decision circuit independent of the input signal level. Opti-
(b) mum jitter performance is obtained by keeping this signal
Fig. 8. Comparator with quantized feedback. (a) Circuit. (b) Frequency
response. constant. The output of the integrator is also used to drive
the mute processor circuit which detects loss of signal to
the receiver. If the integrator output goes low, the linear
V. DECISION
CIRCUIT
channel is operating at its maximum gain, however the
The decision circuit is a comparator coupled with a peak-detected comparator input signal is greater than V,,.
quantized feedback circuit [9]. The ac coupling capacitors Therefore the mute processor flag indicates that the re-
shown in Fig. 1 are essential to avoid amplifier saturation ceiver input signal is lost. This circuit also shuts down both
because of dc offset accumulated in the postamplifier. The the comparator in the decision circuit and the digital
loss of low-frequency response in the signal path must be output buffers. The preamplifier AGC loop performs in
restored if the decision circuit is to operate correctly in the the same manner except that its purpose is to limit the
presence of long strings of consecutive ONE’S or ZERO’S in signal at the preamp output stage. Many preamplifiers will
pseudorandom bit patterns. Quantized feedback restores saturate with high input power commonly encountered in
the low-frequency information via positive feedback. A short loops. In the preamplifier design t h s problem is
simplified view of the circuit is shown in Fig. 8(a). The avoided by shunting the excess signal current away from
low-pass-filtered comparator output is added to the high- the first stage of the preamplifier. As discussed in Section
pass-filtered linear channel output to produce a properly 111, the AGC output voltage turns on the shunt device
equalized comparator input signal. The summing of the (M16 in Fig. 3(a)) when the preamp output stage ap-
signals can best be illustrated in the frequency domain as proaches the nonlinear region. Overall, these two AGC
in Fig. 8(b). Here the fed-forward signal (linear channel loops allow greater than 60 dB of input dynamic range.
output) and the fed-back signal (comparator output) trans-
fer functions A and B are shown together with their
combined response C . Large digital buffers connected to VII. MEASURED
PERFORMANCE
the comparator differential outputs are capable of driving
The minimum measured input current of the receiver for
external TTL loads with a maximum loading capacitance
a BER of was 48-nA rms. Ths translates to an
of 10 pF.
equivalent input noise current of 8-nA rms. The receiver is
capable of 100-pA input signals without any significant
VI. AGC CIRCUITRY degradation of the output eye pattern. The effectiveness of
the quantized feedback is illustrated by the receiver’s per-
Fig. 1 shows that AGC is provided by two independent formance in response to a 215- 1 pseudorandom input
loops. The analog circuitry is virtually identical in both stream at 50 Mbit/s. A digital oscilloscope operating as an
loops. The linear channel AGC loop is shown in Fig. 9. infinite persistence storage scope captures the receiver
The peak-to-peak voltage at the output of the postampli- jitter, typically less than 2 ns, in Fig. 10.
fier is captured by the peak detectors. The positive peak is Fig. 11 is a die photograph of the receiver chip. Auto-
subtracted from the negative peak through the difference matic routing and placement tools were used effectively in
amplifier, and the result is compared with a reference noncritical areas [lo]. The preamplifier and linear channel
voltage VREF. The difference is integrated, and the integra- were manually routed to minimize parasitic capacitance

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 1432
4k
Fig. 10. Receiver eye diagram at 50 Mbit/s.
Fig. 11. Die photograph of receiver.
and resistance. The modest die size of 16 mm2 allows room
for additional analog and digital functions in future gener-
ations of optical receivers.
VIII. CONCLUSIONS
We have shown that wide-band optical receivers can
now be integrated with fine-line CMOS technology. In-
creased integration results from the ability to build high-
impedance nodes and nearly parasitic-free resistors on
chip. Further, high-speed receiver systems will soon inte-
grate clock recovery with the front-end amplifiers making
CMOS an attractive technology alternative.
In this paper we described a 50-Mbit/s monolithc
optical receiver that was fabricated in a 1.75-pm CMOS
technology with an electrical input dynamic range of
greater than 60 dB. We performed a comprehensive noise
analysis of the preamplifier and the predicted equivalent
input noise agreed closely with the measured 8-nA rms.
The overall transimpedance of the linear portion of the
chip which includes the preamplifier, variable-gain ampli-
fier, and postamplifier was well controlled over tempera-
ture, power supply, and processing variations. T h s con-
trolled transimpedance was important in maintaining low
jitter at the output of the decision circuitry as well as
allowing the use of a simple loss of signal scheme. Finally,
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 6, DECEMBER 1988
1 . e nsec
we have proven that a CMOS technology with careful
device layout can provide sufficient isolation for receivers
whose sensitivity approaches the limit predicted solely by
thermal noise considerations.
ACKNOWLEDGMI
NI
The authors thank P. Blomster, J. Hein, D. Morrison, K.
Nguyen, J Scott, D. Sherry, J. Sonntag, A. Stocker, T.R.
Viswanathan. and G. Williams for their contributions and
support.
REFERFNCES
J. M. Steininger and E. J. Swanson, “A SOMb/sec CMOS optical
data link receiver integrated circuit.” in ISSCC Dig. Tech. Pupers,
vol. 29, Feb. 1986, pp. 60-61.
R. G. Meyer and R. A. Blauschild, “A wide-band low-noise
monolithic transimpedance amplifier,” IEEE J . Solid-State Cir-
cuits, vol. SC-21, no. 4, pp. 530-537, Aug. 1986.
I31 M. P. Cooke, G. W . Sumerling, T. V. Muoi, and A. C. Carter,
“Integrated circuits for a 200-Mbit/s fiber-optic link,” IEEE J .
Solid-State Circuit? vol. SC-21, no. 6, pp. 909-915, Dec. 1986.
[41 D. W. Faulkner, A wide-band limiting amplifier for optical fiber
repeaters,” IEEE J . Solid-State Circuits, vol. SC-18, no. 3, pp.
333-340, June 1983.
J. Agraz-Guerena er al., “Twin-tub 111 a third generation CMOS
technology,” in IEDM Tech. Dig.,1984, pp. 63-64.
G. Williams, U.S. Patent 4 540 952, Sept. 10, 1985.
S . D. Personick, Optical Fiber Transmission Systems. New York:
Plenum, 1981, pp. 60-98.
G. Williams, U.S. P?tent 4 574 249, Mar. 4, 1986.
F. D. Waldhauer, Quantized feedback in an experimental 280
Mb/s digital repeater for coaxial transmission,” IEEE Trans. Com-
mun., vol. COM-22, pp. 1-5, Jan. 1974.
C. D. Kimble et al., “Autorouted analog VLSI,” in Proc. 1985
Custom Inregrated Circuits Conj.. pp. 72-78.
David M. Pietruszynski (S’80-M’81) was born in
Reading, PA, in 1960. He received the B.S. de-
gree in electrical engineering from Lehigh Uni-
versity, Bethlehem, PA, in 1981, and the M.S.
degree in electrical engineering from the Univer-
sity of California, Berkeley, in 1983.
From 1981 until 1982 he worked as a consul-
tant for MPR Associates in Washington, DC. In
1982 he joined AT&T Bell Laboratories, Read-
ing, PA, where he is a Member of the Technical
Staff designing integrated circuits for an Analog
I.C. Design group.
Mr. Pietruszynslu is a member of Tau Beta Pi, Eta Kappa Nu, and
Omicron Delta Kappa.
 PIETRUSZYNSKI el d.: 50-MBIT/S CMOS MONOLITHIC OPTICAL RECEIVER 1433

John M. Steininger (M87) was born in Milwau- Eric J. Swanson (S’75-M79) received the
kee, WI, on November 5, 1957. He received the B.S.E.E. degree from Michigan State University,
B.S.E.E. and M.S.E.E. degrees from the Univer- East Lansing, in 1977 and the M.S.E.E. degree
sity of Wisconsin, Madison, in 1979 and 1981, from the California Institute of Technology,
respectively. Pasadena, in 1980.
He has been with AT&T Bell Laboratories, From 1980 through 1985 he was a Member of
Reading, PA, since 1981 where currently he is a the Technical Staff at AT&T Bell Laboratories,
Supervisor of an Analog I.C. Design group which Reading, PA. His work there included echo can-
is working on high-speed/hlgh-frequency inte- celer and optical receiver developments. In 1985
grated circuits. he joined Crystal Semiconductor, Austin, TX,
where he is currently Vice President of Technol-
ogy. His development interests include optical data links, oversampled
data converters, and self-calibrated analog VLSI devices.

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