http://www.vlsi-expert.com/2011/09/delay-interconnect-delay-models-static.html http://www.whycloudcomputing.net/2012/07/cloud-computing-basics-tutorial/ http://nptel.iitm.ac.in/video.php?subjectId=106105083 http://vlsicad.eecs.umich.edu/KLMH/downloads/book/chapter7/chap7-111206.ppt http://www.vlsisystemdesign.com/eco.php http://www.nandigits.com/download.htm http://venividiwiki.ee.virginia.edu/mediawiki/index.php/ToolsSynopsysMain http://bbs.eetop.cn/viewthread.php?tid=299728 http://bbs.eetop.cn/ http://cmosedu.com/videos/videos.htm http://www.vlsi-expert.com/2011/08/delay-timing-path-delay-static-timing.html http://dsal.uchicago.edu/cgi-bin/romadict.pl?query=abhimanam&table=brown http://www.techonlineindia.com/search.aspx?IndexCatalogue=search&SearchQuery=phy sical+design+ degala_s@vizagsteel.com http://www.snapfiles.com/screenshots/recuva.htm http://currentaffairs.gktoday.in/topics/december-2012/page/2/ http://vlsi-sta.blogspot.in/search/label/STA%20Basics http://www.webstatschecker.com/stats/keyword/basic_digital_electronics_interview _questions_and_answers http://vlsiupdatez.blogspot.in/2012/04/digital-design-interview-questions.html http://www.ee.nctu.edu.tw/People/Professor/individual.php?TeacherID=T9407 http://www.youtube.com/watch?v=w0cSahiDvFQ&playnext=1&list=PLB3F0FC99B5D89571&fe ature=results_main http://www.brainybetty.com/SciTech2004/index.htm http://eda.ee.nctu.edu.tw/hrjiang/ http://www.smiletemplates.com/last-added/powerpoint-templates/0.html http://www.youtube.com/watch?v=aGUu2_u4ysk&list=PL1237EC841AE46B6C http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6349427 https://sites.google.com/site/satishkumargrandhi2/what-is-characterization https://www.youtube.com/watch?v=DK-ak_66G1o&feature=rellist&playnext=1&list=PLD2 AC55653E359536 cloud computing microsoft certification http://bbs.eetop.cn/misc.php?action=attachcredit&aid=475732&formhash=c6e12a6a http://www.youtube.com/watch?v=eObJLz6MuHo&feature=BFa&list=PLTEh-62_zAfHmJE-pcj gREKiKyPSgjkxj Complex clock gating with integrated clock gating logic cell http://www.allaboutcircuits.com/vol_4/index.html https://sites.google.com/site/mvrajesh1/interviewquestions http://www.synopsys.com.cn/information/snug/2010/using-multi-bit-flip-flop-for-c lock-power-saving-by-designcompiler http://www.onlymyhealth.com/how-lose-weight-in-days-1312349157 Calculation of Setup Violation Check: Consider above circuit of 2 FF connected t o each other. Setup Slack = Required time - Arrival time (since we want data to arrive before it is required) Where: Arrival time (max) = clock delay FF1 (max) +clock-to-Q delay FF1 (max ) + comb. Delay( max) Required time = clock adjust + clock delay FF2 (min) - set up time FF 2 Clock adjust = clock period (since setup is analyzed at next edge) Calculation of Hold Violation Check: Consider above circuit of 2 FF connected to each other. Hold Slack = Arrival Time - Required time (since we want data to arrive after it is required) Where: Arrival time (min) = clock delay FF1 (min) +clock-to-Q delay FF1 (min ) + comb. Delay( min) Required time = clock adjust + clock delay FF2 (max) + hold time FF2 Clock adjust = 0 (since hold is analyzed at same edge) Calculation of Maximum Clock Frequency: Max Clock Freq = 1/ Max (Reg2reg delay, Clk2Out delay, Pin2Pin delay) Where: Reg2Reg Delay = Clk-to-Q delay of first FF (max) + conb delay (max) + s etup time of 2nd FF. Clk2Out Delay = Clock delay w.r.t FF (max) + clock-to-Q delay of FF1 (m ax) + comb. delay (max) Pin2Pin delay = Comb delay between input pin to output pin (max)