Introduction to VLSI Circuits and Systems, NCUT 2007

Chapter 6
Electrical Characteristic of MOSFETs
Introduction to VLSI Circuits and Systems

Dept. of Electronic Engineering

National Chin-Yi University of Technology
Fall 2007
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
MOS Physics
nFET Current-Voltage Equations
The FET RC Model
pFET Characteristic
Modeling of Small MOSFETs
Introduction to VLSI Circuits and Systems, NCUT 2007
MOS Physics

MOSFETs conduct electrical current by using an

applied voltage to move charge from the source to
drain of the device
Occur only if a conduction path, or channel, has been
created
The drain current I
Dn
is controlled by voltages applied to
the device
Figure 6.1 nFET current and voltages
I
Dn
=I
Dn
(V
GSn
, V
DSn
)
(6.1)
Introduction to VLSI Circuits and Systems, NCUT 2007
Field-effect
Simple MOS structure
Silicon dioxide (S
i
O
2
) acts as an insulator
between the gate and substrate
C
ox
determines the amount of electrical
coupling that exists between the gate electrode
and the p-type silicon region
What is Field-effect ?
The electric field induces charge in the
semiconductor and allows us to control the current
flow through the FET by varying the gate voltage
V
G
Figure 6.2 Structure of the MOS system
Figure 6.3 Surface charge density Q
s
ox
ox
ox
t
C

= (C/ cm
2
) (6.2)
Where, t
ox
is the thickness of the oxide in cm
cm F
ox
/ 10 854 . 8 , 9 . 3
14
0 0

= =
] / [
2
cm C V C Q
G ox s
= (6.3)
Introduction to VLSI Circuits and Systems, NCUT 2007
Threshold Voltage
At the circuit level, V
th
is obtained by KVL
The oxide voltage V
ox
is the difference (V
G
- )
and is the result of a decreasing electric potential
inside the oxide
s ox G
V V + =
Figure 6.4 Voltages in
the MOS system
(6.4)
Where, V
ox
is the voltage drop across the oxide layer
and is the surface potential that represents the
voltage at the top of the silicon
s

Introduction to VLSI Circuits and Systems, NCUT 2007

Electric Fields of MOS (1/ 2)
Figure 6.5 MOS electric fields
Lorentz law: an electric field exerts a force on a
charged particle
A depleted MOS structure cannot support the
flow of electrical current
E Q F
particle
=
qE F
h
+ =
qE F
e
=
(6.5)
s a Si B
N q Q 2 =
ox ox B
V C Q =
(6.6)
(6.7)
(6.8)
(6.9)
(positively charged holes)
(negatively charged electrons)
Figure 6.6 Bulk (depletion)
charge in the MOS system
(bulk charge)
Where
0
8 . 11
Si
(the oxide voltage is
related to the bulk charge)
Introduction to VLSI Circuits and Systems, NCUT 2007
Electric Fields of MOS (2/ 2)
For V
G
<V
Tn
, the charge is immobile bulk charge
and Q
S
=Q
B
For V
G
>V
Tn
, the charge is mode up of two distinct
components such that
If V
G
=V
Tn
, then Q
e
=0
If V
G
>V
Tn
, then
0 < + =
e B S
Q Q Q (6.10)
Figure 6.7 Formation of the
electron charge layer
) (
Tn G ox e
V V C Q =
(6.11)
Where Q
e
: electron charge layer that electrons are
mobile and can move in a lateral direction (parallel to
the surface, also called a channel region)
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
MOS Physics
nFET Current-Voltage Equations
The FET RC Model
pFET Characteristic
Modeling of Small MOSFETs
Introduction to VLSI Circuits and Systems, NCUT 2007
nFET
The dimensionless quantity (W/L) is the
aspect ratio that is used to specify the
relative size of a transistor with respect to
others
The MOS structure allows one to control
the creation of the electron charge layer Q
e
under the gate oxide by using the gate-
source voltage V
GSn
Figure 6.8 Details of the nFET structure
(a) Side view (b) Top view
Figure 6.9 Current and voltages for an nFET
(a) Symbol (b) Structure
L L L = '
W W W = '
(6.19)
Introduction to VLSI Circuits and Systems, NCUT 2007
Channel Formation for nFET
Cutoff modeas Figure 6.10 (a)
If V
GSn
<V
Tn
, then Q
e
=0 and I
Dn
=0
Like an open switch
Active modeas Figure 6.10 (b)
If V
GSn
>V
Tn
, then Q
e
0 and I
Dn
=F(V
GSn
,
V
DSn
)
Like an closed switch
Figure 6.10 Controlling the channel in an nFET
(a) Cutoff (b) Active bias
Figure 6.11 Channel formation in an nFET
(a) Cutoff (b) Active
Introduction to VLSI Circuits and Systems, NCUT 2007
nMOSIV Characteristics (1/ 2)
Three region for nMOS
According Figure 6.12 (Model I, V
DSn
=V
DD
)
Figure 6.12 I-V characteristics
as a function of V
GSn
Tn GS
V V < , 0
.) (
, ) 2 / (
sat D DS DS DS Tn GS
V V V V V V <
.) (
2
, ) (
2
sat D DS Tn GS
V V V V >

=
DS
I
2
) (
2
Tn GSn
n
Dn
V V I =

=
L
W
n n
'
ox n n
C = '
ox
ox
ox
t
C

=
ox
ox n
n
t

= '
(6.20)
(6.21)
(6.22)
(6.23)
(6.24)
(saturation current)
(
n
: device transconductance
parameter)
(A/ V
2
)
(k
n
: process transconductance
parameter)
Introduction to VLSI Circuits and Systems, NCUT 2007
nMOSI V Characteristics (2/ 2)
According Figure 6.13 (Model II, V
GSn
>V
Tn
)
Figure 6.13 I - V characteristics
as a function of V
DSn
[ ]
2
) ( 2
2
DSn DSn Tn GSn
n
Dn
V V V V I =

0 =

DSn
Dn
V
I
[ ] 0 2 ) ( 2 ) ( 2
2
= =

DSn Tn GSn DSn DSn Tn GSn

DSn
V V V V V V V
V
Tn GSn current peak DSn sat
V V V V = = |
2
) (
2
Tn GSn
n
Dn
V V I =

[ ] ) ( 1 ) (
2
2
sat DSn Tn GSn
n
Dn
V V V V I

+ =

2
2
sat
n
Dn
V I

=
(6.29)
(6.30)
(6.31)
(6.32)
(6.33)
(6.34)
(6.35)
(saturation current)
(active region current)
Figure 6.14 nFET family
of curves
(saturation voltage)
Where (V
-1
) is channel length modulation parameter
Introduction to VLSI Circuits and Systems, NCUT 2007
Body-bias Effect
Body-bias effects: occur when a voltage V
SBn
exists
between the source and bulk terminals
Figure 6.15 Bulk electrode and
body-bias voltage
) 2 2 (
0 F SBn F n T Tn
V V V + + =
0 0
|
=
=
SBn
V Tn n T
V V
ox
a Si
C
N q

2
=
(6.45)
(6.46)
(6.47)
Where is the body-bias coefficient with units of V
1/ 2
,
and is the bulk Fermi potential term1
F
2
(zero body-bias threshold voltage)
Where q = 1.6 10
-19
C,
Si
= 11.8
0
is the permittivity
of silicon, and Na si the acceptor doping in the p-type
substrate
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
MOS Physics
nFET Current-Voltage Equations
The FET RC Model
pFET Characteristic
Modeling of Small MOSFETs
Introduction to VLSI Circuits and Systems, NCUT 2007
Non-linear and Linear
The difference between analysis and design
Since non-linear I-V characteristics issue
Analysis deals with studying a new network
from the design, and designers are true problem
solvers
Two approaches to dealing with the problem
of messy transistor equations
Let circuit specialists deal with the issues
introduced by the non-linear devices
Create a simplifies linear model since VLSI
design is based on logic and digital architectures
Figure 6.19 RC model of an nFET
(a) nFET symbol
(b) Linear model for nFET
Introduction to VLSI Circuits and Systems, NCUT 2007
Drain-Source FET Resistance
Figure 6.20 Determining
the nFET resistance
In practical, FET are inherently non-linear
Dn
DSn
n
I
V
R =
DSn Tn GSn n Dn
V V V I ) (
) (
1
Tn GSn n
n
V V
R

] ) ( 2 [
2
DSn Tn GSn n
n
V V V
R

=

n
n
R

1

n
n n
L
W

= '
) (
Tn DD n
n
V V
R

=
) (
1
Tn DD n
n
V V
R

(6.64)
(6.65)
(6.66)
(6.67)
(6.68)
(6.69)
(6.70)
(6.71)
(drain-source resistance)
(at a point in Figure 6.20)
(at b point in Figure 6.20)
2
) (
2
Tn GSn n
DSn
n
V V
V
R

(6.72)
(at c point in Figure 6.20)
Introduction to VLSI Circuits and Systems, NCUT 2007
FET Capacitances
The maximum switching speed of a CMOS
circuit is determined by the capacitances
When we have C = C(V), the capacitance
is said to be non-linear
Figure 6.21 Gate capacitance in a FET
(a) Circuit perspective (b) Physical origin
G ox G
A C C =
' WL C C
ox G
=
GD G GS
C C C
2
1
Figure 6.22 Gate-source and
gate-drain capacitance
(6.76)
(6.77)
(6.78) (ideal model)
Introduction to VLSI Circuits and Systems, NCUT 2007
Junction Capacitance (1/ 2)
Semiconductor physics reveals that a pn junction
automatically exhibits capacitance due to the opposite
polarity charges involved is called junction or depletion
capacitance
Such that the total capacitance is (C
SB
and C
DB
)
Two complications in applying this formula to the nFET
First, this capacitance also varies with the voltage (C =C(V))
Second in next slide
Figure 6.23 Junction
capacitance in MOSFET
) (
0
F A C C
pn j
= (6.82)
Where A
pn
is the area of the junction in units
of cm
2
, and C
j
is determined by the process,
and varies with doping levels
Figure 6.24 Junction capacitance
variation with reverse voltage
j
m
o
R
V
C
C

+
=

1
0

=
2
ln
i
a d
o
n
N N
q
T

(6.83)
(6.84) (built-in potential)
Introduction to VLSI Circuits and Systems, NCUT 2007
Junction Capacitance (2/ 2)
Second, we need to consider in calculating the pn
junction capacitance is the geometry of the pnjunctions
Figure 6.25 Calculation of the
FET junction capacitance
(a) Top view
(b) Geometry
XW A
bot
=
XW C C
j bot
=
sw j j j sw
P x x X x W A = + = ) ( 2 ) ( 2
) ( 2 X W P
sw
+ =
farads P C C
sw jsw sw
=
cm F x C C
j j jsw
/ =
) (
o
L X X +
sw jsw bot j sw bot n
P C A C C C C + = + =
jsw j
m
osw
sw jsw
m
o
bot j
n
V
P C
V
A C
C

+
+

+
=

1 1
(6.85)
(6.86)
(6.87)
(6.88)
(6.89)
(6.90)
(6.91)
(6.92)
(6.93)
(1. bottom section)
(2. sidewall)
(sidewall capacitance per unit perimeter)
(sidewall perimeter)
(non-linear model)
(1 + 2)
(including the overlap section)
Introduction to VLSI Circuits and Systems, NCUT 2007
Construction of the Model
Parasitic resistance and capacitance of MOS
It is important to note that the resistance R
n
is
inversely proportional to the aspect ratio
(W/L)
n
, while the capacitances increase with
the channel width W
Figure 6.25 Calculation of the
FET junction capacitance
(b) Linear model
for nFET
Figure 6.26 Physical visualization
of FET capacitances
(a) nFET
SB GS S
C C C + =
DB GD D
C C C + =
(6.94)
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
MOS Physics
nFET Current-Voltage Equations
The FET RC Model
pFET Characteristic
Modeling of Small MOSFETs
Reference for Further Reading
Problems
Introduction to VLSI Circuits and Systems, NCUT 2007
pFET Characteristic (1/ 4)
nFET translates to pFET
Change all n-type regions to p-type regions
Change all p-type regions to n-type regions
Note, both the direction of the electric fields
and the polarities of the charges will be
opposite according equation (6.101)
n-well is tied to the positive power supply
Figure 6.29 Transforming an
nFET to a pFET
Figure 6.30 Structural detail of a pFET
(a) Side view (b) Top view
ox
ox
ox
t
C

= (6.101)
Introduction to VLSI Circuits and Systems, NCUT 2007
pFET Characteristic (2/ 4)
V
SGp
determines whether the gate is sufficiently
negative with respect to the source to create a layer
of holes under the gate oxide and thus establish a
positive hole charge density of Q
h
C/cm
2
Figure 6.31 Current and
voltages in a pFET
(a) Symbol
(b) Structure
) ( 0
Tp SGp h
V V for Q < =
) (
Tp SGp h
V V for exists Q >
ox
I
FBp Fp Fp d Si
ox
Tp
C
qD
V N q
C
V + = 2 ) 2 ( 2
1

=
i
d
Fp
n
N
q
kT
ln 2 2
(6.102)
(6.103)
(6.104)
Introduction to VLSI Circuits and Systems, NCUT 2007
pFET Characteristic (3/ 4)
Figure 6.33 Gate-controlled pFET
current-voltage characteristics
(b) Active bias
Figure 6.32 Conduction
modes of a pFET
(a) Cutoff
2
) (
2
Tp SGp
p
Dp
V V I =

p
p p
L
W
k

= '
ox p p
C k = '
3 ~ 2 =
p
n
r

n
n n
L
W

= '
p
p p
L
W

= '
(6.105)
(6.106)
(6.107)
(6.108)
(6.109)
Introduction to VLSI Circuits and Systems, NCUT 2007
pFET Characteristic (4/ 4)
Figure 6.34 pFET I V family of curves
Tp SGp sat
V V V =
[ ]
2
) ( 2
2
SDp SDp Tp SGp
p
Dp
V V V V I =

2
) (
2
Tp SGp
p
Dp
V V I =

(6.110)
(6.111)
(6.112)
Introduction to VLSI Circuits and Systems, NCUT 2007
Outline
MOS Physics
nFET Current-Voltage Equations
The FET RC Model
pFET Characteristic
Modeling of Small MOSFETs
Introduction to VLSI Circuits and Systems, NCUT 2007
Scaling Theory (1/ 2)
s
L
L
s
W
W = =
~ ~
2
~
s
A
A =

~
~
L
W
L
W
ox
ox
ox
t
C

=
s
t
t
ox
ox
=
~
ox
ox
ox
ox
sC
s
t
C =

=

~
s
L
W
s =

= '
~
) (
1
T DD
V V
R

) (
1
~
T DD
V V s
R

s
R
R =
~
(6.118)
(6.119)
(6.120)
(6.121)
(6.122)
(6.123)
(6.124)
(6.125)
(6.126)
(6.127)
Introduction to VLSI Circuits and Systems, NCUT 2007
Scaling Theory (2/ 2)
s
V
V
s
V
V
T
T
DD
DD
= =
~ ~
,
R R =
~
s
V
V
s
V
V
GS
GS
DS
DS
= =
~ ~
,
s
I
s
V
s
V
s
V
s
V s
I
D DS DS T GS
D
=

=
2
2
2
2

2
~ ~ ~
s
I V
I V P
D DS
D DS
= =
(6.128)
(6.129)
(6.130)
(6.132)
(6.133)
[ ]
2
) ( 2
2
DS DS T GS D
V V V V I =

(6.131)