An Effective Approach For Subtreshold And Gate

Leakage Power Estimation Of SRAM

Feng Zhang Ge Zhang Yi Yang Jun Wang
Institute of Computing Technology, CAS, Beijing, 100080, China
Graduate School of the IME, Beijing, 100039, China
{ zhangfeng,gzhang,yangyi }@ict. ac. cn
Abstract-The leakage current in SRAM is the vital factor for leakage power of the SRAM.
the low power processor design. In this paper we develop a fast Butts and sohi proposed a generic model for micro-
approach to calculate the total leakage power of SRAM, architecture components [6]. Mamidipaka developed
considering the subthreshold leakage (Isub) and gate leakage
(Igatc).('gae).Thismetod
This method iS prpose ontheS
i proposed RA special
on the SRAM pca comprehensive
estimation
models for subtheshold leakage power
in memor arrays without the spice simulation
architecture, using the stack factors as the average factor to e7tMm idipaka' m moacrays noti the gate
compute the IS ub and using the statistical algorithm to estimate [7]. Maidpaa s m ac delesoile her gate
the gate leakage power. The method does not need to be much le rent coptnAnd the leakage power variato
muchdifferenteprcess.rAndite
considered on the working state of SRAM and it can be applied of leakage leakage
without much spice simulation and suitable for SRAM leakage
* *>- x7 ..... . .
due to the thinner oxide gate
gate subtheshold
arises during the lower threshold voltage.
power computing at the different process. We use this method
to test a number of SRAM circuits in the 0.18um, 0.13um, In this paper, we propose a whole and efficient technique
90nm and 65nm technology and demonstrate the accuracy for the SRAM leakage power estimation, especially the gate-
within less than 5% of hspice on average. This technique is leakage and subtheshold leakage. SRAM architecture is
much useful for the system designers to estimate the power mainly composed of the same memory cells and similar logic
earlier, and can effectively improve the power management of circuits; therefore it is suitable for using the statistical
the processors and shorten the design time. algorithm to measure the Igate. And we compute the average
stack factors of unit cells based on their input vectors and use
the average stack factor as the estimation of Isub. It can ignore
I. INTRODUCTION the various change of large macro cell due to the multiple
Static leakage is increasing rapidly due to the thinner input vectors and it is also useful for different process. We
oxide gate and lower threshold voltage With the apply the technique to estimate leakage power, the
advancement of technology[1-3].The total leakage current of computing results of the algorithm shows these techniques
a circuit is mainly determined by the sum of subthreshold, obtain IOOX to 1,000X speedup compared to spice
gate and reversed biased junction BTBT leakage current. [4] simulation and which can shorten the design time.
A number of previous studies have been reported on the
calculation of each kind of leakage power in subthreshold The rest of the paper iS
int roduces somse bai concepts
organized as follows: Section II
current of an individual BSIM model which is widely used firstl of leakage
power In
for calculating [5]:In addition, gate leakage current causes
increased power dissipation even in active mode of operation
Section do swe
propose the effective approach of leakage
power, do some experiments on the different process and
and hence any gate leakage reduction scheme needs to verify the effectsofourapproach insectionIV,andfollowed
consider its effect in both the active and stand-by modes. by the conclusion in section V.
In high-performance processors, SRAM as the form of II. LEAKAGE POWER ANALYSIS
caches (tag and data arrays), branch target buffers,
reservation stations, etc. LI and L2 caches alone occupy For subthreshold current of an individual BSIM model is
majority of the die area. Expectedly, SRAM also contribute widely used for calculating [8]:
to majority of the leakage power in processors. -qV+_
q
SRAM is the multi-port custom macro cell, testing the I AenKT(G (I e KT
power is dependent on the spice simulation. However the subthW()
t

spice simulation has to spent much time especially on the And A = cox W KT e2 l8 (1)
post layout simulation, and there are many input vectors for L eff q
the simulation of the multi-port cell. Therefore circuit
designers are anxious to have the model to estimate the Where Vg, Vs are gate voltage and source voltage,
VDS ,VTHis the thermal voltage, is the linearized body-
Supported by the National Natural Foundation of China for Distinguished
Young Scholars under Grant No.60325205, the National Natural Science
Foundation of China under Grant No. 60673146, 60603049, the National High
Technology Development 863 Program of China under No. 2006AA0 10201, and
the National Grand Fundamental Research 973 Program of China, National
Basic Research Program of China under No 2005CB32 1600; Supported by
Beijing Natural Science Foundation No.4072024

325
1-4244-0797-4/07/$20.OO ©¢ 2007 IEEE

Authorized licensed use limited to: University of Central Florida. Downloaded on October 25, 2008 at 23:53 from IEEE Xplore. Restrictions apply.
 effect coefficient 9 is the Drain Induced Barrier III. SRAM leakage power analysis model
Lowering, Cox is gate capacitance/area, L and W are the
length and width of the transistors. where it o is the carrier Input Address
mobility and Leff is the effective gate length of the device. B
ffe

Eq(1) of calculating Isub in the chip can be very time- AxCel

consuming. To overcome this barrier, the following simple Clock t
empirical model has been proposed: Input

'sub =I X'°t X
xsI
(2)
Data
'off is the leakage current per micron of a single transistor Output
measured from actual silicon at a given temperature, Wtot is SsActivaion
Pulse Generator
_lSers
the total transistor width(sum of N and P devices), Xs is the
empirical stack effect, and Xt is the temperature factor.
'off and Xt are constants at some temperature, so how to Figurel. Typical architecture ofarray structure
compute the Wtot and Xs are the important factors. For the
Wtot, equation (3) shows: column memory cell array
SRAM core cell has several kinds of architectures, but
W0t/XXs= (W *f )/ Xs, (3) the most common architecture is the 6T cell since the 6T cell
is easy to be realized and has small area. SRAM core cells
f, being the frequency of its occurrence in the design. Xsi account for the major area in the cache design. So the
is the individual factor of one cell, from equation (2) and (3) leakage power of 6T cell is the significant factor affecting
we can get the 'sub the whole power.
Not only the subthreshold leakage is state dependent, The leakage current in arrays varies within a clock cycle
recent researches show that the gate leakage is also state depending on the phase of operation being performed, since
depended. While Isub depends on the number of OFF different transistors would be in off state. There are three
transistors in stack, Igate depends strongly on the position of operations to the SRAM, read, write and idle. The core cell
ON/OFF transistors in stack so different circuit input states just has two states in the three operations in fig2, fig3.
can lead to different Isub and Igate Read or Write
IDLERedoWrte
For simulation purposes, an oxide leakage model was 0
incorporated in an existing 100nm BSIM3v3 (level49) model _ WL
generated Berkeley Predictive Technology Model [8], Since
BSIM3 does not model oxide leakage, voltage dependent
current sources from the gate to source (Igs), and from the
gate to drain were implemented in the macro model, The DL - I' __ DL FL
dependence of these currents on gate to source voltage (V-) T
and gate to drain voltage (Vgd) is given by the following two -ubteo lekag
expressions: ^ g e kage

l7O X L 1l
127.04
Leff X e(5.60625xVg
e
0 06xTo,-2
lo 5) WL
gs 2 iL iK

127.04 x L X e (5.60625 xVg, 10 06X

2O TiTwV Ti --Tr- Ti
gd 2 (4) Idle Phase Write Idle Phase Read Idle Phase
2 ~~~~~~~(4) Phase PaeIl hs

Where T0x and Leff are given in nanometers and igs and igd
are given in iA per ptm of transistor width (assuming
minimum channel length).
Since the gate to source and gate to drain overlap regions
are much smaller than the channel region, the gate tunneling
current in the OFF state is much smaller than gate tunneling
in the ON state. If SiO2 is used for the gate oxide, PMOS
transistors will have about one order of magnitude smaller
gate leakage than NMOS transistors.
Figure2. Leaking memory cell transistors in Idle and active operation phase
There are a lot of differences between the I,ub and Igate
approved by the above equations, from the most 6T cell
design we can see the number and the area of n-ch transistors
are larger than p-ch, the Igate is ignored especially to the thin-
oxide gate. We analyze the 6T cell Isub and Igate at different
process; the data is in table t. The conclusion is that the gate
tunneling current effectively displaces the subthreshold
current, changing the ratio of the leakage current.

326 2007 IEEE International Symposium on Integrated Circuits (ISIC-2007)

Authorized licensed use limited to: University of Central Florida. Downloaded on October 25, 2008 at 23:53 from IEEE Xplore. Restrictions apply.
 Table I. Pattern sequences for leading one position libraries used in the design and secondly Simulate all the
Core 180nm 90nm 65nm (pA) cells exhaustively for average leakage currents and stacking
cell (pA) (pA) factors.
Igate Isub Igate Isub Igate Isub
Read 1.2e 8.2e 1.2e 1.8e 2.le 1.9e To the inverter, the subthreshold leakage power
or
Write II
+04 +04 +05 +05 +06 +06 A= I effective leakage width L = XWp
(Lp / u)
Idle 3.7e Lle 0.7e 2.5e 1.Oe 2.3e Thereforethe effectiveLequation is:
+03 +05 +05 +05 +06 +06
A rTB -
T A=O effective leakage width L n=
JnJL /u)
I Nmux
leakageT-- ~A+(Ctotal-Nmux -N
Nbit -Iactive b(, .) Ididle -B (5) Linv = Y/ Wp (Lp l u) + Y2 Wn (Ln lIu)
Table II Leakage Power Model Inputs To the nand2, leakage power model:
Parameter Description (the inputs ports are A and B)
Nmux SRAM bitline multiplexers
Nbit DataBits L -2W (L /u) A=1 B=
Ctotal The total capacity of SRAM 4
T The statistical time length
We can see the l'eakage power is dependent on the 'state of L 1
the SRAM work. If we want to get the accurate leakage -W
4 n (L nU) A - ,B-O
power, we have to consider the working frequency and data
refresh frequency and so on. In most high speed and high L = - W (L I u) A=O,B= 1
density SRAM the pulse of word line in "on" state becomes 4
shorter and shorter, the Tr is generally much less than the T1,
and the statistical data shows the most core cells are in the L = -W S L /u A=O,B=O
idle state for a long time even though SRAM is working in 4
written or read state (fig3). Therefore the equation (5) can be From the above equations, the nand2 effective L is:
advised as the following one (6):
The nand3 effective L is
'leakage Ctotai B(6)
L2nand - Y2 Wp (Lp I u) + 2 Wn (L/nIu)
Memory Cell Array The above equations show that Isub is much dependent on
_ X_I_ _I Lea}ak. Rtat Of Different the Xs is the ratio of different gates 'sub, and therefore we can
IFdl I nand2 Xs:
i get the
Xs ~2 (Lnnd 2 /Linv)
:-

Rows
~~~~~~~~~~~~~~If
we define the inv Xs is "1", the from the equation, to
aciethe nand3:.

L3nand X Wp (Lp l u) + YWn(Ln l u)

Figure3. Most Core Cells are in active state The nand3 Xs is greater than 3.
Address decoder and other logic circuit Only If we get the W. and Xsi, we can compute the WO,
To facilitate analysis, an effective leakage function (L- Xs and Isub using the equation (2) and (3).
effective) which reports maximum and minimum drive For the gate leakage, the Igate of "on" state transistor is
strength of a gate was used. To obtain drive strength, the L- much larger than "off' state transistor. The statistical
effective algorithm first recursively traverses the netlist tree algorithm is fit to compute the Igate. The table III shows the
and collapses parallel and serial networks using the standard nand3 Igate is dependent on the number of "high" inputs
equations. The L-effective algorithm then uses optimized [9][IO]. The data shows the Igate will decrease as some ratio
collapsation equations to reduce the parallel and serial with the "high" input number.
networks. Table III Gate Leakage variation in different inputs
The bias conditions seen by a device in a circuit depend Nand3(pA) <111> <110> <100> <000> average
on its position in the circuit and the applied input vector. 180nm 2.3e+04 1.7e+04 0.6e+04 0 1.5e+04
There are many logic gates in the decoder, such as inverter, 90nm 3.4e+05 2.6e+05 1.2e+05 0 2.4e+05
nand and nor, therefore firstly determine the primitive cells 65nm 9.le+05 5.2e+05 2.9e+05 0 5.8e+05

2007 IEEE International Symposium on Integrated Circuits (ISIC-2007) 327

Authorized licensed use limited to: University of Central Florida. Downloaded on October 25, 2008 at 23:53 from IEEE Xplore. Restrictions apply.
 SRAM address decoder and clock generators are
combined of digital circuits so their Igate is different to a
certainty ratio. To compute the Igater O spice simulation
Stepl: compute the average gate leakage of unit cells E0algorithm
such as the inverter, nand, nor and so on. 0.6
Step2: Count the number of all cells and their width.
b' 0.4
Step3: Calculate the total gate leakage based on a -d
certainty ratio of various cells. 0. 2-
The above statistical method reflects the average gate
leakage current , if computing the maximum or minimum 018.
Igate, the method will be have some errors more than 50%. 180nm 130nm 90nm
process variation
65nm

IV. EXPERIMENT RESULTS

The proposed approach for average gate and Figure 5. 1024x32 SRAM leakage power at different process
subthreshold leakage current estimation was implemented
and tested for SRAM at different process. All SRAM circuits V. CONCLUSION
are generated from 180nm,130nm, 90nm and 65nm memory In this paper we developed an efficient approach to
compiler ofthe library. computing total leakage current in SRAM considering both
Table IV leakage power of SRAM at different process subthreshold and gate tunneling currents. The proposed
180__mw__
m__ 130__m__mw__ 90nm(mw) 65nmw
approach accurately accounts for the complex interaction
between Igate and Isub. Although the leakage power is
16kb 0.032 0.07 0 18 0.29
32kb 0.101 0.15 0.32 0.52 dependent on the working state, this method need not to pay
64kb 0.213 0.33 0.58 0.98 attention to the input vectors of the macro-cell, it can
calculate the total average leakage fast and accurately based
100% on the stack factors and the statistical algorithm and speed up
0 gate E subtheshold the spice simulation more than 1OOX, it also can help the
80% designers to estimate the power earlier.
W60%1 1X n 5 REFERENCES
[1] Rahul M. Rao, et, Al. Efficient Techniques for Gate Leakage
ai40%[r & ll| rs m | Estimation ISLPED'03, August 25-27, 2003, Seoul, Korea.
[2] F. Hamzaoglu and M. Stan, "Circuit-Level Techniques to Control
20 1> | 0 10| | H | 2 l l Gate Leakage for sub-lOOnm CMOS. Proc. ISLPED, pp. 60-63, Aug.
2002.
0%
1Ll : Lj u[3] Siva Narenda. "Full-chip Sub-threshold Leakage Power Prediction
18Onm 13Onm 9Onm 65nm Model for sub-0.18 pm CMOS" ISLPED '02, August 12-14, 2002.
[4] Fatih Hamzaoglu. et,al circuit-level techniques to control gate
leakage for sub-100nm CMOS". ISLPED'02 August 12-14 2002.
[5] Wenjie Jiang,Vivek Tiwari, Erik de la Iglesia, et al, Topological
Figure 4. Different ratios of Igate VS Isub. Analysis for Leakage prediction of Digital Circuits. Proceedings of
Fig 4 shows the ratio of gate and subtheshold leakage of the 15th International Conference on VLSI Design. 2002: 39 -44
SRAM circuit. We can conclude theIgate is very small in high [6] J.A.Butts and G.S.Sohi.A Static Power Model for Architects.In
thin oxide transistors, and increasing very much along with Intl.Symposium on Micro architecture, 2000.
[7] Mahesh Mamidipaka, et,al. Analytical Models for Leakage Power
thethe
thinner oxide gate.
thinner oxide The gate
gate. The gate leakage
leakage accounts for the
accounts for the Estimation of Memory Array Structures. CODES+ISSS'04,
higher ratio of leakage power under 65nm therefore Igate must September 8 -10, 2004.
be considered more. [8] J.Sheu, et,al .BSIM: Berkeley Short-channel IGFET Model for MOS
transistors.IEEE Solid-State circuits,1987: 558-566
The approach in this paper is mainly used for the average [9] Dong woo Lee,et,al.Gate Oxide Leakage Current Analysis and
leakage current calculating. We use spice to simulate the Reduction for VLSI Circuits. IEEE TRANSACTIONS ON VERY
SRAM circuit with more than a hundred of different input LARGE SCALE INTEGRATION(VLSI) SYSTEMS, VOL. 12,
vectors, and compute the average current of these simulation NO.2, FEBRUARY 2004.
current data. The proposed method had an average error of [10] Rahul M. Rao, et,al.Circuit Techniques for Gate and Sub-Threshold
less than 5% over all circuits and simulated circuit states. Leakage Minimization in Future CMOS Technologies. Solid-State
Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th
European.

328 2007 IEEE International Symposium on Integrated Circuits (ISIC-2007)

Authorized licensed use limited to: University of Central Florida. Downloaded on October 25, 2008 at 23:53 from IEEE Xplore. Restrictions apply.