A Combinatorial Approach to Suppress Leakage Power
in Nanoscale SRAM Cells
D.Kudithipudi, and E.John
Laboratory for Low Power Design
Department of Electrical and Computer Engineering
University of Texas at San Antonio
San Antonio, TX-78256
E-mail: dkudithi@lonestar.utsa.edu, eugene.john@utsa.edu
Abstract— In deep sub-100nm technologies, the exponential
increase of static leakage current pose serious design
challenges as we try to build efficient low power systems with
faster memory cores. Consequently, it is imperative to design
systems that adopt leakage control techniques during both
standby and active mode. In the recent past, the size of
memory cores also has been increasing at a very rapid pace to
cope with the demands of high computing processors. Such
large memory cores will lead to significant leakage power
dissipation, as most of the devices will be in a dormant or
standby mode. This study addresses the static current
dissipation problem in an SRAM memory core, by
implementing a combinatorial approach to reduce leakage
current. In this approach we have combined multiple-Vth
devices, high-oxide thickness devices and dynamic Vth
techniques to reduce both subthreshold and gate-oxide leakage
current. There is a ~60% savings in the total static current
dissipated as compared to a conventional SRAM cell.
I. INTRODUCTION
Nanoscale process helps designers the efficacy to
achieve high complexity devices by integrating greater
density of transistors on the system-on-chip processors
[1][2]. The downside of this is the dissipation of heavy
static leakage current at such small geometries. This will
affect the system design process as a whole, especially for
mobile and hand-held devices where extreme performance
with minimal power consumption is the prime concern
[1][2][3]. To attain such conflicting goals, building power-
efficient systems without sacrificing performance, proves a
very intricate task for chip designers. Specifically, the
device techniques implemented in micron scale may not
hold true in nanoscale. Understanding the dynamics and
physics of circuit behavior is itself still in an exploratory
stage.
On one end, leakage current is increasing at an
exponential rate in the nanoscale design due to the scaled
down gate oxide thickness, supply voltage, threshold
voltage and the channel length. On the other end, as
This research was supported in part by the National Science Foundation
under Grant Number ECS- 0219338
0-7803-9197-7/05/$20.00 © 2005 IEEE. 599
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microprocessors are becoming large and complex, the
internal data storage units in the form of cache arrays
consume an increasing portion of the transistor count and
die area [3]. Henceforth, any alteration in the design of these
sub-units will influence the overall power, performance and
reliability of the system. SRAMs are the core storage
elements of these cache arrays, thereby contributing to a
significant portion of leakage current in the processor. The
leakage reduction techniques applied at gate-level or logic-
level cannot be applied to the conventional six-transistor
SRAM circuit, since it is much more sensitive to the
variation of current (differential) at the bitlines.
Some of the previous work focused only on reducing
one of the leakage components for a particular technique
[1,2,]. A detailed analysis on estimating leakage current in
the SRAM modules is presented in [4]. In [5], authors have
proposed a dual Vth technique to reduce leakage current,
with differential sensing for high-performance. In [7] a
dynamic Vth scheme which uses variable body biasing to
reduce leakage power was implemented. All these
techniques reduce only subthreshold leakage current.
In our work, we concentrated on implementing circuit level
techniques to mitigate both sub-threshold and gate-oxide
leakage power. Multiple threshold voltages and Thick gate
oxide techniques are used independently to reduce active
mode leakage. To further take advantage of these techniques
we used a combinatorial approach, in which we used high
threshold voltage devices on critical leakage path and high
gate oxide devices on critical paths of the SRAM circuit.
Based on the technology node, optimal gate oxide thickness
was chosen. Since this technique only takes care of the
standby leakage, to reduce the active leakage power we
have implemented Dynamic Vth along with the high Vth,
high gate oxide devices. Two additional NMOS transistors
are used in this architecture, where the NMOS substrate can
be switched to 0V for high performance.
The rest of the paper is organized as follows: Section II
explains the leakage current components and paths in an
SRAM cell, Section III describes the estimation of leakage
current in SRAM cells, Section IV provides the
experimental case studies that we used, Section V discusses
the results and Section VI has concluding remarks.
II. LEAKAGE CURRENT IN AN SRAM CELL
A conventional six transistor CMOS SRAM cell
comprises of cross-coupled inverters, which act as memory,
and two pass transistors which serve as a combination
read/write port, as shown in Fig.1. In order to determine the
mode of operation in an SRAM cell three different control
signals are used, Word, Bitline, and Bitline# (complement of
Bitline). Once the complementary signals Bitline and
Bitline# are precharged or driven by external circuitry, the
address is decoded and the wordline Word for the selected
row is driven across the array turning on the pass transistors
N3 and N4. In essence Word is the control signal which
enables the SRAM cell and determines either to write bitline
and bitline# in to the memory or to read from the memory.
Sizing the transistors to the process minimum requirements
will confine the differential charge between the bitline and
bitline# (which determines the speed of the read operation).
The operation of the SRAM cell is therefore very sensitive
to the process variations and especially to the effects caused
by static current dissipation.
The two dominant sources of static leakage power in
any CMOS circuit are: sub-threshold leakage current and
the gate-oxide tunneling current. When the gate-source
voltage of a CMOS transistor is less than its threshold
voltage (Vth), ideally there should be a negligible
conduction between the drain and source (micron scale) [2].
However, at very low Vth (in nanoscale devices), there
exists a significant inversion current from drain to the
source, which is referred to as the sub-threshold leakage.
This implies that using higher Vth devices reduces the sub-
threshold leakage current. Also, at smaller geometries gate
oxide is aggressively scaled to provide substantial current
drive (at reduced supply voltage) and to curtail the drain-
induced barrier lowering (DIBL) effect [6]. This results in
the prevalence of the gate tunneling leakage current.
P1
N3 N4
N1
P2
N2
BitLine
Figure 1: Conventional Six Transistor SRAM cell
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The subthreshold leakage current increases at the rate of
3-6X per each technology generation following the scaling
theory [6], whereas the gate oxide thickness decreases at the
rate of 30% per each technology generation. For further
smaller devices gate tunneling current is expected to be
much higher than the subthreshold leakage current.
There are two dominant subthreshold leakage paths in an
SRAM cell: 1) From the supply (VDD) to the GND terminal
2) From the bitline access transistors (N3 and N4) to the
ground. Collectively, they contribute up to 90% of the total
leakage power in an SRAM cell. Whereas, the gate
tunneling leakage current of the access transistors is
determined by the voltage differential at the bitlines.
III. ESTIMATING LEAKAGE IN SRAM
The sub-threshold leakage drain current in an SRAM cell
is measured using the BSIM4 [10] model given by:
Ids=I0 (1-e(-Vds/vt)) e(Vgs-Vth-Voff/nvt) (1)
where I0 is the current dependent on the transistor geometry,
Voff is the empirically determined model parameter, Vds is
the drain-source voltage,vt is the thermal voltage (=KT/q,
where K,q are physical constants and T is the absolute
temperature), Vth is the threshold voltage, Vgs is the gate-
source voltage, and n is the subthreshold swing parameter.
The smaller the swing, the better the subthreshold behavior
(lower leakage current at Vg=0 for given Vt). To reduce the
swing we can use thinner oxide devices. Further description
of the parameters can be obtained from [10].
The gate-oxide tunneling current is given by the
equations:
Igc = Weff * Leff* Jgate (2)
Jgate=Ag*(tavef/tox)ntox(Vg.Vaux/tox2)*e(-Btox(α-β|Vox|)(1+γ|Vox|) (3)
where Weff and Leff are the effective width and length of the
transistors (Note: P-type transistors are designed twice the
width of N-type transistors). Detailed description of the
terms used in expression (3) is available in [10].
Once the leakage current equation is defined, the overall
subthreshold leakage current is measured by summing up
the drain current through each of the transistors and also the
bitline leakage power occurring through the bitline’s of the
SRAM cell. In the next section we discuss the results of the
evaluation of the power estimates based on SPICE
______ simulations using NANOSIM simulator. Since the transistors
BitLine in the SRAM cells are fundamentally altered as high-
threshold and low-threshold voltage devices customized to
reduce the overall SRAM leakage power the leakage current
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for the p-type and n-type transistors was calculated
separately. We have simulated the basic SRAM memory
cell layout on MAGIC7.2 using BPTM [10] MOSFET
models for 65nm technology nodes. The SPICE simulations
are performed on a transistor-level netlist with RC back
annotation obtained from layout. Once the circuit is
validated, the same SPICE deck was used for estimating
leakage current in NANOSIM. Using the configuration file
we obtain leakage currents from all the nodes and bitlines
and calculate the average and RMS leakage current. To have
more realistic results we have given a very large input
stimulus. This input stimulus is obtained from running
ISCAS95 benchmark circuits.
IV. EXPERIMENTAL STUDY
A. Case Study-1
The following are the case studies that we have used in our
experimental study to reduce leakage power.
• Case 1: Transistors P1, P2, N3, N4 – High
Threshold Voltage.
Figure 2: Average and RMS static leakage current of a
SRAM cell using Multiple-Vth and high gate oxide devices
• Case 2: Transistors N3, N4- High Threshold Voltage
• Case 3: Transistors P1, P2, N1, N2 N3, N4- High
Threshold Voltage
• Case 4: Transistors P1, P2, N3, N4 – High
Threshold Voltage and N1, N2- high gate oxide
thickness
• Case 5: Transistors N3, N4- High Threshold Voltage
and N1,N2-high gate oxide thickness
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• Case 6: Transistors P1, P2, N1, N2 - High Threshold
Voltage and N3,N4- high gate oxide thickness
In the above cases the transistors P1-P2, N1-N4 used can
be related to the labels from Fig. 1. Using such high Vth
devices in the leakage critical paths will reduce the sub-
threshold leakage power [5]. As already mentioned high gate
oxide thickness devices reduce the gate-oxide tunneling
current. Integrating both the techniques on to one circuit is a
layout critical task. However, the leakage savings obtained
are substantial to offset the layout problem.
B. Case Study-I1
In this study case we use Dynamic Vth Scaling (DVTS)
[7] scheme for active leakage power reduction along with
Study Case1 techniques. Whenever there is a slack during
computation, the threshold voltage is adaptively changed to
a higher value via changing the body bias voltage (VBB).
When the world lines of the cache are not in use, we can
switch the substrate to negative voltage to reduce leakage.
Since small positive voltage is given to NMOS at standby
mode, it acts as an increased ground potential reducing most
of the voltage differences and hence reducing the gate
leakage in the SRAM cell. This will decrease the drain to
Figure 3 Total Power consumed in an SRAM block for each
of the case studies
source potential resulting in less Drain Induced Barrier
Lowering (DIBL) factor. The switching time increases
from/to standby mode because of the high well capacitance.
A detailed study on dynamic Vth technique can be obtained
from [7].
V. RESULTS AND DISCUSSION
The static leakage current dissipated in the SRAM cell
for a 65nm technology node is shown in Fig.2. A supply of
0.8V is given based on the technology node.

Fig 4: Static Leakage Current dissipated for Case Study II
The graph represents both the average and RMS (Root Mean
Square) values of the leakage currents dissipated in an
SRAM cell. As expected, for all case studies the leakage
power dissipated is less than that of a conventional SRAM
cell with no special devices. However the savings for each
case varies depending on external factors such as: 1) The
number of read and write operations performed by the
benchmark stimulus. Usually more leakage current is
dissipated for read operation than that for a write operation.
2) Which of the transistors have high threshold voltage
devices (if they form the critical path or not). 3) Whether
both the high threshold voltage devices and high gate oxide
thickness are used for a particular case. Considering all the
above conditions we can clearly see from the graph that
cases 4 and 6 have better savings compared to the other
cases, where both the techniques are employed. There is a
leakage current savings of 45% using these two techniques.
Implementing these techniques will also affect the total block
power of the SRAM memory cell. In Fig.3, the block power
for each of the cases is plotted. The difference in total block
power between conventional SRAM cell and other cases is
not as significant as their counter leakage power savings
(Fig.2.).Considering each of the cases, the leakage power
dissipation is less for case1 and case 3, but not the block
level power as compared to case2. This might be due to
some performance loss caused by using the customized
components. To further save the leakage power we have also
implemented dynamic Vth technique along with the high
threshold voltage devices and high oxide thickness devices.
Fig.4 shows the reduced static leakage current when this
combinatorial approach is used. For all the cases there is a
55-60% reduction in leakage current when this approach is
used.
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VI. CONCLUSIONS
In nanoscale domain, designing for low power and high
end performance systems is an impending task due to the
increasing effects of static power dissipation. In this paper,
we presented an integrated model for leakage power
reduction in SRAM cells. The results are obtained from RC
back annotation of layouts in to SPICE simulations based on
BPTM technology nodes for 65nm. Two study case sets
were incorporated to design the models. Case Study 1
results in a 40% savings in leakage power by implementing
high Vth and high oxide thickness devices at various paths of
the SRAM cell. The model from Case Study 2, which
incorporates dynamic Vth technique along with Study
Case1 techniques proved more effective by showing a 60%
savings in the static leakage current dissipated. We can
extend this model to the entire sub-block and also study the
impact on stability and the noise margins.
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