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R Singh S Sali

written to automatically integrate the substrate in Spice

As digital clocking frequencies continue to increase, designs. It is simple and efficient to use, involving no

substrate noise is fast becoming a critical issue for VLSI information and minimal fabrication details.

mixed-signal chip designers. However, current methods SubSim integrates both CMOS and BJT devices with

for directly modelling the noise in realistically-large the substrate and has been written for use in PSpice

Spice designs are impractical, due to numerical net-lists. In Section 11, we briefly summarise the

instabilities. In this paper, partial modelling of the theory behind substrate modelling in Spice designs. In

substrate is introduced and shown to be an efficient and Section 111, partial-substrate modelling is proposed as

viable approach. The technique is validated using a test- a viable method for making substrate modelling more

bed circuit. Commonly-used noise-reduction schemes efficient and practical. In Section IV, we compare the

are briefly compared and P+ guard-rings are used to commonly-used methods for reducing substrate noise.

reduce the noise in an example circuit. In Section V, partial-substrate modelling is used in an

example circuit. P+ guard-rings are also integrated, to

reduce the noise level.

I. INTRODUCTION

Due to the rapid pace of change of silicon-device 11. SUBSTRATE MODELLING IN SPICE

technologies, circuit designs are becoming very fast and DESIGNS

compact. Their implementation is shifting away from

PCBs, and even multi-chip modules, to fully integrated The type of substrate model used in Spice designs

on-chip designs. Substrate noise, due to digital depends on the doping profile of the substrate.

switching, has emerged as a key limiting factor in the Currently in industry, there are two common profiles -

design process, with digital clocking reaching close to either a heavily-doped substrate with a thin lightly-

microwave frequencies. Signal integrity is therefore a doped epitaxial layer, or a uniformly-doped substrate.

major problem, and many designers have chosen to The former doping profile is commonly used in

remain with PCB or multi-chip designs, until substrate CMOS, and in hybrid BiCMOS, technologies and is

modelling is a more efficient and accurate process. assumed in this work.

Indirect methods have been published which can Substrate noise occurs when current is injected from

accurately, and sometimes efficiently, model the the drain into the substrate, when the NMOS device

substrate noise (see Verghese et al(l), and Miliozzi et switches. Further CMOS devices at the output drain

4 2 ) ) . However, in Spice designs, it is many times not node, provide high capacitative loading which

possible to turn to such tools, because of their expense increases the current flow into the substrate. Digital

and/or complexity. clock frequencies, using this doping profile, can reach

Efficient modelling of the substrate noise, using tools up to about lOOMHz - thus leading to high substrate

such as Spice, is therefore a fundamental requirement. noise levels.

Direct integration of the substrate throughout a design The current is injected vertically into the heavily-

has been traditionally used (Joardar(3) and (4), Su et doped substrate, as it 'seeks' the lowest resistance path.

d ( 5 ) and Verghese et a1(6)), but is impractical for Therefore, a lumped equivalent circuit can be used to

realistic designs. This is due to the way Spice represent the link between the circuit nodes and the

numerically solves for the solution values, using a substrate. Fig. 1 shows the circuit diagram for the

network topology termed the Modified Nodal NOT-gate structure, with the substrate connected to

Admittance (MNA) matrix. In unstable situations, the the CMOS devices. The bulk resistance, for a chip

numerical algorithm finds global minima from which it size of lcm x lcm, can be calculated as approximately

is unable to recover, and the simulation crashes. lo@. Because the heavily-doped substrate has such a

In this work, we propose that a first-order approximation low resistance, it is assumed to be a short circuit and is

to the substrate noise can be gained by modelling only therefore represented by a single electrical node,

selective regions of the substrate - i.e. using a partial-

Conference Publication No 445 0 IEE 1997

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109

called the bulk node. This model is sometimes referred full-substrate integration is both inefficient and

to as the single-node model. impractical. However, if only selected areas of the

The resistive link from the substrate terminal of the design - typically the high-frequency digital sections

CMOS device (either PMOS or NMOS) can be and the sensitive analogue sections - are modelled with

represented by equation (1). This equation (taken from a substrate, then much larger circuits can be modelled

(5)) represents the parallel combination of two lumped for substrate noise. To show that this method is

resistors - the area component of the total resistance, and accurate to the first-order, a test-bed circuit (shown in

the resistance due to current flow at the perimeter of the Fig. 2) has been used.

diffusion. In a P-type substrate, as is considered here, Two simulations have been run - the circuit has been

the N-wells (used for PMOS and NPN devices) form simulated with all the lines linked to the substrate (full-

capacitative links through the epitaxial layer to the bulk substrate model), and with only the high-frequency

node. These are calculated using equation (2). These digital line (100MHz) and the analogue line connected

two equations form the basis for the equivalent circuit, (partial-substrate model). Fig. 3 shows the bulk noise

linking the bulk node to the design. for the circuit with a 40MHz analogue input of

magnitude 2.5&0.1V, where the solid lines represent

the full-substrate implementation. Results were taken

for both CMOS and BJT comparators (see Fig. 3(a)

and 3(b)). As the results show, for this relatively high-

frequency analogue input, a 30% partial-substrate

model (as used here) gives an acceptable first-order

approximation to the noise levels in the substrate.

E x Area These results also show visually that the dominant

CN-we,, = (2)

T frequencies are the same for both full and partial

substrate models. This suggests that when the

substrate noise results are not accurate in the time-

E and p represent permeability of the N-well and the domain, they can be used as a reference point for noise

resistivity of the epitaxial layer, respectively. T is the reduction in the frequency domain. Further tests with

depth between the N-well and the p+ bulk (across the lower analogue input frequencies (lMHz and 10MHz)

epitaxial layer). W and L are the dimensions of the confirmed this point.

diffusion connected to the resistor and Area is the area

of the N-well. The symbols kl, k2 and 6 are 3 unknown

parameters, which are empirically calculated using

measured data from 3 test structures. This is important, IV. METHODS FOR REDUCING SUBSTRATE

so that these theoretically approximate equations show NOISE

relatively little error. For example, ( 5 ) states a 15%

error between the theoretical and measured equivalent The various methods, commonly used for substrate

lumped resistor values. noise reduction, include :

This approach, to directly modelling the substrate linked

with Spice design, is very simple and efficient. In the P+ guard rings.

digital sections, mixed-signal Spice tools (for example 0 N-well guard rings.

PSpice is used here) model the digital gates using high- Trench oxide isolation.

order behavioural models (digital primitives) which are 0 Silicon-on-oxide (SOI).

very fast and simple, but approximate. Between the 0 MOSCAPs.

analogue and digital sections, PSpice inserts A/D and 0 chip packaging (RLC) tuning.

D/A converters, where appropriate. Integration of the

bulk node requires the whole circuit to be represented in For the uniformly-doped substrate profile, (4) has

‘analogue‘ terms, so that all the device nodes can be calculated and compared the effectiveness of each

connected. method (see Fig. 4). (4) has shown that P+ guard-

rings are the most effective scheme for noise

reduction, at high frequencies. (5) has also drawn this

conclusion for the single-node model, noting that the

111. PARTIAL-SUBSTRATE MODELLING P+ guard rings need to be very close to the device for

them to be effective - typically less than the epitaxial

Spice is already known to be very limited in the size of layer’s depth. This is because the resistance path

circuits it can handle, due to numerical instabilities. becomes lower than passing to the bulk. In order to

Each CMOS (or BJT) device requires a number of insure effective use of guard-rings, a separate chip-pin

simultaneous equations to be solved, at each time point. is used which can often be difficult to implement. An

Bulk node integration causes more problems by alternative method is to bias the guard-ring using a

integrating further nodes and instabilities. Therefore, ‘quiet’ digital line.

110

From Fig. 4, it is shown that P+ guard-rings are as placement of P+ guard rings close to the digital noise

effective alone, as with both N-well guards and trench sources and sensitive analogue nodes, is an effective

oxide isolation. This is because both these latter technique commonly used to reduce the substrate noise

methods fail to reduce the current flow to the heavily- level. P+ guard-rings were integrated close to the

doped bulk. NMOS devices at the positive inputs of each of the

Silicon-on-Oxide has been used to overcome many noise comparators which were modelled with the substrate.

problems. It is most effective at low frequencies, The dashed line in Fig. 6, shows the resulting substrate

because of the dc barrier formed by the oxide. This noise. The noise level has decreased by approximately

oxide layer is capacitative and therefore loses its open- 50%, demonstrating the effectiveness of the P+ guard-

circuit circuit properties, as the frequency increases. SO1 rings.

is a non-standard process and therefore is more Also, a single MOSCAP was integrated. The resulting

expensive than other presented methods. From Fig. 4, an bulk noise (Fig. 6, dotted line) shows the delay and

ideal scheme would be a combination of P+ guard-rings smoothing, caused by the capacitor. There is a

and SOL significant reduction in noise level, which can be

Another method, which can be used to filter out the high increased by raising the capacitance value - i.e. by

frequency components of the bulk noise, is to use increasing the MOSCAP’s area. This will increase the

MOSCAPs (see (6)) - a MOSFET-type structure which attenuation of the bulk noise, at lower frequencies.

creates an effective capacitative link with the bulk. The

value of the capacitance is determined by the dimensions

of the device, using equation (2).

Also, an important factor is the tuning of the FUC VI. CONCLUSIONS

lumped values forming the bond-wires and packaging.

In (5), this area was highlighted as a very important In this paper, we have demonstrated the requirement

factor in noise minimisation. Unfortunately, non- for partial-substrate modelling. A test-bed circuit has

standard chip-packaging has been the only offered been used to validate this method. A partial substrate

solution. This is again expensive. model was used to investigate the noise and noise

levels in an example circuit, which would have not

been possible under current methodologies using a

full-substrate model. Commonly used noise-reduction

V. EXAMPLE CIRCUIT schemes have been compared and P+ guard-rings have

been used to lower the noise levels in the example

Fig. 5 shows the example circuit used to demonstrate the circuit.

benefits of partial substrate modelling. Vi, was a

40MHz sine wave, of magnitude 2.5Vf1.5V. SubSim

was used to integrate the substrate both partially and

fully, and then noise-reduction techniques were applied. REFERENCES

The circuit with a full-substrate integrated could not be

modelled, using PSpice. An approximately 30% 1. Verghese N.K. et al, 1996, “Verification

substrate model was created by linking half of the techniques for substrate coupling and their

comparators (8/16), from each of the Analogue-to- application to mixed-signal IC design”, IEEE J.

Digital converters, to the bulk node. The A/D and D/A Solid-state, 3 l , 354-365

PSpice interface structures, which PSpice automatically 2. Miliozzi P. et al, 1996, “Subwave: a methodology

inserts alongside digital primitives, were found to de- for modeling digital substrate noise injection in

stabilise the circuit when digital primitives were mixed-signal ICs”, IEEE Proc. CICC96, 385-388

modelled with the bulk node - i.e. in analogue mode. 3. Joardar K., 1996, ‘Substrate crosstalk in BiCMOS

This is a common problem which was avoidable here, mixed mode integrated circuits’, Elsevier Solid-

because the output stages of the comparators show the State Electronics, 39, 511-516

same driving characteristics as the highest frequency 4. Joardar K., 1994, “A simple approach to modeling

digital gates, in the circuit. Therefore, no digital gates cross-talk in integrated circuits”, IEEE J. Solid-

were needed to be modelled with the substrate linked. State, 29, 1212-1219

As the input frequency was sufficiently high, these 5 . Su D.K., Loinaz M.J., Masui S., Wooley B.A.,

conditions were taken as similar to that used in the test 1993, “Experimental results and modeling

circuits in Section 111, and therefore were assumed to be techniques for substrate noise in mixed-signal

accurate to the first-order. Fig. 6 (solid line) shows the integrated circuits”, IEEE J. Solid-state, 28, 420-

substrate noise level, for a full-time period of the input 429

signal. 6. Verghese N.K. et al, 1995, ‘Simulation techniques

The noise level seems uncomfortably high and SubSim and solutions for mixed-signal noise in integrated

was used to automatically integrate isolation techniques circuits”, Kluwer Academic Publishers, Boston

to reduce this level. As mentioned in Section IV,

Authorized licensed use limited to: University of Central Florida. Downloaded on November 11, 2008 at 22:19 from IEEE Xplore. Restrictions apply.

CMOS 4 0 M k

0.1

0.05

-0.05

-0.1

Input -0.15

PMOS 7 NMOS

-0.2 I I

0 5 10 15 20 25 30

time (ns)

N-well

well c

Repll

\

boCkSMebUbshateCDntOCt

bulk node BJT 4 0 M k

0.15

1

Fig. 1 : NOT-gate linked with bulk node

-0.25l I

0 5 10 15 20 25 30

time (ns)

(solid line represents full substrate, and dashed line

represents partial-substrate)

2nF

1OOMHz

50MHz 5 separate chains

25MHz

1OMHz of 5inverters

1MHz

approach

Frequency (Hz)

techniques (data taken from (4))

112

0.06

0 5 10 15 20 25

time (ns)

guard-ringsand MOSCAP integrated

Authorized licensed use limited to: University of Central Florida. Downloaded on November 11, 2008 at 22:19 from IEEE Xplore. Restrictions apply.

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