and ground to minimise ringing on the chip. All signal lines from output pulse sequence is shown in Fig.

t pulse sequence is shown in Fig. 4b. Considerable improve-

input pads to the output pads are arranged symmetrically to avoid ments in operating speed and reduction of time jitter are expected
differences in transit-time. by the use of differential data inputs. The differential output volt-
age is lVp.,,. An overall yield of 36% on five wafers was achieved
for the operating speed of 4OGbitJs. The total power dissipation is
5OOmW using a single supply voltage of 4 5 V .

Conclusion: We have designed and implemented a 2:l MUX oper-

ating up to 45Gbit/s. The high operating bit rate was achieved by
circuit design and the optimisation approach. The power con-
sumption is 500mW using a single supply voltage of 4 S V . The
high-speed performance of the 2:l MUX circuit is suitable for
application in measurement equipment and optical fibre communi-
cation systems.

Acknowledgments: The authors thank G. Weimann for encourage-

ment, M. Berroth, now with Technical University of Stuttgart, for
many years of continuous engagement, valuable advice and encour-
agement, T. Jakobus for his expert technology management, and
Fig. 2 Micrograph of 2:l M U X circuit the German Federal Ministry of Research and Technology for
fmancial support.

clock 0 IEE 1997 9 January 1997

Electronics Letters Online No: 19970364
input 1 Z . Lao, U. Nowotny, A. Thiede, V. Hurm, G. Kaufel, M. Rieger-
Motzer, W. Bronner, J. Seibel and A. Hiilsmann (Fraunhofer-Institute
of Applied Solid-state Physics, Tullastrasse 72, 0-79108 Freibuvg,
Germany)
input 2

References
190
0 1 FELDER, A., MOLLER, M., POPP, J., BOCK, .I, REST. M., REIN, H.-M., and
output TREITINGER, L.: ‘30GHz static 2.1 frequency divider and 46Gb/s
2 00 rnultiplexer/demultiplexer ICs in a 0 . 6 Si~ bipolar technology’.
2 IEEE Symp. VLSI Circuits, Tech. Dig. Papers, Kyoto, Japan,
Y 1995, pp. 117-118
>
E
-
output
2 KURIYAMA, Y , ASAKA, M., SUGIYAMA, T., IIZUKA, N., and OBARA, M.:
‘Over 40Gbit/s ultrahigh-speed multiplexer IC implemented with
high f,,, AlGaAsiGaAs HBTs’, Electron Lett., 1994, 30, (S), pp.
181
401402
90.83ns 20 91.03ns
ps /div Eza 3 OTSUJI, T , YONEYAMA, M., IMAI, Y., YAMAGUCHI, S., ENOKI, T.,
UMEDA, Y., and SANO, E.: ‘46Gbit/s multiplexer and 40Gbitis
Fig. 3 Measured 40Gbit/s performance o f 2 : l M U X
demultiplexer IC modules using InAlAs/InGaAs/InP HEMT’,
Electron Lett., 1996, 32, (7), pp. 685-686
330 ~ 4 RUNGE, K., PIERSON, R.L., ZAMPARDI, P.J., THOMAS, P.B., YU, J., and
WANG, K.C : ‘40Gbitls AlGaAsIGaAs HBT 4:1 multiplexer IC’,
Electron Lett., 1995, 31, (11), pp. 876-877
200 5 HULSMANN, A., KAUFEL, G., KOHLER, K., RAYNOR, B., SCHNEIDER, J.,
-
9 and JAKOBUS, T.: ‘E-beam direct-write in a dry-etched recess gate
=: HEMT process for GaAdAlGaAs circuits’, Jpn. J. Appl. Phys.,
E 1990, 29, (lo), pp. 2317-2320

167V
a 9091 10 91 0 1
330

Efficient modelling of eubstrate noise and

coupling in mixed-signal SPICE designs
>
E

.. I<
90L6ns 100
ps/div
91.4 6ns
R. Singh and S. Sali

Indexing terms: Mixed analogue-digital integrated circuit, SPICE

Fig. 4 Measured output eye diagrams and output pulse sequence at Substrate noise in realistically large mixed-signal SPICE designs is
45Gbit/s of 2:1 M U X in most cases impossible to model directly, owing to inherent
a Output eye diagrams instabilities. It is proposed that by modelling only the critical
b Output pulse sequence areas of the circuit, fast efficient analysis of the substrate noise
and its coupling effect on the analogue sections can be performed.

Measurement: The chips were measured on wafer using 5O!2
coplanar test probes. Fig. 3 shows the measured results for a data
rate of 4OGbitJs with an input word length of F-1.The two sin-
gle-ended data strings were aligned in time by the delay line length
to provide proper phase shifting by half the bit width. A wide
opening of the eyes is observed at the outputs. Because of the limit
in test instruments, all measurements could only be carried out
using single-ended data input. Fig. 4a shows the output eye dia-
grams of the 2:1 MUX under test at 45Gbitis. A section of the
590
Introduction; Owing to the high clocking speeds of modern digital
technology, substrate noise has emerged as a key issue for the sig-
nal integrity in mixed-signal CMOS/BiCMOS designs [l, 21. This
noise is caused by current being injected from the drain diffusion
into the substrate, when a digital gate switches 131. If the substrate
consists of a lightly-doped epitaxial layer on a heavily-doped bulk
region, as is typical in modern CMOS fabrication technologies,
the heavily-doped substrate is effectively an infinitely-conducting
metal sheet and is equivalent to a single electrical bulk node. Once
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Authorized licensed use limited to: University of Central Florida. Downloaded on November 11, 2008 at 22:21 from IEEE Xplore. Restrictions apply.
integrated into SPICE, the designer is able to study the substrate Initial tests: The circuit shown in Fig. l b has been used as a test-
noise and, if appreciable coupling to the analogue sections occurs, bed to investigate the viability and usefulness of partial-substrate
either the circuit design or implement known techniques need to
be changed to help reduce the coupling level. The link between the
modelling. vn
is a sine-wave signal of 2.5 kO.1V. Tests have been
carried out using both CMOS and BJT comparators, with input
MOSFET or BJT substrate node and the bulk node can be frequencies of 1, 10 and 40MHz. To represent the partial-sub-
approximated by lumped resistors and/or capacitors. Readers are strate model, only the high frequency digital line (CMOS,
referred to [2] for an explanation of the single-node model and 100MHz) and the comparator line are connected to the bulk node.
background details about the calculation of the relevant lumped
resistors and capacitors and their integration into the SPICE
design to give a bulk node. Fig. la illustrates the integration of the
bulk node in a CMOS NOT-gate. For realistic analysis of the sub-
strate noise, the chip package parasitics also need to be integrated.
Bond wires, package pins, and the backside substrate contact (if
present) are modelled in terms of inductances. A lumped capacitor
is used to model the link between the backside of the substrate
LA- _ -
_, A
and the package cavity [3]. 0 10 20 30 0 10 20 30
input a time,ns b

power Fig. 3 Full substrate against partial substrate, with input at lOMHz
substrate contact a CMOS lMHz
b BJT 10MHz
N-well wellC
output ground 0 .I
repil

-0 1

2nF
-0.2
a
0 10 20 30
time.ns
d ’ 10 20
192714
+
100MHz Fig. 4 Full substrate against partial suhtrate, with input at 40MHz

5 separate chains a CMOS 40MHz

of 5 inverters
b BJT 40MHz
10
Figs. 2 - 4 compare the noise generated by the partial-substrate
b )32711/
model with that of the full-substrate models. The full-substrate
Fig. 1 CMOS not-gate implementation, with bulk node connected and results are indicated by the dashed lines. The results show that for
circuit used for viability investigation of partial substrate model circuits with high-frequency analogue circuitry, such as flash AID
a CMOS not-gate implementation converters, a first-order approximation to the bulk node voltage
b Circuit used for viability investigation of partial substrate model can be made by modelling only -30% of the substrate. However,
in many situations, the partial bulk results will not provide accu-
rate results. In these cases, the information should be used as ref-
New approach: The above methodology is commonly used by erence data for any minimisation, noting that the fundamental
designers for direct modelling of the bulk node in SPICE designs. frequency of the full-substrate and partial-substrate results are the
It is simple and helpful in technologies where the single-node
same. Also, with this approach, the reliability of the partial-sub-
model is used. However, SPICE is already limited by the size of
strate model results depends on the choice of subcircuits integrated
circuit that can be simulated and substrate integration adds fur-
ther problems by introducing extra nodes and instabilities to the with the bulk node. For example, the integration of low-frequency
analysis. Also, because each ‘digital’ gate (which uses a digital digital sections alone is certain to provide misleading results.
primitive) needs to be simulated as an ‘analogue’ gate with discrete
CMOS or BiCMOS devices, bulk integration can be very dflicult
to simulate for large designs. Thus, this method cannot be used
for realistically large designs. These problems can be overcome by
modelling the bulk node connected to only part of the circuit, typ-
ically the high-frequency digital sections. We present this approach
as a viable and efficient alternative to the current methodology.
Also, the integration of the lumped components (as shown in Fig.
la) has been automated to allow full and partial-substrate bulk
integration in an efficient flexible manner. For this purpose, a
software tool (SubSim) has been developed. This tool requires no
VLSI and minimal fabrication details.

0 5 10 15 20 25
a time, ns (327121
b b time, ns 132115

Fig. 2 Full substrate against partial substrate, with input at I M H z Fig. 5 Example circuit for partial substrate modelling with results
a CMOS 1 MHz a Circuit
b BJT lMHz b Results

ELECTRONICS LETTERS 27th March 1997 Vol. 33 No. 7 59 1

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Example circuit: To show the full benefits of this new approach,
an example circuit (see Fig. 5 4 was chosen. For this design, it was
not possible to directly model the substrate noise and coupling
using SPICE, with the bulk fully integrated throughout the design.
Therefore, a partial-substrate model was used. From each of the
MD converters half (8) of the comparators were linked to the bulk
node giving an -30% partial-substrate model and V;, was a 40
MHz sine-wave signal of 2.5 +1.5V. This gave similar conditions
to that of the high-frequency tests shown in Fig. 4 and allowed us
to assume the bulk noise simulated (shown in Fig. 5b) as a first-
order approximation to the true noise. This would not be possible
in such an efficient and direct manner using current techniques. As
mentioned earlier, packaging pin inductances and bulk capacitance
are required for realistic simulation and were set to lOnH and
55pF [2], respectively.
The partial-bulk model took -4.5 times longer to simulate than
the circuit with no bulk integrated. Also, simulations showed that
SPICE becomes very unstable when trying to interface the digital
gates in the ‘analogue’mode with the digital. To avoid such insta-
bilities in this example, no digital gates were modelled with the
bulk connected. This is justified as the output stage of the CMOS
comparators show the same driving properties as a CMOS NOT-
gate. To show the effect of bulk noise on the analogue circuitry,
Fig. 5b illustrates the effective coupling to the positive input termi-
nals of one of the CMOS comparators, caused by the substrate
noise. These results give a direct view of the effect of the substrate
on the circuit’s performance and allow the designer to assess the
sensitivity of specific analogue sections to bulk noise. The results
show high levels of noise on the signal. These can be reduced by
placing P+ guard-rings around the sensitive input terminals [3].
Also, the designer can investigate possible circuit changes to try
and reduce the bulk noise, e.g. using a successive approximation
AID, if possible, which has fewer devices but also consists of
higher digital switching frequencies.
Conclusions: We have proposed partial-substrate modelling as an
efficient and viable method for calculating substrate noise, in
mixed-signal designs. A software tool, SubSim (which is available
on request), has been developed to automate the process of sub-
strate integration into SPICE netlists. Initial results have been pre-
sented to give designers an indication of the accuracy of this
approach, under varying conditions. Results are also presented
showing the substrate noise and coupling in an example circuit,
which could not be simulated with a full-substrate implementa-
tion.
0 IEE 1997 I 8 February 1997
Electronics Letters Online No: I9970388
R. Singh and S. Sali (Department of Electrical and Electronic
Engineering, M e n Court, University of Newcastle-upon-Tyne, NE1
7RU, United Kingdom)
References
,
JOARDAR, K.: ‘Substrate crosstalk in BiCMOS mixed mode
integrated circuits’, Solid-State Electron., 1996, 39, (4) pp. 51 1-516
(Elsevier Science Ltd.)
su, D.K., LOINAZ, M.J., MASUI, s., and WOOLEY, B.A.: ‘Experimental
results and modeling techniques for substrate noise in mixed-signal
integrated circuits’, ZEEE J. Solid-State Circuits, 1993, 28, (4) pp.
420-430
VERGHESE, N.K , SCHMERBECK, T.J., and ALLSTOT, D.J.:‘Simulation
techniques and solutions for mixed-signal coupling in
integrated circuits’ (Kluwer Academic Publishers, 1995), 125-
134
592
Authorized licensed use limited to: University of Central Florida. Downloaded on November 11, 2008 at 22:21 from IEEE Xplore. Restrictions apply.
8-wavelength photonic integrated 2 x 2
WDM cross-connect switch using 2 x N
phased-arraywaveguide grating (PAWG)
multi/demultiplexers
Haifeng Li, Chau-Han Lee, Wenhua Lin, S. Didde,
Yung-Jui Chen and D. Stone
Indexing terms: Integrated optics, Wavelength division multiplexing,
Optical interconnection
~~ ~~ ~~
A photonic integrated 2 x 2 WDM cross-connect switch whlch
provides full access to eight wavelength channels has been
designed and fabricated in silica on silicon substrate. The switch
consists of two novel 2 x N phased-array waveguide gratings
which are connected by a thermo-optic switch array with no
waveguide crossing. The crosstalk for the cross and bar states is
better than -20 and -15dB, respectively, with a fibre-to-fibre
insertion loss of <13dB.
Introduction: As the main areas of application of wavelength divi-
sion multiplexing (WDM) have moved from point to point com-
munication to multiaccess networks, there has been a large
increase of interest in adadrop multiplexers [I]. In particular, the
WDM cross-connect (WDM-OXC) switch, which can switch arbi-
trary wavelength components between input signals, is recognised
as being a key component for WDM access networks. in this Let-
ter, we report the design and fabrication of a novel fully photonic
integrated eight-wavelength 2x2 WDM-OXC switch with 200GHz
channel spacing. This type of wavelength switch is transparent to
signal format and bit rate and can be widely used in scalable and
reconfigurableWDM network [2] for dynamic wavelength routing.
Design: A conventional 2 x 2 WDM-OXC switch consists of four
phased-array waveguide gratings (PAWGs), two as demultiplexers
to separate the multi-wavelength components of two input WDM
signals, and the other two as multiplexers to combine the switched
(reconfigured) wavelength components back into two outputs. A 2
x 2 switch array connecting the two pairs of PAWGs allows full
reconfigurability of the multi-wavelength signals at the output
ports. in addition to its large size, this type of device is difficult to
design and is prone to process variations, in particular the central
wavelength mismatch among the PAWGs. To counter those short
comings, we have proposed an unique 2 x N PAWG design [3] to
implement the WDM-OXC with only two 2 x N PAWGs.
rn
Fig. 1 Schematic configuration of 2 X 8 PA WG
Waveguide OA is at O”, at central axis of PAWG
The schematic configuration of a 2 x 8 PAWG design is shown
in Fig. 1. The PAWG has 2 x 8 output waveguide channels,
labelled as -3A, -3B, ..., OA, OB..., 4A and 4B, with a constant
angle spacing of a between each channel. It also has two input
channels OA and OB at angle 0 and -a, respectively. The angle
spacing of a satisfies the grating equation qd(2a) = mAL, where
n,, d, m and AL are the slab waveguide index, grating pitch, grat-
ing order and wavelength channel spacing of the PAWG, respec-
tively. Here we assume N a << 1, which is satisfied in all practical
design cases. The centre wavelength of the PAWG is h, = n&h,
where nc is the channel waveguide refractive index and AL is the
ELECTRONICS LETTERS 27th March 1997 Vol. 33 No. 7